coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2020-08-24	soc/sifive: Drop unneeded empty lines	Elyes HAOUAS
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-04-05	soc/sifive: Use SPDX for GPL-2.0-only files	Angel Pons
2020-03-18	soc: Remove copyright notices	Patrick Georgi
2020-02-24	soc/{samsung,sifive}: Fix typos	Elyes HAOUAS
2019-12-19	soc/{amd,cavium,mediatek,sifive}: Remove unused <stdlib.h>	Elyes HAOUAS
2019-12-04	Change all clrsetbits_leXX() to clrsetbitsXX()	Julius Werner
2019-03-18	src/mb/sifive/hifive-unleashed: initialize Gigabit Ethernet Controller	Xiang Wang
2019-03-04	device/mmio.h: Add include file for MMIO ops	Kyösti Mälkki
2018-12-05	soc/sifive/fu540: Add helper function to get tlclk frequency	Jonathan Neuschäfer
2018-12-04	soc/sifive/fu540: Load PLL settings from a struct	Jonathan Neuschäfer
2018-12-03	soc/sifive/fu540: Simplify UART refclk calculation	Jonathan Neuschäfer
2018-09-26	soc/sifive/fu540: Document #if ENV_ROMSTAGE line	Jonathan Neuschäfer
2018-09-14	soc/sifive/fu540: Switch clock to 1GHz in romstage	Philipp Hug
2018-09-13	soc/sifive/fu540: Get SDRAM controller out of reset	Philipp Hug
2018-09-13	soc/sifive/fu540: Update clock settings according SiFive bootloader	Philipp Hug
2018-09-12	soc/sifive/fu540: Initialize PLL and clock	Philipp Hug