| Age | Commit message (Expand) | Author |
|---|---|---|
| 2018-09-10 | soc/sifive/fu540: Add driver for OTP memory | Philipp Hug |
| 2018-09-10 | soc/sifive/fu540: add CLINT support | Xiang Wang |
| 2018-09-10 | riscv: update mtime initialization | Xiang Wang |
| 2018-09-02 | riscv: separately define stack locations at different stages | Xiang Wang |
| 2018-07-18 | sifive/fu540: add empty sdram init and size functions | Philipp Hug |
| 2018-07-17 | riscv: add support for modifying compiler options | Xiang Wang |
| 2018-04-26 | src/sifive: Add the SiFive Freedom Unleashed 540 SoC | Jonathan Neuschäfer |
 |
index : coreboot | |
| Some coreboot project code with my work | vimacs |
| summaryrefslogtreecommitdiff |