| Age | Commit message (Expand) | Author |
|---|---|---|
| 2015-01-27 | vboot2: add verstage | Stefan Reinauer |
| 2015-01-01 | soc/riscv: Fix typo in src/soc/ucb/Makefile.inc. | Ronald G. Minnich |
| 2014-12-09 | UCB RISCV: Switch to DYNAMIC_CBMEM | Kyösti Mälkki |
| 2014-12-01 | Add UCB RISCV support for architecture, soc, and emulation mainboard.. | Ronald G. Minnich |
 |
index : coreboot | |
| Some coreboot project code with my work | vimacs |
| summaryrefslogtreecommitdiff |