summaryrefslogtreecommitdiff
path: root/src/soc
AgeCommit message (Collapse)Author
2020-05-01soc/intel/jasperlake: Add support to generate ACPI GPIO operationsKarthikeyan Ramasubramanian
Add support to generate ACPI operations to get/set/clear RX/TX GPIOs. BUG=b:152936541 TEST=Build and boot the mainboard. Ensure that there are no errors in the coreboot logs regarding unsupported ACPI GPIO operations. Change-Id: Ibc4846fbd9baf4f22c48c82acefed960669ed7d4 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-30soc/amd/picasso: Add support for em100Furquan Shaikh
This change enables support for em100 for Picasso platform. Since em100 requires lower SPI speed, this change configures speed in all modes as 16MHz. BUG=b:147758054,b:153675510 BRANCH=trembyle-bringup TEST=Verified that em100 works fine on trembyle. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ib5ea1fe094fda9b8dba63e94b37e61791629564f Reviewed-on: https://review.coreboot.org/c/coreboot/+/40825 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-30soc/amd/picasso: Allow mainboard to configure SPI settingsFurquan Shaikh
This change adds options to allow mainboard to configure SPI speed for different modes as well as the SPI read mode. BUG=b:153675510,b:147758054 BRANCH=trembyle-bringup TEST=Verified that SPI settings are configured correctly for trembyle. Change-Id: I24c27ec39101c7c07bedc27056f690cf2cc54951 Signed-off-by: Furquan Shaikh <furquan@google.com> Signed-off-by: Rob Barnes <robbarnes@google.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40421 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-30soc/amd/picasso: Move SPI init calls into sb_spi_init()Furquan Shaikh
This change adds a helper sb_spi_init() that makes all the required calls for configuring SPI to ROM. BUG=b:147758054,b:153675510 BRANCH=trembyle-bringup TEST=Verified that SPI configuration is correct for trembyle. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ic5b395a8d3bdab449c24b05d1b6b8777e128b5e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40824 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-30soc/amd/picasso: Introduce enums for SPI read mode and speedFurquan Shaikh
This change adds enums for spi_read_mode and spi100_speed in preparation for adding these to chip.h in follow-up CLs. This makes it easier to reference what the mainboard is expected to set for these SPI configs. BUG=b:147758054,b:153675510 BRANCH=trembyle-bringup TEST=Verified that SPI configuration is correct for trembyle. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I7f9778b41bd059a50f20993415ebd8702a1ad58e Reviewed-on: https://review.coreboot.org/c/coreboot/+/40823 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-30soc/amd/picasso: Get rid of chip.h inclusion from southbridge.hFurquan Shaikh
southbridge.h does not really need chip.h. So, this change removes the inclusion of chip.h from it. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I09c87b975ecd5f7798da8dd858be0c729aef42de Reviewed-on: https://review.coreboot.org/c/coreboot/+/40822 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-30soc/amd/common/block/smbus: Include acpimmio_map.h in sm.cFurquan Shaikh
sm.c requires acpimmio_map.h for ACPIMMIO_* macros. This change includes acpimmio_map.h in sm.c Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ia049254fa389a76bcf6538c0449229b4d856086e Reviewed-on: https://review.coreboot.org/c/coreboot/+/40821 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-30Revert "soc/mediatek/mt8183: Force retraining memory if requested"Julius Werner
This reverts commit 285975dbba8c7f3bbb9f9950e79a30bb983d5123. Reason for revert: VB2_RECOVERY_TRAIN_AND_REBOOT was never meant to have any special effect on memory training behavior. It was just supposed to be a "reboot automatically after reaching kernel verification" recovery reason. On x86 devices this was used to prime the separate recovery MRC cache in the factory (make sure it is initialized before shipping). This isn't used on Kukui anyway, but in order to make sure nobody copies this code and keep the behavior consistent between platforms, let's remove it. Change-Id: I5df5e00526e90cb573131de3c8bac9f85f4e3a5f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40623 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-30sc7180: Increase SPI flash frequency to 37.5MHzJulius Werner
It seems that all SC7180 boards we have can well handle 37.5MHz of SPI flash speed, so bump that up from the current 25MHz so that we don't leave boot speed on the table. (The next step would be 50MHz which currently doesn't work on all boards so we're not going there yet.) BUG=b:117440651 Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Id6e98fcbc89f5f3bfa408c7e8bbc90b4c92ceeea Reviewed-on: https://review.coreboot.org/c/coreboot/+/40874 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philip Chen <philipchen@google.com>
2020-04-29soc/intel/tigerlake: Check SPD is not NULL before printEric Lai
Check SPD is not NULL before print. This can prevent the system from hanging up. BUG=b:154445630 TEST=Check NULL SPD is not print. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Iccd9fce99eda7ae2b8fb1b4f3c2e635c2a428f04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40560 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-29soc/amd/picasso: Enable secure debug unlock conditionallyFurquan Shaikh
This change adds a Kconfig option PSP_UNLOCK_SECURE_DEBUG which when enabled includes secure debug unlock blobs and sets the required softfuses and options for amdfwtool. By default this is set to 'N'. BUG=b:154880818 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I47d8af67989b06242d662c77b7d9db97f624edd5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-04-29soc/amd/picasso: Use a helper to set bits in PSP_SOFTFUSEFurquan Shaikh
This change updates Makefile.inc to use a helper function set-bit to set a bit for the soft fuses. It gets rid of the different checks that were done to set soft fuses to magic values in different places. This is still not the best way to handle the fuses and instead this logic should be embedded within the amdfwtool by making it aware of specific platforms. But until that happens, we want to avoid having to add PSP_SOFTFUSE setting in various places with different values. BUG=b:154880818 TEST=Verified that the softfuse values are same with and without this change. Change-Id: I73887eb9c56ca5bb1c08d298fa818d698da1080b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40700 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-29soc/amd/picasso: Drop prompts from some Kconfig optionsFurquan Shaikh
Some of the PSP Kconfig options that are prompted to the user should really be selected by mainboard. This change updates such options to not make them user-visible any more. BUG=b:154880818 Change-Id: Iaff02fb1e720e0562b740799593322e59b022212 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-29soc/amd/picasso: Fix comment about SMU firmware2 typeFurquan Shaikh
SMU firmware2 has type 0x12 i.e. decimal 18 and not 0x18. This change updates the comment for SMU firmware2 type. Change-Id: Ia2e35aff3e460a3423f90d6ecdbe2362331391f3 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-04-29soc/amd/picasso: Drop addition of PSPTRUSTLETS_FILEFurquan Shaikh
PSPTRUSTLETS_FILE was including a binary for fTPM which according to BIOS architecture design guide is the firmware enabled TPM. Chrome OS does not really use firmware enabled TPM. Also, this is an option which is mainboard dependent. This change drops the addition of PSPTRUSTLETS_FILE to PSP directory. If this is something that is required by any mainboard, there should be a separate Kconfig to include the required files. BUG=b:154880818 TEST=Verified that trembyle still boots Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Iaa2126c879986d00c921c85fb5cb5257c7065006 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-04-29soc/amd/picasso: Drop unused OPT_PSPNVRAM_FILEFurquan Shaikh
This change drops unused option OPT_PSPNVRAM_FILE from picasso Makefile. BUG=b:154880818 TEST=Verified that trembyle still boots to OS. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I64b328a92f5ee76e198a2ad3ec72d2cc4aeb9e91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40684 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-29soc/amd/picasso: Drop addition of PUBSIGNEDKEY_FILEFurquan Shaikh
This change drops the addition of PUBSIGNEDKEY_FILE to PSP directory. This file is used to add OEM key for BIOS, however this is currently unused for upcoming zork board. In the future, if any mainboard needs this, it can be added based on some Kconfig selection. BUG=b:154880818 TEST=Verified that trembyle still boots up fine. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Icd97856a94a100898678702d99bbe29b82956004 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40682 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-29soc/amd/picasso: Disable inclusion of S0i3 firmware by defaultFurquan Shaikh
Enabling of S0i3 is a mainboard decision. This change sets the option to include S0i3 firmware by default to 'n'. BUG=b:154880818 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I5d533e317535b01efe9dd32272483296bf4fafab Reviewed-on: https://review.coreboot.org/c/coreboot/+/40681 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-29soc/amd/picasso: Disable MP2 FW inclusion by defaultFurquan Shaikh
Inclusion of MP2 firmware is optional and dependent on mainboard. Set default option for including MP2 firmware in PSP directory to 'n'. BUG=b:154880818 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I1ff7527a409d8ac7f4d30e69eafc53975b63e49b Reviewed-on: https://review.coreboot.org/c/coreboot/+/40680 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-04-29soc/amd/hda: Move HDA PCI device from DSDT to SSDTFurquan Shaikh
This change adds support in common block HDA driver to add a PCI device for HDA in SSDT and removes the HDA device from DSDT for Stoneyridge and Picasso. _INI method is still retained in stoneyridge since I am unsure why it was added. In order to support the _INI method, HDA driver makes a callback hda_soc_ssdt_quirks() to allow SoCs to add any quirks required for the HDA device. This callback is implemented by Stoneyridge to provide the _INI method which retains the same functionality for HDA device. This makes it easier to ensure that we don't accidentally make the DSDT and SSDT entries inconsistent w.r.t. ACPI name and scope. BUG=b:153858769,b:155132752 TEST=Verified that audio still works fine on Trembyle. Change-Id: I89dc46b92fdcb785bd37e18f0456935c0e57eff5 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40785 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-29soc/amd/picasso: Drop _INI method and OperationRegion for AZHD deviceFurquan Shaikh
_INI method for AZHD device for Picasso family was just copied from Stoneyridge as part of initial change. There is no evidence that this is required for Picasso. Also, removing the _INI method works perfectly fine. Thus, this change drops the _INI method for AZHD device on Picasso. Since the _INI method was the only entity using the OperationRegion fields, this change also drops the operation region. BUG=b:155132752 TEST=Verified that audio still works on Trembyle Change-Id: If42abf91ee5cd47a881b0a3b4ca1916ea5169261 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40782 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-29soc/amd/hda: Add .acpi_name() callback to HDA driverFurquan Shaikh
This change adds .acpi_name() callback to HDA driver that returns "AZHD" as the ACPI device name for HDA controller. Since this is now done by the common HDA driver, this change also removes the HDA device name returned by stoneyridge in chip.c. BUG=b:153858769 Change-Id: I89eaa799518572f3c46c7ce9ef8dd3f85daa12bb Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40781 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-29soc/amd/common/block/hda: Use tabs instead of spaces in hda.cFurquan Shaikh
This is a cosmetic change to use tabs to align hda_audio_ops and hdaaudio_driver entries. Change-Id: I8e398706cbe7087d0178b2433606f8984651c0d6 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40780 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-29soc/amd/common/block/hda: Use default pci_dev_ops_pciFurquan Shaikh
This change sets ops_pci for hda_audio_ops to default pci_dev_ops_pci and removes the custom lops_pci since the driver does not really need a custom ops_pci. BUG=b:153858769 Change-Id: I4b46e22ef556c0f49152c41a07f3c54c513ae37a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40779 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-29soc/amd/common/block/hda: Drop PCI_DEVICE_ID_AMD_FAM17H_HDA0Furquan Shaikh
PCI device PCI_DEVICE_ID_AMD_FAM17H_HDA0 does not really use the same vendor ID as PCI_VENDOR_ID_AMD. Thus, drop this device from the list of pci_device_ids[] that are supported by the common hda driver. BUG=b:153858769 Change-Id: If41dc7179e1e5b476878ee24c8a355b1cde762eb Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40778 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-29soc/amd/picasso: Add bootblock supportFelix Held
The original plan for Picasso was to combine the features of bootblock with romstage due to its unique way of coming out of reset. Early in development, all bootblock support was removed from the directory. All Picasso designs will now use a bootblock as their first stage. The reason being that it requires less invasive changes than using a hybrid romstage. Add a basic bootblock back to the directory, and compatible with the design of lib/bootblock.c. The files support RESET_VECTOR_IN_RAM and add appropriate settings in Kconfig. Make Makefile.inc calculates the size and base of bootblock from known parameters. * Future work may attempt to streamline this further, in conjunction with changes in amdfwtool. See b/154957411. BUG=b:147042464, b:153675909 Change-Id: I1d0784025f2b39f140b16f37726d4a7f36df6c6c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37490 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-29soc/intel/tigerlake: Add method to look up GPIO com ID for an indexVenkata Krishna Nimmagadda
This patch adds GPID, a helper method to look up GPIO community ID for an index. This patch also includes Intel's common GPIO ASL code. CGPM method in the common code uses the GPID method introduced in this patch. BUG=b:148892882 BRANCH=none TEST="BUILD volteer and ripto" Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com> Change-Id: Id6a00fb8adef0285d6bbc35cd5a44539bd3be6b8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40478 Reviewed-by: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-29soc/intel/common: Add method to modify GPIO community PM configVenkata Krishna Nimmagadda
This patch adds CGPM, a helper method to configure GPIO power management bits that are part of miscellaneous config. This is needed for configuration of these bits on S0ix entry and exit. BUG=b:148892882 BRANCH=none TEST="BUILD volteer and ripto" Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com> Change-Id: Iac3a269d3071eb5d4100d516249eeb5ce23c02fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/40260 Reviewed-by: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28soc/amd/common/block/sata: Add missing .ops_pci memberFurquan Shaikh
This change sets .ops_pci for sata device_operations to default pci_dev_ops_pci. It is required to set the subsystem IDs making the behavior consistent with default_pci_ops_dev. BUG=b:153858769 Change-Id: I695ac8961c92a3061beca890f5d47413b251e22b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40777 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28soc/amd/picasso: Use AMD common SATA driverFurquan Shaikh
This change enables the use of AMD common block SATA driver for Picasso. Since the common driver provides ACPI device name and PCI device for SATA in SSDT, these are removed from picasso chip.c and sb_pci0_fch.asl. BUG=b:153858769 TEST=Verified that "STCR" device is correctly reported on trembyle in SSDT. Change-Id: Icfdcf9f5e08820b565aa9fcdd0cdc7b5c9eadcd5 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40770 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28soc/amd/sata: Move SATA PCI device from DSDT to SSDTFurquan Shaikh
This change adds support in common block SATA driver to add a PCI device for SATA in SSDT and removes the SATA device from DSDT. This makes it easier to ensure that we don't accidentally make the DSDT and SSDT entries inconsistent w.r.t. ACPI name and scope. BUG=b:153858769 Change-Id: I16ac36d997496ff33c5b44ec9bd2731b2b8799eb Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40769 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28soc/amd/sata: Add .acpi_name() callback to SATA driverFurquan Shaikh
This change adds .acpi_name() callback to SATA driver that returns "STCR" as the ACPI device name for SATA. Since this is now done by the common SATA driver, this change also removes the SATA device name returned by stoneyridge in chip.c. BUG=b:153858769 Change-Id: I5e0998be3016febbb3b0e91940750a38edb6a9e7 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40768 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28soc/amd/common/block/sata: Use tabs instead of spaces in sata.cFurquan Shaikh
This is a cosmetic change to use tabs to align sata_ops and sata0_driver entries. Change-Id: Ia9eabd0cd64ecc9cbff0d4c3e3c6b71bbf29e3a9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40767 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28soc/amd/common/block/sata: Fix the condition to include sata.cFurquan Shaikh
sata.c was being added to ramstage based on the selection of CONFIG_SOC_AMD_COMMON_BLOCK_HDA which is not correct. This change fixes the error by including sata.c based on selection of CONFIG_SOC_AMD_COMMON_BLOCK_SATA. BUG=b:153858769 Change-Id: I5d23e5817872ddbb3d8d4f7dcabbaafcee4d51f4 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40766 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28soc/amd/picasso: Add UPD settings to chip.hMarshall Dawson
Add values that align with UPD settings. BUG=b:153675909 TEST=Trembyle builds and boots to payload Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I6bce44a43e57ba00d2b29cfa6249cef51e9ceabb Reviewed-on: https://review.coreboot.org/c/coreboot/+/38699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-04-28soc/intel/tigerlake: fix call to print_spd_info()Nick Vaccaro
Pointer passed to print_spd_info() from meminit.c needs to be dereferenced first, so this change dereferences it. BUG=b:154352883 TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot volteer, login to kernel and execute the following cbmem command: localhost ~ # cbmem -c | grep LPDDR4X and verify it returns "SPD: module type is LPDDR4X" Change-Id: I5ff64121f0d50947c4946e9e02460dfb7319d01a Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-04-28device: Constify struct device * parameter to acpi_inject_dsdtFurquan Shaikh
.acpi_inject_dsdt() does not need to modify the device structure. Hence, this change makes the struct device * parameter to acpi_inject_dsdt as const. Change-Id: I3b096d9a5a9d649193e32ea686d5de9f78124997 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40711 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28device: Constify struct device * parameter to acpi_fill_ssdt()Furquan Shaikh
.acpi_fill_ssdt() does not need to modify the device structure. This change makes the struct device * parameter to acpi_fill_ssdt() as const. Change-Id: I110f4c67c3b6671c9ac0a82e02609902a8ee5d5c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40710 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28soc/intel: Constify struct device * parameter to intel_igd_get_controller_infoFurquan Shaikh
intel_igd_get_controller_info() does not need to modify the device structure. Hence, this change makes the struct device * parameter to intel_igd_get_controller_info() as const. Change-Id: Ic044a80e3e2c45af6824a23f3cd0b08b94c0f279 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-04-28soc/intel: Constify struct device *param to sd_fill_soc_gpio_infoFurquan Shaikh
sd_fill_soc_gpio_info() does not need to modify device structure. Hence, this change makes the struct device * parameter to this function as const. Change-Id: I237ee9640ec64061aa9ed7c65ea21740c40b6ae2 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-04-28i2c/designware: Constify struct device * parameter to dw_i2c_soc_dev_to_busFurquan Shaikh
dw_i2c_soc_dev_to_bus() does not need to modify the device structure. Thus, this change makes the struct device * parameter to dw_i2c_soc_dev_to_bus as const. Change-Id: Ibf5c8d8127dff2ab2ccbd1f6b4f553e98e81955f Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40704 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28device: Constify struct device * parameter to write_acpi_tablesFurquan Shaikh
.write_acpi_tables() should not be updating the device structure. This change makes the struct device * argument to it as const. Change-Id: I50d013e83a404e0a0e3837ca16fa75c7eaa0e14a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-04-28soc/amd/{common,picasso}: Move GFX device from static ASL to SSDTFurquan Shaikh
This change: 1. Adds PCI device for graphics controller in ACPI SSDT tables using acpi_device_write_pci_dev(). 2. Gets rid of IGFX device from picasso acpi/northbridge.asl. This makes it easier to ensure that we don't accidentally make the DSDT and SSDT entries inconsistent w.r.t. ACPI name and scope. BUG=b:153858769 Change-Id: I3a967cdc43b74f786e645d3fb666506070851a99 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-04-28soc/amd/picasso: Use common block graphics driverFurquan Shaikh
This change selects common block graphics driver for Picasso and also adds PCI ID for Family 17h graphics controller to the graphics driver. Since the common driver provides .acpi_name() callback for graphics device, soc_acpi_name() no longer needs to provide the ACPI name for graphics device. BUG=b:153858769 Change-Id: Id3ffcb05d8f8a253a0b27407d52d7907c507cabb Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-28soc/amd/common: Add a common graphics block device driver for AMD SoCsFurquan Shaikh
This change adds a common graphics block device driver for AMD SoCs. In follow-up CLs, this driver will be utilized for Picasso. This driver is added to enable ACPI name and SSDT generation for graphics controller. BUG=b:153858769 Change-Id: I45e2b98fede41e49158d9ff9f93785a34c392c22 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-04-28amd/family17h: Add PCI device IDs for all controllers in AMD Family17hFurquan Shaikh
This change adds all the missing PCI device IDs for AMD Family 17h. IDs that were already present are updated to include _FAM17H_ in the name instead of _PCO_ and _DALI_. This ensures that the PCI IDs match the family and models as per the PPR. In cases where the controller is present only on certain models, _MODEL##H_ is also included in the name. BUG=b:153858769 BRANCH=None TEST=Verified that trembyle and dalboz still build. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ia767d32ec22f5e58827e7531c0d3d3bac90d3425 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-04-28soc/amd: Update macro name for IOMMU on AMD Family 17hFurquan Shaikh
IOMMU for AMD Family 17h Model 10-20h uses the same PCI device ID 0x15D1. This change updates the name to indicate that the PCI device ID is supported for FP5(Model 18h) and FT5(Model 20h). BUG=b:153858769 BRANCH=None TEST=Trembyle and dalboz still build. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I17c782000ed525075a3e438ed820a22d9af61a26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-04-28soc/intel/common/block/smbus: Set SPD array NULL if no DIMM presentEric Lai
Set SPD array NULL if no DIMM present. do_smbus_read_byte returns negative value if SMBus transaction fails. BUG=b:154445630,b:151702387 TEST=Check SPD is NULL if no DIMM in the slot. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ie81adbfab5bb1d5c557fe549a158cb68e26b1162 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-04-28soc/intel/cannonlake: Report driver strength by _DSM in eMMC ACPI deviceKane Chen
According to doc 621880, it suggests setting 40 ohm in byte 185 in extCSD. This commit provides _DSM method for driver to query driving strength. TEST=mmc extcsd read |grep HS_TIMING and found bit[7:4] is set to 4 BUG=b:154159888 Signed-off-by: Kane Chen <kane.chen@intel.com> Change-Id: I1b4df8b0d1d2cad3a7f521ad47ee5a4b3320c767 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-28soc/intel/cometlake: Add ucode from repoFelix Singer
On Comet Lake, add the following microcode updates from the 3rdparty repository: - 06-8e-0c (CPUID signature: 0x806ec) - 06-a6-00 (CPUID signature: 0xa0660) Tested with Clevo N141CU. Signed-off-by: Felix Singer <felixsinger@posteo.net> Change-Id: Id10b013df8ce98a4e9830782570e20fbcfad05c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-30 12:04:59 +0000