coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2018-04-25	soc/intel/apollake: add support for tracking memory details	Aaron Durbin
2018-04-25	soc/intel/common: disable paging if PAGING_IN_CACHE_AS_RAM enabled	Aaron Durbin
2018-04-25	soc/amd/stoneyridge: Add additional early LPC and SPI init	Marc Jones
2018-04-25	soc/intel/apollolake: Sync FSP PCIE NPK device as per devicetree	Shaunak Saha
2018-04-24	soc/amd/common/block/pi/amd_late_init.c: Fix illegal memory access	Richard Spiegel
2018-04-24	compiler.h: add __weak macro	Aaron Durbin
2018-04-23	drivers/spi: reduce confusion in the API	Aaron Durbin
2018-04-23	cpu/x86: move NXE and PAT accesses to paging module	Aaron Durbin
2018-04-23	soc{broadcom,imgtec,mediatek,qualcomm}: stop using spi_xfer_two_vectors	Aaron Durbin
2018-04-20	pci: Move inline PCI functions to pci_ops.h	Patrick Rudolph
2018-04-20	soc/amd/stoneyridge/include/soc/southbridge.c: Rename gpio structure	Richard Spiegel
2018-04-20	soc/intel/common: Adjust LPC Generic IO setup	Lijian Zhao
2018-04-19	soc/amd/common/block/pi/heapmanager.c: Simplify code	Richard Spiegel
2018-04-19	soc/intel/cannonlake: Set DISB after Dram init	Lijian Zhao
2018-04-19	soc/intel/apollolake: fix 'DENSITY' misspelling	Aaron Durbin
2018-04-19	soc/intel/cannonlake: Force LPC IO decode settings	Lijian Zhao
2018-04-18	soc/amd/stoneyridge/include/soc/gpio.h: Remove vendor code reference	Richard Spiegel
2018-04-17	soc/intel/apollolake: Implement _PS0/_PS3 methods for PCIe root ports	Venkateswarlu Vinjamuri
2018-04-17	soc/intel/apollolake: Configure PCIe root port #3 for GLK WiFi	Venkateswarlu Vinjamuri
2018-04-17	soc/intel/apollolake: Configure PCIe root port #1 for APL WiFi	Venkateswarlu Vinjamuri
2018-04-17	soc/intel/skylake: check DPTF_TSR0_ACTIVE_AC* in _ACx methods	Frank Wu
2018-04-16	soc/amd/stoneyridge/northbridge.c: Fix bit definitions	Richard Spiegel
2018-04-16	soc/amd/stoneyridge/lpc.c: Fix bit definitions	Richard Spiegel
2018-04-16	soc/intel/skylake: Hook up libgfxinit	Nico Huber
2018-04-16	intel/fsp_broadwell_de: Set FSP serial speed to match coreboot's	David Hendricks
2018-04-16	soc/intel/apollolake: Fix CPU address bits	Hannah Williams
2018-04-16	soc/intel/apollolake: update cache options for glk	Aaron Durbin
2018-04-16	intel/fsp_broadwell_de: Remove buggy code for SMBus clock gating	Werner Zeh
2018-04-13	soc/amd/stoneyridge: add a romstage hook for mainboards	Martin Roth
2018-04-12	include/memory_info.h: Change serial number field from 5 bytes to 4	Raul E Rangel
2018-04-11	soc/amd: Fix generating SMBIOS Type 17	Raul E Rangel
2018-04-11	src/amd/stoneyridge: Fix a typo (EDGEL_TRIG -> EDGE_TRIG)	Jonathan Neuschäfer
2018-04-11	amd/stoneyridge: Reorder temp mtrr for flash	Marshall Dawson
2018-04-11	soc/intel/common/block/cpu: Fix cpu_get_power_max	Mario Scheithauer
2018-04-11	soc/intel/common/block/gspi: Set Clock Update Bit for clock updates.	Shamile Khan
2018-04-11	Correct "MTTR" to "MTRR"	Jonathan Neuschäfer
2018-04-11	soc/intel: Remove superfluous pointers variables	Arthur Heymans
2018-04-11	soc/intel/common: Configure all possible GFX DSM memory reserve range	Subrata Banik
2018-04-10	soc/intel/apollolake: fix SPI input clock speed	Aaron Durbin
2018-04-10	soc/intel/cannonlake: Set Cannonlake I2C clock	Lijian Zhao
2018-04-10	soc/intel/common: prepare for lpss clock split	Aaron Durbin
2018-04-10	soc/amd/stoneyridege: Create AP jump structure	Richard Spiegel
2018-04-10	soc/amd: Add "halt this AP" callback to romstage	Richard Spiegel
2018-04-09	soc/intel/apollolake: Fix GPIO group to GPE mapping for GLK	Hannah Williams
2018-04-09	soc/intel/apollolake: enable MONITOR/MWAIT for GLK	Cole Nelson
2018-04-09	soc/intel/common: Add funtion to modify PAT & NXE bit	Naresh G Solanki
2018-04-09	amd/stoneyridge: Add GNB IOAPIC init	Marc Jones
2018-04-09	soc/intel/{apl,glk}: Move flush_l1d_to_l2 function to common location	Naresh G Solanki
2018-04-06	fsp_broadwell_de: Provide valid address and size for DCACHE range	Werner Zeh
2018-04-06	fsp_broadwell_de: Provide valid ACPI path names for domain and LPC	Werner Zeh