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2021-03-01soc/intel/skylake: Correct SMBUS_SLAVE_ADDR definitionAngel Pons
According to document 332691-003EN (SPT-H datasheet volume 2), the hardware defaults to 0x44, which matches what newer platforms use. Change-Id: I494587b0074ab3675c3e88676375f667e757cdf0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50941 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel: Factor out common gpe.hAngel Pons
The definitions are identical across seven platforms. Unify them. Change-Id: I32bbd0777f8ca9d0362d210b43e0ba8dd0c8d79b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50940 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel/skylake: Move soc_acpi_name()Angel Pons
Done for consistency with newer platforms. Change-Id: I1250c4514e1512e748bfc65c3f9f9da4ff1ef78e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50939 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel: Factor out identical acpigen GPIO helpersAngel Pons
Change-Id: I27f198d403f6ba05ba72ae0652da224d4cbf323a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50938 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel/skylake: Clean up SD GPIO handlingAngel Pons
This is to align with newer platforms. Change-Id: If33ea3a7835ec071be3fd060f9712c47678bd6bf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50963 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel/skylake: Remove unused macro in cpu.hAngel Pons
Change-Id: I92c9c06c606215a4bd9b44b3b4b1f0acced8a252 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50962 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel: Include gfx.asl from northbridgeAngel Pons
The iGPU is on the northbridge or system agent, not the southbridge. Change-Id: Ic63a7ad532fd1faa8e90d44bf7269040fa901757 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-01soc/amd/cezanne: Add PSP whitelist debug unlock supportRaul E Rangel
Signed-off-by: Raul E Rangel <rrangel@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibe3136682d2a9d248d5c6f26957e69013e4847ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/51078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01acpi: Move PCI functions to separate fileTim Wawrzynczak
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Idc96b99da9f9037267c0bec2c839014b13ceb8cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/51106 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/intel/common/gpio: Add gpio_routes_ioapic_irq functionTim Wawrzynczak
This function returns true if any GPIO pad is programmed to route the given IRQ to the IO-APIC. It does so by keeping track of which pads are routed to IOxAPIC and looking this up in the new function. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Iceda89cb111caa15056c204b143b4a17d59e523e Reviewed-on: https://review.coreboot.org/c/coreboot/+/49407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-01soc/intel/broadwell: Use ctdp.asl from HaswellAngel Pons
Both files are equivalent. Drop Broadwell's ctdp.asl and use Haswell's. Change-Id: Ida17d030d6022af18078321ee76b425095fe9f5c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-01mb/ocp/deltalake: Fill ECC type in romstageAngel Pons
Fill the ECC type in `struct memory_info` in romstage, and in SoC code. The SMBIOS override is unnecessary, and this is not mainboard-specific. Change-Id: I8370b3ee7d75914b895946b53923598adf87b522 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50179 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01memory_info.h: Store SMBIOS error correction typeAngel Pons
There are platforms that support error correction types other than single-bit ECC. Extend meminfo to accomodate additional ECC types. It is assumed that `struct memory_info` is packed to save space. Thus, use `uint8_t` instead of an enum type (which are usually 4 bytes wide). Change-Id: I863f8e34c84841d931dfb8d7067af0f12a437e36 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50178 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01soc/amd/common/block/acpimmio: Add fch_disable_legacy_dma_ioRaul E Rangel
Add a method to disable decoding the legacy DMA IO ports. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I979445cfa8317334e62e9ebf12256ece9f8058bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/51075 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-27soc/intel/denverton_ns: Drop `pcidev_path_on_root_debug` usageAngel Pons
Currently, this function is only invoked for the SPI device through common SoC code. Since both Intel Harcuvar and Scaleway Tagada have enabled the SPI device in the devicetree, there's no need to use the debug version of `pcidev_path_on_root`. Change-Id: I4340d5860d23c2fa230105f7a7d345c367b2b2aa Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50128 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Suresh Bellampalli <suresh.bellampalli@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-26soc/amd/cezanne/acpi: Generate MADT LAPIC NMI settingsRaul E Rangel
With this change NMI works in the kernel: ---------------- | NMI testsuite: -------------------- remote IPI: ok | local IPI: ok | -------------------- Good, all 2 testcases passed! | --------------------------------- See setup_lapic() for where this gets configured. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia391ec5a015d909462ff8aaf3cb047c6fd45fe0a Reviewed-on: https://review.coreboot.org/c/coreboot/+/50562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-02-26rk3399: clock: Fix style for rkclk_ddr_reset()Julius Werner
This function should be using the RK_CLRSETBITS() macros to access the special Rockchip write-mask registers, like the rest of our code. Also, there were already existing bit field definitions for these bits that should be used (although it makes sense to adjust them a bit to allow passing in the channel number). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: If1f5c06aabb16045d890df3bbd271f08a2cdf390 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51080 Reviewed-by: Moritz Fischer <moritzf@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-26intel/xeon_sp: Add ACPI to control GPIOMaxim Polyakov
This has been tested on the OCP Delta Lake platform. Change-Id: I07c882077eb3c035faae81641bc860e69db224b4 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39979 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao
2021-02-26rk3399: sdram: Remove obs_err variable to avoid uninitialized useJulius Werner
CB:50863 refactored the data_training() function to split out read gate training into a separate function, but in the course of this forgot to correctly initialize the local obs_err varible in the new function to 0. This means that it will be used uninitialized, and when it happens to be non-zero it makes the training process fail. Due to the convoluted control flow in the function, it seems that GCC's static analyzer couldn't pick up on this uninitialized use. The whole variable is unnecessary anyway, all it's used for is to force the function to return two lines below without doing anything with side-effects in between. This patch removes the variable and simplifies the code in all three training functions to avoid this uninitialized use issue and make everything a bit more readable. (Also restore the original pre-clang-format continuation line intendations for more readability.) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ia475d64c06f2ec1bf9295742d173ce66717b821c Reviewed-on: https://review.coreboot.org/c/coreboot/+/51079 Reviewed-by: Moritz Fischer <moritzf@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-25soc/amd/cezanne/acpi: Use IO addresses for ACPI blockRaul E Rangel
This causes the linux kernel to complain: 32/64X address mismatch in FADT/Pm1aEventBlock: 0x00000400/0x00000000FED80800 32/64X address mismatch in FADT/Pm1aControlBlock: 0x00000404/0x00000000FED80804 32/64X address mismatch in FADT/PmTimerBlock: 0x00000408/0x00000000FED80808 32/64X address mismatch in FADT/Gpe0Block: 0x00000420/0x00000000FED80814 The linux kernel also verifies that the PM Timer block only uses IO ports. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I612b6bfb67d8559127ab2ee8a2fb828493820e31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-25soc/amd/cezanne/acpi: Add globalnvs.aslRaul E Rangel
Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I53290226012d9f6c08c6adae0a633c7fd5702135 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-25soc/amd: only print CPU family and model in bootblockFelix Held
Printing this in both bootblock and romstage is redundant, since the CPU family and model aren't expected to change between bootblock and romstage entry. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reported-by: Paul Menzel <pmenzel@molgen.mpg.de> Change-Id: Id7c6aea0d8a6dac39114593584e534661faea89d Reviewed-on: https://review.coreboot.org/c/coreboot/+/51062 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-25soc/amd/cezanne/Kconfig: sort selected optionsFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I78b847c54c6cd3bfc2b947a579f4ba6b410fd2c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-25soc/intel/{skl,cnl}: Uniformize romstage.h whitespaceAngel Pons
Change-Id: Ide0e33826dd237bcd13f00400bbc8a08255b4f62 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50945 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-25mb/google/asurada: Enable RTC for event logYu-Ping Wu
BUG=b:177399759 TEST=firmware_EventLog passed on asurada BRANCH=none Change-Id: I759f9030f525fa9e34ed542198a9dba8f25909f5 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49453 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-02-25soc/amd/cezanne/acpi/pci0.asl: Add LPC deviceRaul E Rangel
Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Iadb8e77fb618e14cd9a6c0214bb3f5ae2dbc829d Reviewed-on: https://review.coreboot.org/c/coreboot/+/50922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-24soc/amd/cezanne: Add eSPI supportZheng Bao
Change-Id: I7ed24e76df3c0542b04c0f072c1eaacceea4b71f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49965 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24soc/amd/picasso/data_fabric: add missing data fabric device function 7Felix Held
The device function is missing in the PCI device table in the PPR, but is present in the hardware. Verified on a Mandolin board with PCO APU. The corresponding ticket for the PPR is DESPCSOC-6667. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie91438bc905691d443ca4e7841549d1e3bca39ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/51041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-24soc/amd/cezanne/Makefile: move setting of PSP soft fuse bit 6Felix Held
The PSP soft fuse bit 6 doesn't do what the comment above it says. See NDA document #55758 for details. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic84cf6e1eee30af92cd700dc4bf78290143bf88b Reviewed-on: https://review.coreboot.org/c/coreboot/+/51040 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-24soc/intel/*/smmrelocate.c: Sync includesAngel Pons
Since Elkhart Lake and Alder Lake use alphabetical ordering, apply that to the other platforms. Now there are only two versions of smmrelocate.c across seven different platforms. They will be unified in follow-ups. Change-Id: I5425323a6d4eecaa97916b6f2683dff57392157c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50935 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24soc/intel/*/smmrelocate.c: Uniformize cosmeticsAngel Pons
Use the same log message everywhere for consistency. Change-Id: I9d2230bc92313269470839486f6644f16e837d7c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50934 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24soc/intel/{skl,cnl}: Move smm_lock() to cpu.cAngel Pons
Looks like smmrelocate.c is nearly identical across multiple platforms. This is done to be able to deduplicate smmrelocate.c in the follow-ups. Change-Id: I2edc64c9eabc3815b12a2e3cffb03cba2228eea0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50933 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24soc/intel/{cnl,icl}: Use matching type castAngel Pons
Change-Id: Ie534a05f8d3945492ab5b817522486cdcd3c4cab Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50932 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24soc/intel/*/pmutil.c: Align cosmetics across platformsAngel Pons
Change-Id: I78d1b15deac2b80cc319dcfc5ab6bf419e2d61db Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50931 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24soc/intel/skylake/pmutil.c: Define __SIMPLE_DEVICE__Angel Pons
Change-Id: I01035ad88dc6ba702fde2c58aa0093214a57e482 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50930 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24soc/intel/skylake/pmutil: Correct soc_smi_sts_array()Angel Pons
The array was copied from Broadwell, which uses a different bit layout for SMI_STS. Copy the array from Cannonlake instead, because Skylake uses the same bit layout. This could be deduplicated in the future. Change-Id: I1c4df727c549eac6f361754d6011bf302da64c5a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50929 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24soc/intel/{adl,jsl,ehl,tgl}: Remove ITSS polarity restoreAamir Bohra
Post boot SAI PCR access to ITSS polarity regsiter is locked. Restore of ITSS polarity does not take effect anyways. Hence removing the related programming. Change-Id: I1adab45ee903b9d9c1d98a060143445c0cee0968 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-24soc/intel/alderlake: Add soc_get_xhci_usb_info() for elog supportTim Wawrzynczak
Add MMIO offsets for USB2 and USB3 port status registers, for both north (TCSS) and south (PCH) XHCI controllers; implement soc_get_xhci_usb_info() to return the appropriate entries for elog. Change-Id: I5ceb73707a0af0542a07027fd5c873a9658b19d6 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-02-24src/soc/intel/xeon_sp/cpx: Add enable IIO error masksRocky Phagura
This adds functionality to mask certain IIO errors on the root complex as recommended by HW vendor. Tested on DeltaLake mainboard. Boot to OS, verify IIO mask registers are programmed correctly. Signed-off-by: Rocky Phagura <rphagura@fb.com> Change-Id: I99f05928930bbf1f617c2d8ce31e8df2a6fd15e6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2021-02-23soc/intel/tigerlake: Remove polling for Link Active Status at resumeJohn Zhao
Tigerlake TBT only has SW CM support. The polling for "LA == 1" is not applicable for SW CM platform at the resume sequence. This change removes the pollng for "LA == 1" to improve resume performance. BUG=b:177519081 TEST=Boot to kernel and validated s0ix on Voxel board. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I886001f71bf893dc7eda98403fa4e1a3de6b958e Reviewed-on: https://review.coreboot.org/c/coreboot/+/50806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-23intel/common/block/cpu: Add APIs to get CPU info from lapic IDAamir Bohra
Add support to get core, package and thread ID from lapic ID. Implementation uses CPUID extended topology instruction to derive bit offsets for core, package and thread info in apic ID. BUG=b:179113790 Change-Id: If26d34d4250f5a88bdafacdd5d56b8882b69409e Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-02-23soc/intel/broadwell: Use cbmem_recovery()Kyösti Mälkki
For consistency with other soc/intel add s3resume variable, this helps towards unified chipset_power_state. Change-Id: I34a123f9fc13bd86264317c7762bf6e9ffd0f842 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-23soc/intel/baytrail: Use cbmem_recovery()Kyösti Mälkki
For consistency with other soc/intel add s3resume variable, this helps towards unified chipset_power_state. Change-Id: Ida04d2292aabb5a366f3400d8596ede0dee64839 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-23soc/intel/baytrail: Use a variable for s3resumeKyösti Mälkki
This helps towards unified chipset_power_state. Change-Id: I532384ad6c5b2e793ed70f31763f2c8873443816 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-22soc/intel/tigerlake: Enable end of post support in FSPNick Vaccaro
Send end of post message to CSME in FSP, by selecting EndOfPost message in PEI phase. In API mode which coreboot currently uses, sending EndOfPost message in DXE phase is not applicable. BUG=b:180755397 TEST=Extract and copy MEInfo tool from CSME Fit Kit to voxel, execute ./MEInfo | grep "BIOS Boot State" and confirm response shows BIOS Boot State to be "Post Boot". Change-Id: I1ad0d7cc06e79b2fe1e53d49c8e838f4d91af736 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51012 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-22soc/amd/picasso/acpi: Change PCI0 BAR windowRaul E Rangel
Picasso currently declares the BAR region between TOM and IO_APIC_ADDR. This region includes MMCONF. We don't want to map any PCI BARs in this region. This also matches what intel does. See soc/intel/braswell/acpi/southcluster.asl for an example. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I9474fd6ac75a7245b3c35151c38186e913219bb0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-22soc/amd/cezanne/acpi: Add pci0.aslRaul E Rangel
This differs slightly from picasso. The PCI BAR region is between TOM1 and CONFIG_MMCONF_BASE_ADDRESS. This matches what the Intel platforms are doing. It also matches what linux derives from the e820 tables: > [mem 0xd0000000-0xf7ffffff] available for PCI devices Picasso currently declares the region between TOM and IO_APIC_ADDR. This region includes MMCONF. We don't want to map any PCI BARs in this region. TEST=Boot majolica and check logs pci_bus 0000:00: root bus resource [io 0x0000-0x0cf7 window] pci_bus 0000:00: root bus resource [io 0x0d00-0xffff window] pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff] pci_bus 0000:00: root bus resource [mem 0x000c0000-0x000dffff] pci_bus 0000:00: root bus resource [mem 0xd0000000-0xf7ffffff] pci_bus 0000:00: root bus resource [bus 00-3f] Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4ff02012795e2166e3a4197071b1136727089318 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50893 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-22soc/amd: Move root complex SSDT TOM1/TOM2 generation functionRaul E Rangel
This will also be used for cezanne. Stoney also has a similar function, but it hard codes the scope path. I didn't have a device setup to test if switching to this function was a no-op. So I left it. TOM2 isn't used by any ASL, so we could remove it later. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I7c8f476a7735fea61a3244b97988e3ead3b42e79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-22soc/amd/cezanne/acpi/soc.asl: Add platform.aslRaul E Rangel
Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I01adba010bfad1bb4fdf20a8d0ab22aeeebeb10a Reviewed-on: https://review.coreboot.org/c/coreboot/+/50891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-22soc/amd/cezanne/acpi: Add MMIO devicesRaul E Rangel
The devices were copied from picasso with the following modifications: * UART{2,3} were deleted * I2C{0,1} were added * eMMC was removed since it hasn't been validated Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Iddfb975e9292785d0951dd7bb31c1997d2185abd Reviewed-on: https://review.coreboot.org/c/coreboot/+/50573 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-19 17:57:58 +0000