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2017-08-04soc/amd/stoneyridge: Use generic gpio libraryMarc Jones
Use the genric GPIO library. Add the required functions. Also, update the Kahlee mainboard dependency to match. Change-Id: I2ea562b052401efff3101f736788ca77d21e6de6 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20543 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-03soc/intel/apollolake: Skip disabled IGD deviceSubrata Banik
If IGD PCI device is disabled: 1. BAR for the device will be 0. 2. There is no need to allocate framebuffer for this device. Some early SOCs don't have GFX model fuse by default hence we need to add a check to ensure PCI device is enable. This code to avoid die inside coreboot for missing resources. Change-Id: Ied677e8c77fa7b166b016da458caad0e4702b5d8 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-03soc/intel/skylake: Skip disabled IGD deviceSubrata Banik
If IGD PCI device is disabled: 1. BAR for the device will be 0. 2. There is no need to allocate framebuffer for this device. Some early SOCs don't have GFX model fuse by default hence we need to add a check to ensure PCI device is enable. This code to avoid die inside coreboot for missing resources. Change-Id: Ic31d3e57ba730f6b569bf2cc3bdc54cb369b8caf Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-03soc/intel/cannonlake: Sort Kconfig for CannonlakeLijian Zhao
Look and feel update, sort the sequence in Kconfig. Change-Id: I41d99979d9c7d081086aac8bfef27186b37a6e70 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/20828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-03soc/intel/braswell/Kconfig: select RELOCATABLE_RAMSTAGEMatt DeVillier
Without RELOCATABLE_RAMSTAGE selected, S3 resume will hang under Linux and Windows. All other Intel SoCs have this selected by default, so this change simply corrects an omission on Braswell. TEST: boot Linux on google/cyan with and without RELOCATABLE_RAMSTAGE selected; observe that S3 resume fails without and succeeds with. Change-Id: I9071d9b4e3e3a156281d95fae059947c4c26f744 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/20819 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02soc/nvidia/tegra*: force using our headers instead of compiler's/system'sPatrick Georgi
The code doesn't include much, but when compiled outside the coreboot build (what the shipped Makefile is made for), we want to make sure that the few files it includes are controlled by us. TEST=`cd src/soc/nvidia/tegra124/lp0; make CC=arm-eabi-gcc` works Change-Id: Ic2f1e4aa4047617b048ef7ef98d71f9d540ccd74 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/20860 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-01soc/dmp/vortex86: Fix CMOS read and random RTC resetMartin Roth
The array of CMOS values that was passed into the read routine was never getting updated. GCC 7.1 gives a warning on this: error: may be used uninitialized in this function Change-Id: I2f7c9b6455761a38598467b001efb0603fd14c32 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-07-31soc/amd/stoneyridge: Add GPIO functions to romstageMarc Jones
A mainboard may access GPIO in romstage. Change-Id: Id380c6570943ce2a0bf6112d62cc91aeae283fcf Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20310 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-31soc/amd/stoneyridge: Fix GPIO bank1 control definitionMarshall Dawson
Change-Id: Ia6c7357ba0c581dc46d173f462efce181847a4e1 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20526 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-31soc/amd/stoneyridge: Move ACPI MADT table to socMarc Jones
Move the mainboard MADT tables to generic soc ACPI code. Change-Id: I49fb55b1315da8fe65421b43fc4312ed588d5ecb Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20277 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-31soc/amd/stoneyridge: Add GNVSMarc Jones
Add ACPI asl for global non-volatile storage (GNVS). Change-Id: I9ecab92181bfe60e7b6c6e91ffb9fa843345352f Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/20275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-28soc/intel/apollolake: Add CNVI and PCIE IRQs for GLKHannah Williams
Change-Id: I0387ccf6970e6169cbebd232ae210731338d0900 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/20755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-28soc/intel/skylake: Remove incorrect ME PG-status printBarnali Sarkar
As per discussion with CSME team, ME is NOT using PCI Config Space register HFSTS2 Bit 10 to update ME power-gated status. ME goes to CM0-PG state after ME device becomes idle after Bit 2 of MMIO register offset 0x800 (D0i3 Control - HECI1_D0I3C) is being set. And to retrieve the PG status of ME, one should read from the PWRMBASE+offset 0x590 (which should give the value 0xF9) and PWRMBASE+offset 0x594 (which should give the value 0xFF). But, also it needs some time for the ME FW to go to idle state and reflect these values in PWRMBASE registers after D0i3 bit is being set. This does not happen instantly. So, in coreboot, if we read the ME PG state in finalize.c, which happens just after FSP Notify phase, where actually ME D0i3 bit is set, we do not read the correct PG state values (i.e, 0xF9 and 0xFF). But, once it boots to Kernel, if we read those same registers through iotool mmio_read32 command, we get correct values. So, removing the ME PG state prints from coreboot, since it is actually showing wrong information, although ME Power Gating is successful. Change-Id: Idd31a9803b4c9db7d4bb8bbec5374583a8df0c41 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-27soc/amd/stoneyridge: Remove unused SD controllerMarshall Dawson
Remove the unused support code from the old multi-device hudson SD controller. The binaryPI blob contains the correct steps for setting up SD and the public BKDG doesn't completely document the controller. The sd.c file was using device IDs not associated with the Stoney Ridge APU. The hudson_enable() code removed was also looking for incorrect device IDs and the PM_MANUAL_RESET register doesn't behave as the source indicates. The SD default settings may be overridden. Future improvements may include a few Kconfig options and a weak call to the mainboard for overriding additional defaults. BUG=chrome-os-partner:62580062 Change-Id: I7dbd70320740e8a05e6bf16af125d67012f20674 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-27soc/amd/stoneyridge: Enable verstage supportMarshall Dawson
Add Kconfig selects for vboot and update the makefile to pick up files to be used in verstage. Change-Id: If5c439a330d687156006aec2ebaea18ff2c96b3e Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19756 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-27soc/amd/common: Convert to C_ENVIRONMENT_BOOTBLOCKMarshall Dawson
Add dedicated CAR setup and teardown functions and Kconfig options to force their inclusion into the build. The .S files are mostly duplicated code from the old cache_as_ram.inc file. The .S files use global proc names in anticipation for use with the Kconfig symbols C_ENVIRONMENT_BOOTBLOCK and POSTCAR_STAGE. Move the mainboard romstage functionality into the soc directory and change the function name to be compatible with the call from assembly_entry.S. Drop the BIST check like other devices. Move InitReset and InitEarly to bootblock. These AGESA entry points set some default settings, and release/recapture the AP cores. There are currently some early dependencies on InitReset. Future work should include: * Pull the necessary functionality from InitReset into bootblock * Move InitReset and InitEarly to car_stage_entry() and out of bootblock - Add a mechanism for the BSP to give the APs an address to call and skip most of bootblock and verstage (when available) (1) - Reunify BiosCallOuts.c and OemCustomize.c (1) During the InitReset call, the BSP enables the APs by setting core enable bits in F18F0x1DC and APs begin fetching/executing from the reset vector. The BSP waits for all APs to also reach InitReset, where they enter an endless loop. The BSP sends a command to them to execute a HLT instruction and the BSP eventually returns from InitReset. The goal would be to preserve this process but prevent APs from rerunning early code. Change-Id: I811c7ef875b980874f3c4b1f234f969ae5618c44 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-27soc/amd/stoneyridge: Convert 48Mhz enable to read/write32Marshall Dawson
Use the appropriate read32() and write32() calls. Remove unnecessary cast. Change-Id: Ib5430bdb30844d3508a09ddb77a969c0628f6c7d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-27soc/amd/stoneyridge: Clarify BAR mask in SPI baseMarshall Dawson
The format of the D14F3xA0 SPI Base_Addr register is different than a traditional BAR. Change the function to preserve any enables already in place. Change the AND mask to remove the reserved field and the enables. Change-Id: I9a43c029a2e1576703ce9cdc787d18658e9190a5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-27soc/intel/cannonlake: Correct gpio definitionLijian Zhao
The following changes have been applied for GPIO: 1. Correct port id using by GPIO community 3 for CNL-LP. 2. Correct number of doubleword for each pad from 2 to 4. Change-Id: I717d1ffba8e6722543f4cf8083fe6145fa85e184 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/20775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-27soc/intel/apollolake: Make usage of RAPL selectableMario Scheithauer
Apollo Lake SoC supports configuration of Running Average Power Limits (RAPL) for package domain. This feature is not required for all APL mainboards. According to the APL SoC EDS Vol 4 chapter 18.4 Power Limiting Control it is not necessary to enable the RAPL algorithm per default. For that reason make the RAPL configuration selectable. Change-Id: Ib737b162f72b76c15e5768859f9099e2e7ef6426 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/20759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-27soc/intel/skylake/igd.c: check return value of init_igd_opregionMartin Kepplinger
init_igd_opregion itself is supposed to return cb_err so this adds error handling, just like other implentations of write_acpi_tables do it. this had been found by coverity: *** CID 1378270: Error handling issues (CHECKED_RETURN) /src/soc/intel/skylake/igd.c: 147 in write_acpi_igd_opregion() 141 /* If IGD is disabled, exit here */ 142 if (pci_read_config16(device, PCI_VENDOR_ID) == 0xFFFF) 143 return current; 144 145 printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n"); 146 opregion = (igd_opregion_t *)current; CID 1378270: Error handling issues (CHECKED_RETURN) Calling "init_igd_opregion" without checking return value (as is done elsewhere 5 out of 6 times). 147 init_igd_opregion(opregion); 148 update_igd_opregion(opregion); 149 current += sizeof(igd_opregion_t); 150 current = acpi_align_current(current); TEST=Built Change-Id: If6f5d53037f093607d89cfe8faf193d55de7f6c4 Found-by: Coverity (CID 1378270: Error handling issues (CHECKED_RETURN)) Signed-off-by: Martin Kepplinger <martink@posteo.de> Reviewed-on: https://review.coreboot.org/20766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2017-07-26soc/intel/skylake/chip.h: Provide enum values for SataModeNico Huber
The values were verified to be correct with the KabylakeFsp0001 from github. Skylake FSP documentation disagrees so YMMV. Change-Id: I1ee04dbbed48d5376dbc24ae70753b059f2646eb Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20765 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-26soc/intel/apollolake: Update memory HOB info save functionRavi Sarawadi
SMBIOS memory HOB produced by glk FSP v52_27 has new structure members, which are not available in current apl FSP. New FSP-m header file in https://review.coreboot.org/#/c/20673/ lists new SMBIOS structure members. Break memory HOB save routine into different functions for glk and apl to accomodate new changes. Change-Id: I33c6e4f2842cebbb326b6a05436fa69e3836ffc6 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/20674 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-26intel/common/block/itss: Extend itss_irq_init() to handle IOSF 1.0Werner Zeh
Current implementation of itss_irq_init() uses 8 bit write access to IRQ routing registers which is not supported on Apollo Lake. This commit moves the register access from 8 bit to 32 bit so that this function can be used with every platform. Change-Id: I15c3c33a16329fd57f0ad7f99d720adbf300d094 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/20680 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-25soc/intel/skylake: Add IGD id for mobile Xeon with GT2Nico Huber
Change-Id: I2cd210dd0443b854294ce7ee8e267594e3ea1780 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20651 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-07-25soc/intel/skylake: soc/intel/skylake: Initialize struct member to 0Subrata Banik
As per GCC 7.1 compiler struct reset_reply is considered as uninitialized inside send_heci_reset_message function. Change-Id: Ide53a9267dfba1a00263ada1d7016a48ecb9aad8 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20739 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-25soc/intel/skylake: Skip Spi Flash Lockdown from FSPBarnali Sarkar
coreboot was setting SPI FPR register to protect the mrc_cache data range stored in flash. This programming was being done after FSP Notify 1. But, FSP was locking the SPI by setting FLOCKDN Bit during Notify phase 1, due to which coreboot was unable to protect that range. As solution, FSP introduced a new UPD SpiFlashCfgLockDown to skip the lockdown of flash on interest of bootloader. Set that UPD to 0 to skip the lockdown of FAST_SPI flash from FSP. The same is being done from coreboot after end of Post at finalize.c file. BUG=b:63049493 BRANCH=none TEST=FPR can be set properly to protect the mrc_cache range. The issue reported in the bug doesn't come when both software and hardware WP is enabled with this patch. Change-Id: I3ffca2f1b05ab2e4ef631275ef7c3a6e23e393aa Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-25soc/intel/common/block: Modify fast_spi_lock_bar functionBarnali Sarkar
Use 16bit write to avoid touching the upper two bytes that may cause write cycle to fail in case a prior transaction has not completed. This function sets the WRSDIS(Bit 11) and FLOCKDN (Bit 15) of the SPIBAR + BIOS_HSFSTS_CTL. While WRSDIS is lockable with FLOCKDN, writing both in the same cycle is guaranteed to work by design. Avoid read->modify->write operation not to clear the RW1C bits unintentionally. Change-Id: Ia7880aaca0ed64150c994d49786a0a008bbaa98b Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-24soc/intel/common/block: Add max SPI transaction time-out as 5 secBarnali Sarkar
Earlier 15ms time-out was kept for SPI transactions which was not enough for SPI Erase transactions. Increase the max time-out time to 5 secs which was present in SKL before common code. This increase in time-out won't disturb other SPI transactions like Read, Write or Read Status, since, for those it will come out of the loop once FDONE bit or FCERR bit is set. BUG=b:63959637 BRANCH=none TEST=Built and booted poppy and all SPI transactions succeeded. Change-Id: I1c015d80b33677de11755fb2097373631d1fa8c4 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-24soc/intel/skylake: Use common opregion implementationPatrick Rudolph
Enable SOC_INTEL_COMMON_GFX_OPREGION for all FSP versions. Allows to get rid of opregion.c, as it's no longer needed. Change-Id: I39190488e12917a09dbf7ee3947a33940ebc290b Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20222 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2017-07-24Update files with no newline at the endMartin Roth
Change-Id: I8febb8d74e2463622cab0313c543ceebec71fdf4 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-24Fix files with multiple newlines at the end.Martin Roth
Change-Id: Iaab26033e947cb9cf299faf1ce6d40a90a9facbe Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20704 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-22soc/intel/cannonlake: Keep variable from going out of scopeMartin Roth
The variable p was going out of scope while still being pointed to by *cpu_name. Fix coverity ID 1378215 (Pointer to local outside scope) Change-Id: I6ad7b1919104b4d97869efe5065e39c2a43de638 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2017-07-21Revert "soc/intel/cannonlake: Add postcar stage support"Martin Roth
This reverts commit 399c022a8c6cba7ad6d75fdf377a690395877611. This was merged too early. I'll repost it. Change-Id: Iabac0aaa0a16404c885875137cf34bf64bf956f7 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20686 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-21Revert "soc/intel/cannonlake: Call into FSP siliconinit"Martin Roth
This reverts commit dbe7f893c0e3fffc4e9862d872d65df752feaf9d. This was merged too early. I'll repost it. Change-Id: Ife56f45e91c0b961d0fad0e1872c6df3f9e18973 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20685 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-21soc/intel/apollolake: Add pci device id for GLK IGDHannah Williams
Change-Id: Id2c94afed8976687524a0913ea1c13aeddd98333 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/20654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-21soc/intel/cannonlake: Call into FSP siliconinitLijian Zhao
The following changes can make system call into FSP siliconinit and exit from that until payloads. 1. Add frame to call fspsinit. 2. Temporarily set all the USB OC pin to 0 to pass FSP siliconinit. Change-Id: I1c9c35ececf3c28d7a024f10a5d326700cc8ac49 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/20581 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-21soc/intel/cannonlake: Add postcar stage supportLijian Zhao
Initialize postcar frame once finish FSP memoryinit Change-Id: I888d471fa620b7fc9f8975524a31f662e1fc5079 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/20534 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-21soc/intel/skylake: Perform LPC offset read after lockdown operationSubrata Banik
This patch is to provide an additional read LPC pci offset register BIOS_CONTROL (BC) - offset 0xDC to ensure that the last write is successful. Change-Id: I308c0622d348fc96c410a04ab4081bb6af98e874 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-21common/block/fast_spi: Perform SPI offset read after lock down operationSubrata Banik
This patch is to provide an additional read SPI pci offset register BIOS_CONTROL (BC) - offset 0xDC to ensure that the last write is successful. Change-Id: I3b36c1a51ac059227631a04eb62b9a6807ed37b1 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20615 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-21soc/intel/skylake: Rectify LPC Lock Enable (LE) bit definitionSubrata Banik
LPC pci config register BIOS Control (BC) - offset 0xDC bit 1 is for Lock Down. Change-Id: I838dd946b8cdb7114f58ccc5d02159f241f0bad0 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-21soc/intel/apollolake: Bring in delta for GLK SOCHannah Williams
Change-Id: I3e76726bb77f0277ab5776ae9d3d42b7eb389fe3 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/19603 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-20soc/intel/cannonlake: Make ramstage relocatableLijian Zhao
Relocate ramstage into CBMEM. Change-Id: I0543d25d722c5872f4f139a98e5125a41cc40653 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/20640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-20soc/intel/common/gpio: add helpers for relative pin calcuationsAaron Durbin
The gpio numbers are global, but they have their respective place within each community and the group within their community. For all the calculations open coding this calculation convert them to use the helpers. Change-Id: I0423490ae1740ef59225a70fea80a7d91ac2a39a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-20soc/intel/common/gpio: fix gpi_status_get()Aaron Durbin
A pad number is passed into gpi_status_get() to determine if its associated bit is set from a generated event. However, the implementation wasn't taking into account the gpi_status_offset which dictates the starting offset for each community. Additionally, the max_pads_per_group field is per community as well -- not global. Fix the code to properly take into account the community's gpi_status_offset as well as the max_pads_per_group. Change-Id: Ia18ac6cbac31e3da3ae0ce3764ac33aa9286ac63 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20652 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hannah Williams <hannah.williams@intel.com>
2017-07-20soc/intel/skylake: Remove dead `CONFIG_PRE_GRAPHICS_DELAY`Nico Huber
`CONFIG_PRE_GRAPHICS_DELAY` was only applied on a dead code path in `igd.c` that is guarded by always selected `CONFIG_ADD_VBT_DATA_FILE`. Nobody missed it for nearly a year, plus, it's not applied on the GOP path, let's drop it. Change-Id: I0b70cce3a3f2b50cb4e72c4d927b35510ff362a2 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-20soc/intel/skylake/igd: Remove dead quirk from dead code pathNico Huber
This quirk was superseded a view lines above. Also the whole path is guarded by `CONFIG_ADD_VBT_DATA_FILE` which is always selected for nearly a year now. Change-Id: I7fc5184d6e81e4588616e0302dee410e74bdab5a Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20110 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-07-20soc/intel/skylake: Fix broken memory info HOB scanningNico Huber
It looks like this code was written with completely different semantics in mind. Controllers, channels and DIMMs are all presented in their phy- sical order (i.e. gaps are not closed). So we have to look at the whole structure and not only the first n respective entries. Change-Id: I8a9039f73f1befdd09c1fc8e17cd3f6e08e0cd47 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20650 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-20soc/intel/common/smbios: Amend debug messageNico Huber
Change-Id: I6fcee760eb32b797430eb363ce0202557b74a126 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20649 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-20intel/common/block/i2c: Fix clock programming of i2cNaresh G Solanki
When configuring i2c frequency to I2C_SPEED_FAST_PLUS, observed frequency was I2C_SPEED_FAST. This was due to incorrect register programming. TEST= Build for Soraka, I2C frequency during firmware execution was I2C_SPEED_FAST_PLUS when configured for I2C_SPEED_FAST_PLUS. Change-Id: Ib0e08afe0e1b6d8c9961d5e3039b07ada9d30aa3 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/20646 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-06 05:00:45 +0000