summaryrefslogtreecommitdiff
path: root/src/soc
AgeCommit message (Collapse)Author
2015-07-13tegra210: Fix coding style in clock.cStefan Reinauer
Change-Id: I1a8ce0b8ec291a5ddd8fdefcda24842e2a3c692d Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10861 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-13t210: Apply A57 hardware issue workaround during cpu startupFurquan Shaikh
Define custom stage_entry to apply workaround for A57 hardware issue for power on reset. It is observed that BTB contains stale data after power on reset. This could lead to unexpected branching and crashes at random intervals during the boot flow. Thus, invalidate the BTB immediately after power on reset. BUG=chrome-os-partner:41877 BRANCH=None TEST=Compiles successfully and reboot test does not crash in firmware for 10K iterations. Change-Id: Ifbc9667bc5556112374f35733192b67b64a345d2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bc7c2fec3c6b29e291235669ba9f22ff611064a7 Original-Change-Id: I1f5714074afdfee64b88cea8a394936ca848634b Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284869 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10899 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-13t210: Add TZDRAM_BASE param to BL31_MAKEARGSFurquan Shaikh
1. Make TTB_SIZE Kconfig option 2. Add Kconfig option for maximum secure component size 3. Add check in Makefile to ensure that Trustzone area is big enough to hold TTB and secure components 4. Calculate TZDRAM_BASE depending upon TTB_SIZE and TZ_CARVEOUT_SIZE BUG=chrome-os-partner:42319 BRANCH=None Change-Id: I9ceb46ceedc931826657e5a0f6fc2b1886526bf8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a425d4978a467b157ea5d71e600242ebf427b5bb Original-Change-Id: I152a38830773d85aafab49c92cef945b7c4eb62c Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284074 Original-Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10878 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-12Change #ifdef and #if defined CONFIG_ bools to #if IS_ENABLED()Martin Roth
Kconfigs symbols of type bool are always defined, and can be tested with the IS_ENABLED() macro. symbol type except string. Change-Id: Ic4ba79f519ee2a53d39c10859bbfa9c32015b19d Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10885 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-10Braswell: Move the microcode into a subdirectoryLee Leahy
Include the microcode files from the microcode subdirectory. BRANCH=none BUG=None TEST=Build and run on cyan. Change-Id: I4c8bf64d221d9ead18f1b7d6e1f01f61d88c9b25 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10873 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-07-09rk3288: Fix & vs && mix up in hdmi driverStefan Reinauer
Change-Id: I54650671adaef3bc129c662d6e972474c869afaa Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10859 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-07-09ipq8064: enable timestamp collectionVadim Bendebury
One kilobyte of SRAM needs to be allocated and the feature enabled. BRANCH=storm BUG=chrome-os-partner:34161 TEST=timer error messages do not show up in the coreboot log any more Change-Id: I1d5e5521bf9ae495d4f4f50ff017c846a8420719 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ffb9bfb0cdfab1391f8ae07669a2ab6b24d88dd7 Original-Change-Id: I60066672334db36f5e7adbef6794d7afd177d292 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/235893 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10847 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-09t210: set CAR2PMC_CPU_ACK_WIDTH to 0Yen Lin
HW team has suggested to set CAR2PMC_CPU_ACK_WIDTH to 0. BUG=None BRANCH=None TEST=Tested on Smaug; still boot to kernel Change-Id: I4d13a4048b73455b16da7a40c408c912fa97e4e7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8891a79e72af26d986af9e415149d4ca0aa6fedd Original-Change-Id: I850a6756d7743993802fb85aad403e4cbef7a661 Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/282416 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10841 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-09t210: i2c6: enable SOR_SAFE and DPAUX1 clocks for i2c6 to workYen Lin
I2C6 controller needs SOR_SAFE and DPAUX1 clocks to work. These 2 clocks are mistakenly enabled by MBIST. MBIST fix will be submitted next, which will disable these 2 clocks as initial states. Enable these 2 clocks now so I2C6 will continue to work after MBIST fix. BUG=None BRANCH=None TEST=Tested on Smaug, make sure that panel shows display (I2C6 is used to turn on backlight) Change-Id: Id47453e784d53fd6831e8d19a8d57c04c4e1f82f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 83e935f100be85e1e831a3f9f16962304f7cd7d6 Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Change-Id: If312881c94570066bdc54f0f5c48226e862bddc6 Original-Reviewed-on: https://chromium-review.googlesource.com/282415 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10840 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-08Braswell: Fix error in the warranty statementLee Leahy
Fix a cut and paste error in the warranty statement. BRANCH=none BUG=None TEST=Build and run on cyan Change-Id: If64b02f2c0fc2970932f23b99ad64beab5ab754e Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10835 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
2015-07-08memlayout: Add timestamp regions for t210 and cygnusStefan Reinauer
This is needed to make those SOCs compile with timestamps enabled. Change-Id: Iac20cb9911e1c76a18c8530385c9d7b8b46399e5 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10833 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
2015-07-07marvel/bg4cd: move timestamp init to SoC codePatrick Georgi
No need to repeat this in the mainboard code (even if there's only one right now). Change-Id: Iaa3508c27f8c38cfa343ab1d8a094ce922dec157 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/10825 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-07-07rk3288: Use timestamp region for pre-cbmem timestampsFurquan Shaikh
BUG=None BRANCH=None TEST=Compiles successfully for veyron_pinky Original-Change-Id: I3862e9bf2c32085c921adae4c1dcdf88ff0f3ff3 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/227243 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 0fabdbb05826160beb8ee8f89339b18a49e87ab8) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I4504d29a43084d4bd406626899b25903200fa6d7 Reviewed-on: http://review.coreboot.org/10740 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-07-07t132: Add timestamp collection support in t132Furquan Shaikh
Add a region TIMESTAMP to store all the timestamps starting from bootblock to end of romstage. At the end of romstage take all the timestamps in TIMESTAMP region and put it into cbmem BUG=chrome-os-partner:32973 BRANCH=None TEST=Compiles successfully and cbmem -t prints all timestamps Original-Change-Id: I856564de80589bede660ca6bc1275193f8a2fa4b Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/223110 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit b8ccf5731df9ca149a2a0661362e7745515bfe5e) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I266e46ed691ebe5f0a20ed28b89e6e74399487a1 Reviewed-on: http://review.coreboot.org/10736 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-07-07x86: Drop -Wa,--divideStefan Reinauer
Fix up all the code that is using / to use >> for divisions instead. Change-Id: I8a6deb0aa090e0df71d90a5509c911b295833cea Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10819 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-07T210: UTMIP: Correct UTMIP PLL programming as per Mark KuoTom Warren
BUG=chrome-os-partner:39603 BRANCH=none TEST=Built OK for Smaug. Change-Id: Iba170d8ad6f1dff111421fd61f71da19de57efaa Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1bf1c1442dacf45bac5d55b05ada99a2c96f2e45 Original-Change-Id: Iecf04691a637b56e2f2287ab7d4d0cdda0382421 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/282720 Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org> Original-Reviewed-by: Mark Kuo <mkuo@nvidia.com> Reviewed-on: http://review.coreboot.org/10814 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06Braswell: Update to end of June.Lee Leahy
Remove some CamelCase in acpi.c Add FSP PcdDvfsEnable configuration parameter. Add lpc_init and lpc_set_low_power routines. Remove Braswell reference to make code easier to port to another SOC. BRANCH=none BUG=None TEST=Build and run on cyan Change-Id: I5063215fc5d19b4a07f3161f76bf3d58e30f6f02 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10768 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06Braswell: Update the ACPI tablesLee Leahy
Build the GNVS pointer and add it to the DSDT. Add the opregion for GOP support. Build the SSDT entry and add it to the RSDP. The arch/x86/boot/acpi.c module adds the HPET entry, remove the acpi_create_intel_hpet routine. BRANCH=none BUG=None TEST=Build and run on cyan Change-Id: I8c7ae36b24da583928ad2532f611a855268b51f9 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10748 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06veyron*: Kill SKIP_DISPLAY_INIT_HACKDavid Hendricks
Now that we have functioning display code for all platforms, we can just get rid of this ugly hack used on non-Chromebook veyrons. BUG=none BRANCH=none TEST=built for Brain, Rialto, Mickey, Romy Change-Id: Ibe248c7cc74940811345c249d66992d74fe85fe5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9c627b087ba9fc07b4ec4a6d55d2e0203bdd4ff5 Original-Change-Id: I946eddb4e8ce1dbaa20212a2bb417e71a31b2ba3 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/282049 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/10785 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-07-06t210: MTC cleanupFurquan Shaikh
1. Correct MTC weak function definitions. 2. Correct MTC message in case no training data is present. BUG=None BRANCH=None TEST=Compiles successfully and boots to kernel prompt on smaug. Change-Id: Iba3c994982da947af3fbd2d7e9a06dff7947f2b9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ce9a4cd7d824acd0da5615b33319869f6cf1cd56 Original-Change-Id: I037439246709c8ec0ec7f12ea109cbe0ae1073ae Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/278027 Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10780 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2015-07-06rk3288: Add VOP_MODE_NONE for headless devicesDavid Hendricks
BUG=none BRANCH=none TEST=built w/ follow-up rialto patch Change-Id: I166c75673c199e8c6860f601db6759cdc3cb9c96 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ba0e0b639f12654ec54216d4366c688baa5b3253 Original-Change-Id: Id21c87ace2f4d381a1e374e1d5fe15cf1cd96da0 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/282047 Reviewed-on: http://review.coreboot.org/10779 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06rk3288: Auto-detect display.David Hendricks
We currently select either HDMI or EDP (default). This patch allows us to use HDMI as a fallback for devices that may have a display connected on either interface. It also renames the enums to sound a little more sensible in other contexts (more on that in the follow-up patches). VOP_MODE_AUTO is added to the mode enum which will make it explicit that a board can support either. In AUTO_MODE we will try EDP first and then fallback to HDMI. Other modes can be set to force a certain behavior such as HDMI-only on Mickey where it doesn't make sense to try EDP. A follow-up patch will add logic for when we explicitly don't want to probe for any display (headless devices). BUG=none BRANCH=none TEST=On veyron_danger, connected EDP and HDMI displays and saw dev mode screen appear on EDP display. Unplugged EDP and then dev mode screen showed up on HDMI. Change-Id: I22b38031c4ab3d79fbb182f7a906da1197f35543 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3f57ed3758c4e516d9fd226ad9499b102b81b423 Original-Change-Id: I352dcde16f7f3ebbf5796852b685685e541eb794 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/281076 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/10775 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06rockchip: rk3288: correct ddr 300MHz clock settinghuang lin
CRU request (24MHz * nf) / nr > 440MHz, but now ddr 300MHz setting can't meet this request, so modify it BRANCH=None BUG=None TEST=Set ddr frequency to 300MHz and boot from mickey Change-Id: I00324f5864f5ce8c1a3768268e402e0beca214c6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3d292b67245e714cb03ed35ee28c9b838d514da5 Original-Change-Id: I885704542293ed55e429a0b4b30135af7978990f Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/282445 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/10772 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-04Kconfig: Fix references to obsolete symbolsMartin Roth
These are all Kconfig symbols that have been removed or renamed. USE_PRINTK_IN_CAR was removed in commit 8c4f31b3 Drop the USE_PRINTK_IN_CAR option. It's a bogus decision... DYNAMIC_CBMEM was removed in commit e2b0affd Remove Kconfig variable that has no effect MAINBOARD_HAS_BOOTBLOCK_INIT was removed in commit 342535cc Remove Kconfig variable that has no effect CACHE_ROM was removed in commit 4337020b Remove CACHE_ROM. SMM_MODULES was removed in commit 44cbe10f smm: Merge configs SMM_MODULES and SMM_TSEG INCLUDE_MICROCODE_IN_BUILD was removed in commit eb73a218 soc/fsp_baytrail: Fix use of microcode-related Kconfig variables CAR_MIGRATION was removed in commit cbf5bdfe CBMEM: Always select CAR_MIGRATION REQUIRES_BLOB was removed in commit 70c85eab build system: Retire REQUIRES_BLOB CPU_MICROCODE_IN_CBFS was renamed to SUPPORT_CPU_UCODE_IN_CBFS in commit 66e0c4c8 - cpu: Rename CPU_MICROCODE_IN_CBFS to SUPPORT_CPU_UCODE_IN_CBFS CONSOLE_SERIAL_UART was renamed to CONSOLE_SERIAL in commit afa7b13b uart: Redefine Kconfig options CONSOLE_SERIAL8250MEM was renamed to DRIVERS_UART_8250MEM in commit afa7b13b - uart: Redefine Kconfig options Change-Id: I8952ca8c53ac2e6cec5f9c77d2f413f086bfab9d Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10766 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-07-03Kconfig whitespace cleanup: Change leading spaces to tabsMartin Roth
Change-Id: Icab6bd9f55f086da7b51ae463f34e29366d50e1a Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10764 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-02tegra124: verified boot fixupsStefan Reinauer
This patch fixes up verified boot (vboot2) configuration of all tegra 124 bases boards in the tree. Change-Id: I81f2e83821cbfdbe2a55095543e7447efdde494e Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10761 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-07-02Move baytrail & fsp_baytrail to the common IFD interface.Martin Roth
- Add the common/firmware subdir to the baytrail & fsp_baytrail makefiles and remove the code it replaces. - Update baytrail & fsp_baytrail Kconfigs to use the common code. - Update the IFD Kconfig help and prompts for the TXE vs ME. - Whittle away at the CBFS_SIZE defaults. All the fsp_baytrail platforms have their own defaults. Change-Id: I96a9d4acd6578225698dba28d132d203b8fb71a0 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10647 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-01tegra132: adjust vboot2 memlayout to make coreboot compileStefan Reinauer
romstage didn't fit in it's region anymore. Change-Id: I5a2f41cb0e0a87339dbf61906ee2060e132cc394 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10759 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
2015-07-01nvidia/tegra210: Drop unused Kconfig symbolPatrick Georgi
The deleted symbols aren't used anywhere in the coreboot tree and come from the downstream chromeos-2013.04 branch. Change-Id: I0ebc2936dff400cf8fe68794c86ac583aba2a14b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10752 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-01rockchip/rk3288: Initialize CPU in bootblockPatrick Georgi
Some basic MMU setup is required to allow unaligned memory accesses that happen across our entire codebase. Change-Id: If5a84e19a7a3e47d6009fd073b1323dfb25e6a06 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/10753 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2015-07-01tegra210: Include correct include filesStefan Reinauer
Some include files were unnecessary, and program_loading.h was missing. Change-Id: Ief3d970af5fbbb6b79da06ba3ea1d8613bfc314f Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10749 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
2015-06-30nvidia/tegra210: reserve more room for the romstage in vboot buildsPatrick Georgi
Change-Id: I11c2e270179c54af8687435ff662a509ac714505 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10733 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-06-30nvidia/tegra210: add new SoCPatrick Georgi
This includes Chrome OS downstream up to Change-Id: Ic89ed54c. Change-Id: I81853434600390d643160fe57554495b2bfe60ab Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10633 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30qualcomm/ipq806x: Fix uart in verstagePatrick Georgi
An old Kconfig symbol from Chrome OS survived into the Makefile (but is nowhere declared or used). Use the same symbol as for uart.c in the other stages. Change-Id: I7a6f1b82254e888d6f2d65d6cff87c4d546ec097 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10703 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-06-30qualcomm/ipq806x: centralize vboot configurationPatrick Georgi
vboot configuration (separate stage or not, which stage loads romstage) depends on SoC properties (eg. amount of SRAM), not on board specifics, so move this part of the configuration to the SoC. Change-Id: I70b4cd1794ddf2aba7cdae94859ea1d76ae019f4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10702 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30t210: Set UTMIP_PCOUNT_UPDN_DIV to 0Stephen Barber
Improve USB device mode stability as per suggestion by Laurent. BUG=chrome-os-partner:40929 BRANCH=smaug TEST=flash firmware and check that USB device mode is still functional. Change-Id: Id6dd7bb2e1632c512cfdf7d38a16de26a8f71471 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4298741ef4440c8bd8dac4a9f9eaa55ba560cbfb Original-Change-Id: I07d6c46d215f2ccf2c76c580f59c4fa0d519eaa5 Original-Signed-off-by: Stephen Barber <smbarber@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/278030 Original-Reviewed-by: Benson Leung <bleung@chromium.org> Original-Tested-by: Benson Leung <bleung@chromium.org> Reviewed-on: http://review.coreboot.org/10695 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-26rockchip/rk3288: complete vboot configuration and move to SoCPatrick Georgi
Where vboot verification can start, and how the code flow looks like is more a property of the SoC (and its properties, like amount of SRAM) rather than the board. Change-Id: I610153ea4ceddc226d8cc3e17a515e41fc0479cf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10662 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-26soc/intel/common: Restrict common romstage/ramstage code to FSPLee Leahy
Restrict the use of the common romstage/ramstage code to FSP 1.1 BRANCH=none BUG=None TEST=Build and run on cyan/sklrvp Change-Id: Ifbdb6b4c201560a97617e83d69bf9974f9411994 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10653 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-06-25Braswell: Remove copyright addressLee Leahy
Remove the copyright address from all of the files. BRANCH=none BUG=None TEST=None Change-Id: I7190e34e165e5652d33902440fa08253b77f4af2 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10337 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-06-25Braswell: Add Braswell SOC supportLee Leahy
Add the files to support the Braswell SOC. BRANCH=none BUG=None TEST=Build for a Braswell platform Change-Id: I968da68733e57647d0a08e4040ff0378b4d59004 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10051 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-06-25soc/intel/common/Kconfig: Fix warning & whitespaceMartin Roth
Because of a missing close quote, we have the warning: src/soc/intel/common/Kconfig:52:warning:multi-line strings not supported This was added in commit 0946ec37 -Intel Common SOC:Add romstage support The whitespace issue - using spaces instead of a leading tab was added in the same commit. Change-Id: I429c66afb5a7e10ca0e0ef619ac46722c63fb376 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10654 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2015-06-24Intel/common: Remove copyright addressLee Leahy
Remove the copyright address from the remaining files. BRANCH=none BUG=None TEST=None Change-Id: I026a0ff2bcb6c9580b45700edab446b787223007 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10336 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-06-24Intel Common SOC: Add romstage supportLee Leahy
Provide a common romstage implementation for the Intel SOCs. BRANCH=none BUG=None TEST=Build for Braswell Change-Id: I80f5f8f0f36e9023117b07d4af5c806fff8157b6 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10050 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-06-24Remove address from GPLv2 headersPatrick Georgi
Follow up for commit b890a12, some contributions brought back a number of FSF addresses, so get rid of them again. Change-Id: Icf83d5e2a3daea385af3572e9eac6b2431652c28 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10640 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-06-24Kconfig: Get rid of obsolete symbolsMartin Roth
CAR_MIGRATION was removed in commit: cbf5bdfe - CBMEM: Always select CAR_MIGRATION ALT_CBFS_LOAD_PAYLOAD was removed in commit: cf6c9cc2 - Kill ALT_CBFS_LOAD_PAYLOAD MARK_GRAPHICS_MEM_WRCOMB was removed in commit: 30fe6120 - MTRR: Mark all prefetchable resources as WRCOMB. EXTERNAL_MRC_BLOB was removed in commit: 0aede118 - Drop unused EXTERNAL_MRC_BLOB CACHE_ROM is only in Google's codebase. LID_SWITCH is only in Google's codebase. DEFAULT_POST_DEVICE_LPC is only in Sage's codebase. ROMSTAGE_RTC_INIT is only in Sage's codebase, or was never used. HUDSON_NOT_LEGACY_FREE never existed as far as I can tell. MAINBOARD_DO_EDID never existed as far as I can tell. Change-Id: I636ea7584fb47885638dbcd9ccedfafb1ca2c640 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10616 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-06-23nvidia/tegra: expose more registersTom Warren
This is in preparation for t210 Change-Id: I3e640b1f7fc583518361527dec4c3c1072c80251 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e762d4bde1a18691257453e4b87a0bb42a0a2d7c Original-Change-Id: Ida096106bb0137c07ad62d2df06628e37f0d884c Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/272754 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10632 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2015-06-23tegra: Move pinmux enum constants from tegra/pinmux.h to soc-specific pinmux.hFurquan Shaikh
Since pinmux register format has changed completely for t210, move the constants to pinmux.h in soc-specific folders. BUG=chrome-os-partner:37546 BRANCH=None TEST=Compiles successfully for ryu and foster. Change-Id: Ic1680ac50fc2619657d0c610a5dfc3fb51df7286 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7844c941a6187f884b31a8f7cc52e64268d2c732 Original-Change-Id: Icd3b2a72f3698e0772e888d9209e1fcd5d10e77d Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/260900 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10631 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2015-06-23Kconfig: Move CBFS_SIZE into Mainboard menuMartin Roth
The CBFS size is really mainboard specific, since it really depends on size of the chip on the mainboard, so it makes sense to have it in the mainboard menu along with the ROM-chip size. - Move the CBFS_SIZE definition up in src/kconfig - Move the Mainboard Menu markers out of src/mainboard/kconfig into src/Kconfig so CBFS_SIZE can live in the mainboard menu. - Add a long list setting default values to do what the chipset directories were previously defaulting the values to. This will be trimmed down in a following patch that creates a common set of IFD routines. (Who knew that kconfig supported line wrapping?) - Update the help text. Change-Id: I2b9eb5a6f7d543f57d9f3b9d0aa44a5462e8b718 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10610 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-23intel/broadwell: Fix refcode handlingPatrick Georgi
Allow adding and executing a refcode binary. Change-Id: I00e91a088a5695b42528e246d0ed642d988603e3 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/10638 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-23broadwell: fix typoPatrick Georgi
It's guarded by a non-standard configuration option, so didn't trigger. Change-Id: Ib7a9a45befcb7857edde37e20de7d65a60970882 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10623 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-15 12:48:10 +0000