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Some coreboot project code with my work
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2021-01-31
soc/amd/picasso/psp: fix check of MSR_PSP_ADDR contents
Felix Held
2021-01-31
soc/amd/*/psp: move MSR_CU_CBBCFG to common and rename to MSR_PSP_ADDR
Felix Held
2021-01-31
soc/amd/stoneyridge/southbridge: move PSP BAR hide bit to its register
Felix Held
2021-01-31
soc/amd/cezanne: add soc/cpu.h with CPUID define for Cezanne A0 stepping
Felix Held
2021-01-30
soc/intel/broadwell/pch: Drop some `config_of` uses
Angel Pons
2021-01-30
soc/intel/broadwell: Move `ramstage.c` to PCH scope
Angel Pons
2021-01-30
soc/intel/broadwell: Make `broadwell_init_pre_device` static
Angel Pons
2021-01-30
soc/intel: Replace `SA_PCIEX_LENGTH` Kconfig options
Angel Pons
2021-01-30
soc/intel/broadwell: Define and use MMCONF_BUS_NUMBER
Angel Pons
2021-01-30
soc/intel/broadwell: Use common SMBus code
Angel Pons
2021-01-30
soc/intel/{baytrail,broadwell} Fix building with refcode blobs
Angel Pons
2021-01-30
soc/amd,intel: Drop leftover GNVS includes
Kyösti Mälkki
2021-01-30
soc/amd/stoneyridge/southbridge: replace southbridge prefix with fch
Felix Held
2021-01-30
soc/amd/cezanne: add use result of acpi_is_wakeup_s3() in FSP calls
Felix Held
2021-01-30
soc/amd/picasso/chip: add missing acpi/acpi.h include
Felix Held
2021-01-30
soc/intel/common/block: Create PCIE related macros
Subrata Banik
2021-01-30
soc/intel/alderlake: Remove pch.h from SoC directory
Subrata Banik
2021-01-30
soc/amd/piasso/data_fabric: rename data_fabric_read_reg32
Felix Held
2021-01-30
soc/amd/picasso/data_fabric: factor out indirect address/index write
Felix Held
2021-01-29
soc/amd/cezanne: add empty ramstage FCH support
Felix Held
2021-01-29
soc/amd/picasso/fch: replace southbridge prefix with fch
Felix Held
2021-01-29
soc/amd/cezanne/chip: add FSP silicon init driver call
Felix Held
2021-01-29
soc/intel: Remove duplicate call to acpi_wake_source()
Kyösti Mälkki
2021-01-29
device/Kconfig: Declare MMCONF symbols' type once
Angel Pons
2021-01-29
soc/intel: Drop CMEM from GNVS
Kyösti Mälkki
2021-01-29
soc/intel/baytrail,broadwell: Use resume_from_stage_cache()
Kyösti Mälkki
2021-01-29
stage_cache: Add resume_from_stage_cache()
Kyösti Mälkki
2021-01-29
soc/amd/picasso/Kconfig: order SOC_AMD_COMMON* selections alphabetically
Felix Held
2021-01-28
soc/amd/cezanne/Kconfig: move selections in alphabetical order
Felix Held
2021-01-28
soc/amd/picasso: allow USB_PD port setting override
Chris Wang
2021-01-28
soc/intel: Remove selection of ME_REGION_ALLOW_CPU_READ_ACCESS
Sridhar Siricilla
2021-01-28
xeon_sp/cpx: Update meminfo max_capacity_mib and number_of_devices
Johnny Lin
2021-01-28
soc/amd/common: Handle I2C resource only if base address is defined
Zheng Bao
2021-01-28
mb/google/asurada: Improve boot time by raising little CPU frequency
Yidi Lin
2021-01-28
soc/mediatek/mt8192: Implement dram all channel calibration
Huayang Duan
2021-01-28
soc/mediatek/mt8192: Add mt6315_romstage_init
Yidi Lin
2021-01-28
soc/mediatek/mt8192: Add function to raise the CCI frequency
Weiyi Lu
2021-01-28
soc/intel/xeon_sp/skx: Add soc_acpi_name
Marc Jones
2021-01-28
ACPI: Separate ChromeOS NVS in ASL
Kyösti Mälkki
2021-01-28
ACPI: Declare GNVS variables globally
Kyösti Mälkki
2021-01-28
arch/x86: Remove most C_ENV_BOOTBLOCK_SIZE limits
Kyösti Mälkki
2021-01-28
arch/x86: Top-align .init in bootblock
Kyösti Mälkki
2021-01-28
cpu/x86: Rename __protected_start symbol
Kyösti Mälkki
2021-01-28
soc/intel: Refactor acpi_wake_source()
Kyösti Mälkki
2021-01-28
soc/intel: Refactor fill_acpi_wake()
Kyösti Mälkki
2021-01-28
soc/amd/picasso/acpi: Fix PCI0 MMIO window
Raul E Rangel
2021-01-28
soc/amd/picasso: fix CBFS MCACHE on Zork
Kangheui Won
2021-01-28
soc/amd/picasso/acpi: Remove DMA addresses for UARTs
Raul E Rangel
2021-01-28
soc/amd/cezanne/chip: add empty SoC device operations
Felix Held
2021-01-28
soc/amd/cezanne: compress FSP binaries in CBFS
Felix Held
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