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2019-06-28{soc,northbridge}/Kconfig: Remove unused CACHE_MRC_SIZE_KBElyes HAOUAS
Change-Id: Ie922832bc7641a44a53c0cda8d808579c66420b5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-28soc/intel/cannonlake: fix use of legacy 8254 timerMatt DeVillier
FSP sets the use of the 8254 timer via the Enable8254ClockGating UPD, which defaults to enabled, overriding what is set by coreboot. Per the FSP integration guide, this UPD needs to be disabled when a legacy OS is booted (ie, when SeaBIOS is used as the payload). Add a Kconfig option to set the UPD properly based on payload selection, and remove the existing coreboot code in lpc.c since it is either ineffective or being overridden by FSP. Test: build/boot out-of-tree WHL board with both SeaBIOS and Tianocore, ensure 8254 timer usage set correctly for each. Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Change-Id: I0e888bf754cb72093f14fc02f39bddcd6d288203 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33512 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-28qualcomm: qclib: Ensure interface table entry name is terminatedJulius Werner
This string is printed in dump_te_table() so we should make sure it's properly null-terminated. This fixes Coverity issue 1401305. Change-Id: I45827f552c2d8a4e01b50a699ac88ee457043282 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33375 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-06-26soc/intel/cannonlake/Kconfig: Don't have all variants select ↵Arthur Heymans
SOC_INTEL_CANNONLAKE This allows to use Kconfig options to differentiate between SOC variants. Change-Id: Ica11c68377e3d0dc8a8f48198e01a74d7bebe642 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33559 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-25soc/intel/dnv: Fix value of B_PCH_GPIO_RX_SCI_ROUTEPatrick Havelange
The value for that macro should be 1<<19. This is confirmed by the Intel doc and also by N_PCH_GPIO_RX_SCI_ROUTE. See Intel Atom® Processor C3000 Product Family Datasheet (February 2018) : https://www.intel.com/content/www/us/en/products/docs/processors/atom/c-series/c3000-family-datasheet.html Signed-off-by: Patrick Havelange <patrick.havelange@essensium.com> Change-Id: I808d9131032a9796d837e00ad6fb3369b792e597 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33573 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Guckian Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-24cbfstool: Drop update-fit optionPatrick Rudolph
The ifittool is used instead. Drop old code. Change-Id: I70fec5fef9ffd1ba3049badb398783f31aefb02f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-06-24Replace ENV_RAMSTAGE with ENV_PAYLOAD_LOADERSubrata Banik
This patch relying on new rule, ENV_PAYLOAD_LOADER which is set to ENV_RAMSTAGE. This approach will help to add future optimization (rampayload) in coreboot flow if required. Change-Id: Ib54ece7b9e5f281f8a092dc6f38c07406edfa5fa Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com>
2019-06-21mediatek/mt8183: support SAMSUNG and MICRON EMCP LPDDR4X DDR bootupHuayang Duan
Support SAMSUNG KMDP6001DA-B425 and MICRON MT29VZZZAD8DQKSL EMCP LPDDR4X DDR From the calibration log of MICRON MT29VZZZAD8DQKSL, we found the begin pass range of RX window earlier than with other DDR type. So need change the DQS starting offset to increase the scan range of RX window. BUG=b:80501386 BRANCH=none TEST=Boots correctly on EMCP DRAM Change-Id: I5fcc8673a2fbd7ec3a8776ab61c57f8903ddda20 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32243 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Huayang Duan <huayang.duan@mediatek.corp-partner.google.com>
2019-06-21mediatek/mt8183: fix mode register setting fail issueHuayang Duan
The mode register setting of DRAM may fail without some delay after each MR write. BUG=b:80501386 BRANCH=none TEST=Boots correctly and stress test pass on Kukui. Change-Id: I51785e90b2014994be5018bfe543245d44626242 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32284 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Huayang Duan <huayang.duan@mediatek.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-21mediatek/mt8183: enable DDR low power featuremtk11195
BUG=b:80501386 BRANCH=none TEST=Boots correctly and stress test pass on Kukui. Change-Id: Ic48580e7e5db25dc1c29dabf41c4e3816fb946d3 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Huayang Duan <huayang.duan@mediatek.corp-partner.google.com>
2019-06-21soc/intel: Provide SPD manufacturer ID and module type to SMBIOSDuncan Laurie
The DIMM manufacturing ID was not being initialized and so the DIMMs were not described in SMBIOS tables properly. The module type can also be provided, but the SMBIOS code expects SPD module type values from DDR2 so the DDR3/4 values are adjusted before sending to SMBIOS. BUG=b:134897498 BRANCH=sarien TEST=dump and compare with dmidecode BEFORE: Type: DDR4 Manufacturer: Unknown (0) Form Factor: Unknown AFTER: Type: DDR4 Manufacturer: Hynix/Hyundai Form Factor: SODIMM Change-Id: Id673e08aa6e3dad196009c3c21a3dda2f40c9e42 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33379 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-21soc/intel/cannonlake: Rename SOC_INTEL_COMMON_CANNONLAKE_BASEArthur Heymans
What it really means to do is to use different FSP headers. Change-Id: I3c75d4aac8525ab2639608fb9c1b3a9afef0e943 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33575 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-21cpu/x86/msr: Move IA32_MISC_ENABLE bits to common placeElyes HAOUAS
Change-Id: I51aa300358013cb0e76704feb2115d2a7e260f8a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31193 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Guckian Reviewed-by: Vanny E <vanessa.f.eusebio@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-21soc/intel/skylake: Clean up KconfigArthur Heymans
This does the following: - select MAINBOARD_USES_FSP2_0 on Kabylake (does not support FSP1.1) - Remove stale Kconfig option on intel/saddlebrook - select SOC_INTEL_KABYLAKE on intel/kblrvp Change-Id: I64f48eeb00150aea039d533b0ac471fdd8483b90 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33561 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-21soc/intel/skylake: Remove ROMCCFLAGSArthur Heymans
This is never used. Change-Id: I414acc38f72e206eb48cfd98214985c320862c91 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-06-21soc/intel/skylake/romstage: Increase size of postcar stackChristian Walter
I increase the size oof the postcar stack to prevent a stack overflow during the measured boot feature. After common string functions have been moved from inline into .c file (https://review.coreboot.org/c/coreboot/+/32901), I experienced a stack overflow in the postcar stage while verifiying the romstage during measured boot. To prevent this, the stack size should be increased. To play it safe, it should be increased to 8 KiB - though this is open for discussion. Change-Id: I6f1a4631bcadfb8c7d1de5bf0919e40990a65606 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-06-21mediatek/mt8183: set vproc12 voltage correctlyHsin-Hsiung Wang
The correct address for vproc12 register of sw mode is 0x1426 instead of 0x140a. BUG=b:80501386 BRANCH=none Test=Boots correctly on Kukui and see that regulator is not stuck to 1.05V anymore: grep vproc12 /sys/kernel/debug/regulator/regulator_summary Change-Id: I13867b11c44019875e0ed607343197950a3b38b2 Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33168 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-21mediatek/mt8183: Add infra group DCM settingWeiyi Lu
Add infra group DCM (Dynamic Clock Management) settings, which slows down OR gate clocks while hardware is in idle state. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui. Change-Id: I4741dfb7b984deb92171f370e5fb2593829d74c2 Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: You-Cheng Syu <youcheng@google.com>
2019-06-21mediatek: Add SPI tick_dly settingMengqi Zhang
Add spi tick_dly setting for high-speed spi xfer. BUG=b:80501386 BRANCH=none TEST=emerge-kukui coreboot; emerge-elm coreboot Change-Id: Ie49fc3efe2a4a6dcdf2a2fc4c91b47e35d4f086e Signed-off-by: Mengqi Zhang <Mengqi.Zhang@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-06-21mediatek/mt8183: Add SPI GPIO driving settingMengqi Zhang
Set SPI GPIO driving to support SPI FLASH. BUG=b:80501386 BRANCH=none TEST=emerge-kukui coreboot; emerge-elm coreboot Change-Id: I95002ec71abd751c33c089185db04ed4a8686699 Signed-off-by: Mengqi Zhang <Mengqi.Zhang@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32460 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-21mediatek/mt8183: Support RTC in ramstageYou-Cheng Syu
We need to support RTC in ramstage so that we can see correct timestamp in ChromiumOS eventlog. BUG=b:134461866 TEST='mosys eventlog list' shows correct timestamp on Kukui Change-Id: Idb0fe5c05e4ecdf0e6398e3c781c71d14f85f19b Signed-off-by: You-Cheng Syu <youcheng@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-06-21mediatek/mt8183: Add efuse calibration in auxadcjg_poxu
The values from auxadc may be incorrect if not calibrated by efuse. Without calibration, the value error range is about +/-50mv, and after being calibrated the error range is about +/-10mv. BUG=b:131391176 TEST=make clean && make test-abuild; boots on Kukui rev 2 units. BRANCH=none Change-Id: Iccd6ea0ad810c993f9b62c0974279c960f890e52 Signed-off-by: Po Xu <jg_poxu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32800 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: JG Poxu <jg_poxu@mediatek.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-21soc/intel/common/block/pcr: Remove unneded 'else'Elyes HAOUAS
'else' is not needed after a 'break' or 'return'. Change-Id: Ib3371ef6edb85a47ed734dd2ff9ce94008aa4e65 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33336 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Vlado Cibic Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-21mediatek/mt8183: Calibrate vsim2 to 2.7 VHsin-Hsiung Wang
The default voltage of vsim2 is set to 2.76V for sim card usage. In general, 2.76V of vsim2 is composed of 2.7V main voltage and 0.06V calibration voltage. However, vsim2 is used for the tx_ovdd power of display port IT6505 on the kukui board design which needs 2.7V. So we set it to 2.7V with modifying calibration value. BUG=b:126139364 BRANCH=none TEST=measure vsim2 voltage with multimeter Change-Id: I4dffdde89cbde91286d92e6c2b445f0b3d0ad2fe Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-06-20soc/intel/braswell/smbus.c: Add support for i2c mode block writeFrans Hendriks
Intel Braswell supports i2c block write using SMBus controller. smbus_i2c_block_write() is added to configure SMBus controller in i2c mode before calling do_i2c_block_write(). Add smbus.c to ramstage. BUG=N/A TEST=Verify LCD display is working on Facebook FBG-1701 Change-Id: I50c1a03f624b3ab3b987d4f3b1d15dac4374e48a Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33225 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-06-18soc/intel/skylake: Select microcode updates depending on discrete PCHArthur Heymans
Change-Id: I05e97484605306afc70c726187bda8091216c9cc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-16soc/intel/common: Fix booting issue without default IGD enabledSubrata Banik
This patch ensures to boot platform without onboard GFX (PCI B0:D2:F0) enabled from mainboard devicetree.cb. TEST=Previously platform was dying at "GMADR is not programmed!" with IGD disabled. Change-Id: I8c907ee25db4538a84890f2ccc3187afa86604b8 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33449 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-13soc/intel/{cml, whl}: Add option to skip HECI disable in SMMSubrata Banik
This patch provides an additional option to skip HECI function disabling using SMM mode for WHL and CML platform, where FSP has dedicated UPD to make HECI function disable. User to select HECI_DISABLE_USING_SMM if FSP doesn't provided dedicated UPD. Right now CNL and ICL platform will use HECI_DISABLE_USING_SMM kconfig to make HECI disable and WHL/CML has to rely on FSP to make HECI disable. Change-Id: If3b064f3c32877235916f966a01beb525156d188 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-13soc/intel/icelake: Replace PCI device LPC to ESPI as per EDSSubrata Banik
As per Icelake EDS PCI device B:D:F (0:0x1f:0) referred as ESPI, hence modify SoC code to reflect the same. This patch replaces all SoC specific PCI LPC references with ESPI except anything that touches intel common code block. Change-Id: I4990ea6d9b7b4c0eac2b3eea559f5469f086e827 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
2019-06-12vendorcode/intel/fsp/fsp2_0/cometlake: Update FSP-M/S header files as per v1155Aamir Bohra
This CL implements below changes: 1) Update FSP-M and FSP-S header files as per FSP release version 1155. 2) Update the PcdSerialIoUartNumber reference in fsp_params.c with SerialIoUartDebugControllerNumber. Change-Id: I6d412424f9f5c5d2d56b789c2fef4bdb817a3019 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32844 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-12qcom: Add i2c driverPrudhvi Yarlagadda
Add i2c driver in coreboot. Change-Id: I3d39d0325718fc5dd60da42eb2b87dcc4429bfc2 Signed-off-by: Prudhvi Yarlagadda <pyarlaga@codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-06-12{drivers,soc/intel/braswell}: Implement C_ENVIRONMENT_BOOTBLOCK supportFrans Hendriks
No C_ENVIRONMENT_BOOTBLOCK support for Braswell is available. Enable support and add required files for the Braswell Bootblock in C. The next changes are made support C_ENVIRONMENT_BOOTBLOCK: - Add car_stage_entry() function bootblock-c_entry() functions. - Specify config DCACHE_BSP_STACK_SIZE and C_ENV_BOOTBLOCK_SIZE. - Add bootblock_c_entry(). - Move init from car_soc_XXX_console_init() to bootblock_soc_XXX_Init() Removed the unused cache_as_ram_main() and weak car_XXX_XXX_console_init() BUG=NA TEST=Booting Embedded Linux on Facebook FBG-1701 Building Google Banos Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-06-11soc/amd/common: Add errors for invalid AcpiMmio accessMarshall Dawson
Add a method for the soc/amd/<product> to indicate what AcpiMmio ranges are supported. Induce a build error if soc or mainboard code is added which attempts to use an unsupported block. This patch attempts to dissuade accessing unsupported blocks without requiring the complexity of structures or reinitializing at the beginning of a new stage. TEST=boot grunt, force build errors by removing blocks in iomap.h BUG=b:131682806 Change-Id: I2121df108fd3caf07e5588bc3201bcdd8dcaaa00 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-06-10sdm845: qspi: Add Dual SPI supportJulius Werner
This patch adds support for the Dual SPI feature (SDR 2-bit in Qualcomm terminology) to the QSPI controller. Change-Id: I7aed2ccd9627f5de5dd760b418f74d56d2c031d3 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33284 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-09soc/intel/icelake: Pass FSP-M/S UPD as per ICL requirementAamir Bohra
1. Gfx stolen memory requirement for ICL GFX 2. Enable PeiGraphicsPeim support Change-Id: I22dd14249b7402873f1ac07bee164ee7bee36414 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31955 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-09soc/intel/common: Skip SoC GT programming based on CONFIG_SKIP_GRAPHICS_ENABLINGSubrata Banik
Skip GT specific programming in coreboot to support early parts without GT enable. Change-Id: I231e13367cbfbafbfb0cb4235487dbcbcae76820 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33189 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-08src/soc/intel/skylake/acpi: Remove Return for PS0/3Christian Walter
Remove the Return statement within the PS0, PS3 methods. PS0/3 are not allowed to return anything. Even an empty return will be resolved to Return(Null). In order to be conform with the specification, the code has been refactored to remove the return statements. Change-Id: I7b4820e8dd40a9169a7facce67282b8af5af67af Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33293 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-08src/soc/intel/skylake/bootblock: Add SPT C236 to PCH TableChristian Walter
Add Skylake C236 to the PCH Table. The one which was already in there is actually the CM236 and not the C236. This can be checked in datasheet: 100-series-chipset-datasheet-vol-1 p. 25. Change-Id: I435927f15e9d3219886375426b09c68632dfe3d9 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-06-07soc/intel/cannonlake: Add _DSM method for SD controllerV Sowmya
The SD controller seems to take some time after restarting the clock at 1.8V before it actually switches from 3.3V to 1.8V. Add a _DSM method that simply sleeps when switching between 3.3V and 1.8V. Otherwise, the kernel times out too quickly waiting for the card to acknowledge the 1.8V switch. The card itself is waiting until it sees the clk signal being driven at 1.8V. BUG=b:125441242 TEST=Boot Hatch with SD card and CR2 removed, observe voltage switch succeeds. Change-Id: I15090ed9f9bc90b35dfcba47c913e3d37b799d0b Signed-off-by: V Sowmya <v.sowmya@intel.com> Signef-off-by: Evan Green <evgreen@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-07soc/intel: Add some missing MCH PCIe IDsKeno Fischer
These are documented in the Intel Datasheet entitled "6th Generation Intel® Processor Datasheet for S-Platforms" "6th Generation Intel® Processor Datasheet for H-Platforms" (Volume 2) Without them, coreboot fails to properly inform the payload of the amount of available memory. Signed-off-by: Keno Fischer <keno@juliacomputing.com> Change-Id: I5b810c6415c4aa0404e5fa318d2c8db292566b8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/33286 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-06-06soc/intel/skl/graphics: Implement panel setupNico Huber
Logs from Linux' i915 suggest that not even the FSP/GOP takes proper care of this. The sequence is mostly the same as on older platforms, with a slightly different configuration of the backlight PWM. We light the panel up with 50% PWM duty cycle. This often results in an already rather high perceived brightness, but shouldn't be too blinding. Change-Id: I762a77c8df023a4c14af502af5edfeeb961da1ae Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-06-06soc/amd/common: Make biosram functions more readableMarshall Dawson
Modify the 16 and 32 bit BIOS RAM access functions that had been originally moved from stoneyridge. This was suggested in the review of 69486cac7: Create AcpiMmio functionality from stoneyridge Change-Id: I5b491da6f263cbab2b549301e16a7e19896f2428 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32932 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06soc/amd/common: Update AcpiMmio commentsMarshall Dawson
Document the AcpiMmio individual blocks better. This is in response to a request in gerrit for 69486cac7: Create AcpiMmio functionality from stoneyridge Correct comments that were inadvertently left in place from older patches. Change-Id: I4c16a866de5622e8cfbd3a08816b9d3182950d0e Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32931 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06qcs405: Enable VBOOT_MIGRATE_WORKING_DATANitheesh Sekar
Enable VBOOT MIGRATE_WORKING_DATA so that the data required by depthcharge is copied into the coreboot tables and made available to depthcharge after BOOT_IMEM is cleansed. Change-Id: I0317b73d24b07553672695998589f86677e0be64 Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33158 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-06-06soc/amd/common: Fix consistency in AcpiMmio argumentsMarshall Dawson
Change all arguments named "offset" to "reg" to match the others. These should have gone into change 69486cac7: Create AcpiMmio functionality from stoneyridge Change-Id: Ifdd00d0a5d1e03bfa68a13eeece2d2cfd56aa39d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32930 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06soc/amd/common: Clean up prototypes for AcpiMmioMarshall Dawson
Reorder the biosram prototypes to match the rest of the file. Remove prototypes for asf 32-bit functions that have not been implemented. Change-Id: Ic2663158d8a71952c26eb37f34342a6ea5e58a42 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32929 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06src/amd/stoneyridge: Move alink source to commonMarshall Dawson
Relocate the alink access functions out of stoneyridge where they were dead code. This source maintains the ability to access all register spaces, however more modern APUs define only ABCFG in the BKDGs. BUG=b:131682806 Change-Id: I5c558ccc64bd04a66399c678d43beb0a97e72f63 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32663 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06soc/amd/stoneyridge: Add ALink-AHB Bridge to iomap.hMarshall Dawson
Add the address and replace the hardcoded value in the ASL code. Change-Id: If0b99de78d8c5948e2e5f2aa50dfc2efc1bd1ba1 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32662 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06soc/amd/stoneyridge: Move sata to commonMarshall Dawson
Relocate generic sata support from stoneyridge to common/block. BUG=b:131682806 Change-Id: I4e9eddaa291e5e03f4f8d88826973c5b8ee9a1c5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32661 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06soc/amd/stoneyridge: Split sata functionalityMarshall Dawson
Separate chipset-specific source from sata_init(), and modify it to better match coreboot conventions. A subsequent patch will move the generic portion to soc/amd/common. The support for enabling port multipliers appears to have been first added for Kabini. Although missing from the documentation, the ability to affect the HBA Capabilities Register seems to remain for Stoney Ridge. Change-Id: I5dd9f613d36badc3e4d185a22b4475cb82ce187e Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32660 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-01 03:41:09 +0000