Age | Commit message (Collapse) | Author |
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per hw team's check and info from EDS, this pin needs to be pu 20K.
Otherwise SoC may not notice interrupt request from
EC over LPC because SERIRQ line is floating.
BUG=chrome-os-partner:55586
BRANCH=none
TEST=boot ok and Quanta factory verified the keyboard issue is gone
Signed-off-by: Kane Chen <kane.chen@intel.com>
Change-Id: I5b0213514ce152d4e2cecdda8786925495a0f24a
Reviewed-on: https://review.coreboot.org/15951
Tested-by: build bot (Jenkins)
Reviewed-by: Freddy Paul <freddy.paul@intel.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
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IO Standby State (IOSSTATE): The I/O Standby State defines
which state the pad should be parked in when the I/O is in a
standby state. Iosstate set to 15 means IO-Standby is ignored
for this pin (same as functional mode), So that pin keeps on
functioning in S3/S0iX.
Change-Id: Ie51ff86a2ea63fa6535407fcc2df7a137ee43e8b
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Signed-off-by: Shankar, Vaibhav <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/15776
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Upper CMOS bank is used to store the boot count. It is important to
enable it as soon as possible in bootblock.
BUG=chrome-os-partner:55473
Change-Id: I7c4f49c337c2e24a93c1e71466e2f66db04be562
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15998
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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1. skylake does not support UART over I/O. So, NO_UART_ON_SUPERIO needs
to be selected by default.
2. Move BOOTBLOCK_CONSOLE under UART_DEBUG.
3. Include bootblock/uart.c only if UART_DEBUG is selected.
Change-Id: I4e996bea2a25b3b1dfb9625d97985a9d3473561b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/16025
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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Without this patch, eDP output is non-functional pre-graphics driver
regardless of payload (SeaBIOS, Tianocore) or video init method
(VBIOS, GOP driver) and once the standard Windows Intel HD graphics
driver is loaded.
Test: Boot Windows on peppy and auron_paine, install Intel HD
Graphics driver, observe functional eDP output with full video
acceleration.
Debugging method: adjust location of call to run VBIOS within
coreboot, observed that eDP output functional if the VBIOS is run
before the power optimizer lines, broken if run afterwards.
Change-Id: I6d8252e3de396887c84533e355f41693b9ea7514
Signed-off-by: Prabal Saha <coolstarorganization@gmail.com>
Reviewed-on: https://review.coreboot.org/15261
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Select HAVE_HARD_RESET in the KCONFIG file to enable use of the
hard_reset routine.
TEST=Build and run on Galileo Gen2
Change-Id: Ib11a80b64cf1c55aec24f2576d197da9017b9751
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15992
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Fix build error caused by macro substitution in the function definition
when the Kconfig value HAVE_HARD_RESET is not selected.
src/soc/intel/common/reset.c:36:21: error: macro "hard_reset" passed 1 arguments, but takes just 0
void hard_reset(void)
^
src/soc/intel/common/reset.c:37:1: error: expected '=', ',', ';', 'asm' or '__attribute__' before '{' token
{
^
make: *** [build/bootblock/soc/intel/common/reset.o] Error 1
TEST=Build and run on Galileo Gen2
Change-Id: I793570e62a0e46cca86cc540c243e363896ceac7
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15988
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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These non-ascii & unprintable characters aren't needed.
Change-Id: I129f729f66d6a692de729d76971f7deb7a19c254
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/15977
Tested-by: build bot (Jenkins)
Reviewed-by: Omar Pakker
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: I7930d5cded290f2605d0c92a9c465a3f0c1291a2
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/15974
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Update Makefile.inc to allow MTRR display during bootblock and postcar.
TEST=Build and run on Galileo Gen2
Change-Id: If12896df46b9edfc9fff3fab3a12d2dae23517a3
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15990
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change routine name from car_state_entry to car_stage_entry.
TEST=Build and run on Galileo Gen2
Change-Id: Ifd11db3fa711f2fe52ade1c6cde94f9be1f3a652
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15857
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: I7f0d3400126d593bad8e78f95e6b9a378463b4ce
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15963
Tested-by: build bot (Jenkins)
Reviewed-by: Omar Pakker
Reviewed-by: Martin Roth <martinroth@google.com>
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(pci_read_config32(...) > 14) & 0x3 looks rather unusual (and prevents
"case 3" below from ever happening)
Change-Id: Id90655c39ff53da9569441278bbf73497d643480
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1293139
Reviewed-on: https://review.coreboot.org/15965
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Testing for "devfn < 0" on an unsigned doesn't work, and i2c_bus_to_devfn
returns an int (with -1 for "error"), so use int for devfn.
Change-Id: I7d1cdb6af4140f7dc322141c0c018d8418627434
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1357450, #1357449
Reviewed-on: https://review.coreboot.org/15964
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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The bootblock gets slightly too big, so adjust the space assigned to
it.
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
BUG=none
BRANCH=none
TEST=emerge-nyan coreboot works again.
Change-Id: Ib44d98692ae88c7cd3610c8e643d7d48ac858161
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 4b9038b018ed7a26fbce01d982b22166b328de37
Original-Change-Id: If494e49fb60c11e01ca780c84036ebf24459628c
Original-Reviewed-on: https://chromium-review.googlesource.com/346492
Original-Reviewed-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Queue: Stefan Reinauer <reinauer@google.com>
Original-Tested-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://review.coreboot.org/15950
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Change EVT3 board id to 5.
BUG=chrome-os-partner:55320
TEST=None.
BRANCH=None
Change-Id: I020be47e1fdbf886c7c471d7fdcace1537875b6d
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 63bd6541055172765c31a9b1220a24d4e3604cdc
Original-Change-Id: I21a8764ff95892430944778f4898d2f1d4c97fd7
Original-Signed-off-by: Kan Yan <kyan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/362391
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://review.coreboot.org/15949
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This removes the newlines from all files found by the new
int-015-final-newlines script.
Change-Id: I65b6d5b403fe3fa30b7ac11958cc0f9880704ed7
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/15975
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Use the ACPI generator for creating the Chrome OS gpio
package. Each mainboard has its own list of Chrome OS
gpios that are fed into a helper to generate the ACPI
external OIPG package. Additionally, the common
chromeos.asl is now conditionally included based on
CONFIG_CHROMEOS.
Change-Id: I1d3d951964374a9d43521879d4c265fa513920d2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15909
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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This is required for using GPE_* macros in devicetree.cb.
BUG=chrome-os-partner:55670
Change-Id: I8f6f536df96cf8145bb0c03ec413fb2f374301b5
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15946
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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1. Enable SoC SD_CMD/D* signals pull-down of 20k when SD-card
is removed. When SD-card is disconnected, the pull-down is
disabled.
2. Provide path for weak leakage from buffers of SD_CMD/D* signal
to be grounded. Thus dropping voltage on the SD_CMD/D* signals to ~0V.
BUG=chrome-os-partner:54421
TEST=no power leakage when SDCard isn't inserted on skylake platform
Change-Id: I567199b172841125f8916a61a76005cfdaa62eb8
Signed-off-by: Zhuo-hao.Lee <zhuo-hao.lee@intel.com>
Reviewed-on: https://review.coreboot.org/15910
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Do not pass VBT table to fsp in normal mode and S3 resume so that
PEIM GFX will not get initialized.
Change-Id: Iab7be3cceb0f80ae0273940b36fdd9c41bdb121e
Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
Reviewed-on: https://review.coreboot.org/14575
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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When enabling the controller ODT, the controller vref needs to
correspond with the ODT value and DQ drive strength.
BRANCH=none
BUG=chrome-os-partner:54871
TEST=run "stressapptest -M 1024 -s 1000" on kevin board and pass
Original-Commit-Id: a7251c72b87d9f149b68d086c3252f1c668e0e80
Original-Change-Id: I7e54b3473f68a382208a0fb0b0600552fe6390ad
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/358762
Original-Commit-Ready: Dan Shi <dshi@chromium.org>
Original-Tested-by: Caesar Wang <wxt@rock-chips.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Squashed with:
rockchip/rk3399: Halt if we get an invalid odt or drv value
When we were pushing the updated sdram.c to coreboot.org, the compiler
there found that we were not initializing vref_value_dq in all code
possible code paths.
This patch updates those code paths to halt the system.
Branch=none
Bug=none
Test=Built with coreboot.org toolchain and verified that the compile
errors were gone.
Change-Id: I0ad4207dc976236d64b6cdda58d10bcfbe1fde11
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362726
Reviewed-by: Julius Werner <jwerner@chromium.org>
Change-Id: I22a0cef6f12d9aae2ea4dcb99e7ebdd788f2cdd1
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/15812
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Add new UPDs for Fspm and Fsps. Update headers to make new UPDs
available for use. New UPDs enable various memory and trace funtionality
options as well as support for zero sized IBB region.
BUG=chrome-os-partner:55513
BRANCH=none
TEST=built and tested with no regressions
Change-Id: Id1573baaa306ed4fe4353df5f27e5963cb1a76e6
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/15815
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This patch updates dptf variable in gnvs based on device
configuration by reading the device tree structure.
BUG=chrome-os-partner:53096
TEST=Verify that the thermal zones are enumerated
under /sys/class/thermal in Amenia and Reef board.
Navigate to /sys/class/thermal, and verify that a
thermal zone of type TCPU exists there.
Change-Id: I8ab34cdc94d8cdc840b02347569a9f07688e92cd
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15620
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch adds apollolake soc specific change. DPTF
ASL files are now in src/soc/intel/common so that
they can be reused but different soc can have different values
e.g., for skylake cpu soc thermal reporting device is at
Bus 0, Device 4, Function 0 while for apollolake it is Bus 0, Device 0,
Function 1. This patch adds a dptf asl file in soc directory where we
can define all values which can change across soc's and can be
included in mainboard dptf asl.
BUG=chrome-os-partner:53096
TEST=In Amenia and Reef board verify that the thermal zones are
enumerated under /sys/class/thermal in Amenia and Reef board.
Navigate to /sys/class/thermal, and verify that a thermal
zone of type TCPU exists there.
Change-Id: I888260a9c799d36512411a769f26dd30cf8d5788
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15619
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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This patch adds the common ASL code for Intel
platforms. This is the basic ASL needed to add support
for DPTF controlled devices. We are moving
these commmon ASL files to src/soc/intel/common/acpi as
these are same codes used in all Intel platforms and
hence no need to duplicate.
BUG=chrome-os-partner:53096
TEST=Verify that the thermal zones are enumerated
under /sys/class/thermal. Navigate to
/sys/class/thermal, and verify that a thermal
zone of type TCPU exists there.
Change-Id: I01078382a9008263c6ad99f6bf07558885af6a63
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15093
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Including the terminating null, 17 characters were being written to the
field, overwriting the a byte of the size field.
Fortunately, the size was updated soon after this.
Fixes coverity warning 1229570 - Destination buffer too small.
Change-Id: I39285a9283dd9a17d638afe5b2755c7e420d7698
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/15889
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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FSP temp ram init was getting called earlier from ROMCC bootblock.
Now with C entry boot block, it is needed to locate FSP header and
call FspTempRamInit.
Hence add fsp 1_1 driver code to locate FSP Temp ram and execute.
BUG=chrome-os-partner:55357
BRANCH=none
TEST=Built kunimitsu and ensure FSP Temp Ram Init return success
Change-Id: If40b267777a8dc5c473d1115b19b98609ff3fd74
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/15787
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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List of activity performing in this patch
- early PCH programming
- early SA programming
- early CPU programming
- mainborad early gpio programming for UART and SPI
- car setup
- move chipset programming from verstage to post console
BUG=chrome-os-partner:55357
BRANCH=none
TEST=Built and booted kunimitsu till POST code 0x34
Change-Id: If20ab869de62cd4439f3f014f9362ccbec38e143
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/15785
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Enable cache-as-ram and prepare for c entry in bootblock.
BUG=chrome-os-partner:55357
BRANCH=none
TEST=Built and booted kunimitsu till POST code 0x2A
Credits-to: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I3412216cdf8ef7e952145943d33c3f07949da3c1
Reviewed-on: https://review.coreboot.org/15784
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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BUG=chrome-os-partner:55639
Change-Id: I7a536bc1cab51e7c942b2e0e48dfe18d8de08a6e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15925
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
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BUG=chrome-os-partner:55639
Change-Id: Ie38cdbec513e2bb66e276399c8b4490cbe34a747
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15924
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
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BUG=chrome-os-partner:55639
Change-Id: Idbad4f8763be18002907a62be755b2fdf7e479ec
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15895
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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BUG=chrome-os-partner:55639
Change-Id: Ie859ec3ff682e91a4d7d38d3c3cd6badf7385431
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15894
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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With VBOOT_VERIFY_FIRMWARE separated from CHROMEOS, move recovery and
developer mode check functions to vboot. Thus, get rid of the
BOOTMODE_STRAPS option which controlled these functions under src/lib.
BUG=chrome-os-partner:55639
Change-Id: Ia2571026ce8976856add01095cc6be415d2be22e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15868
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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VBOOT_VERIFY_FIRMWARE should be independent of CHROMEOS. This allows use
of verified boot library without having to stick to CHROMEOS.
BUG=chrome-os-partner:55639
Change-Id: Ia2c328712caedd230ab295b8a613e3c1ed1532d9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15867
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Currently, coreboot performs an erase of the entire MRC cache region on
flash if there is a version mismatch for the MRC data. Instead of doing
that, store the new MRC data in the next available slot, if there is
enough space available in the cache region.
BUG=chrome-os-partner:55699
Change-Id: Ib24a94f0a47c79941ed9f60095360ae3aad5540b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15915
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The monitor/mwait is broken on Apollolake. So use ACPI legacy
mwait IO redirection as a work around
BUG=chrome-os-partner:55110
Change-Id: I2e1834130d9586b4310466d3549d19bf427ffe24
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/15890
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Quark does not support the rdmsr and wrmsr instructions. In this case
use a SOC specific routine to support the setting of the MTRRs. Migrate
the code from FSP 1.1 to be x86 CPU common.
Since all rdmsr/wrmsr accesses are being converted, fix the build
failure for quark in lib/reg_script.c. Move the soc_msr_x routines and
their depencies from romstage/mtrr.c to reg_access.c.
TEST=Build and run on Galileo Gen2
Change-Id: Ibc68e696d8066fbe2322f446d8c983d3f86052ea
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15839
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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All mainboards (nyans) utilizing the cache_policy option
has it set to DCACHE_WRITETHROUGH. This option is for setting
the framebuffer's cache attribute. However, this option is
reliant on an architecture-specific enumeration. Just remove
the option and use DCACHE_WRITETHROUGH across the board. If
someone wants to reconfigure it at a later date one can
introduce a non-architecture specific option.
Change-Id: I6a0848231f5e28d36ec2d56b239bed67619fe5a7
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15838
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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We set this driving control to prevent signal attenuation caused by
LVDS DRV termination.
When DA_LVDSTX_PWR_ON is not set, LVSH has no power and LVDS DRV
termination status is unknown (floating). This creates a chance that
MIPI output would be influenced. The DSI's LP signal will be half
voltage attenuation. There will be no display on panel.
When DA_LVDSTX_PWR_ON is set, LVSH and LVDS DRV termination are
effective and termination is fixed OFF. The DSI won't be influenced.
We only need to set this register once, so we set it here to prevent
repeatedly setting in the kernel when the system goes to recovery mode.
BUG=chrome-os-partner:55296
BRANCH=none
TEST=build pass elm and show ui
Change-Id: Ie3ccf6fb611dd5a1e2c02b7825d42a92e61268c0
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 0d25a27f300acc4b65a894110d3ee0cc9676cd12
Original-Change-Id: Ie71f9cc41924787be8539c576392034320b57a49
Original-Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/360850
Original-Commit-Ready: jitao shi <jitao.shi@mediatek.com>
Original-Tested-by: jitao shi <jitao.shi@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/15807
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This allows the board to save the recovery request in case of unexpected
reboots caused by FSP.
With recovery module in vboot handling the saving of recovery reason
across reboots, there is no need to have special fsp reset handling
under soc.
BUG=chrome-os-partner:55431
Change-Id: I0b7ce14868a322072d3e60c1dae43f211b43fdbf
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15804
Tested-by: build bot (Jenkins)
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This allows the board to save the recovery request in case of unexpected
reboots caused by FSP.
BUG=chrome-os-partner:55431
Change-Id: If71802d2cba52a426f4c2db90d6c5384ed03ce68
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15803
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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As shown in testing, if CA use 34.3ohms drive strength, it leads
to an overshoot. To fix this, change the drive strength to 48 ohms.
BRANCH=none
BUG=chrome-os-partner:54871
TEST=run "stressapptest -M 1024 -s 1000" on kevin board and pass
Change-Id: I8666474fc18391da14a3338611f962f2f08f36d0
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: fbc1c13f9ab808fc907b2e3f9bde1d09f92980f1
Original-Change-Id: I231f5b1bd45ff262686fbacbaf119a8a57fad27b
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/358761
Original-Commit-Ready: Dan Shi <dshi@chromium.org>
Original-Tested-by: Caesar Wang <wxt@rock-chips.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/15811
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Fix the board ID handling.
Recovery switch and WP status GPIO has been reassigned in board rev3.
Configure related GPIOs based on Board ID.
BUG=chrome-os-partner:55320
TEST=Verified GPIO assignment for Rev.1 board.
BRANCH=None
Change-Id: Id8e1ba1c039f8b5b503f0da038e5cfc84b72678f
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: d295ab514e31d9ebd1b77e0af9b769e64cbf567e
Original-Change-Id: I6d3d5df2e9017f7845edc3cd0b2c19ad7c58a97c
Original-Signed-off-by: Kan Yan <kyan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/361393
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://review.coreboot.org/15809
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
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1. Remove unused functions/structures.
2. Add checks for NULL return values.
3. Change prefixes to vb2 instead of vboot for functions used internally
within vboot2/
4. Get rid of vboot_handoff.h file and move the structure definition to
vboot_common.h
5. Rename all functions using handoff structure to have prefix
vboot_handoff_*. All the handoff functions can be run _only_ after cbmem
is online.
6. Organize vboot_common.h content according to different
functionalities.
BUG=chrome-os-partner:55431
Change-Id: I4c07d50327d88cddbdfbb0b6f82c264e2b8620eb
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15799
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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All the mainboards share the same config options for CHROMEOS. Instead
of duplicating those in every mainboard, move the CHROMEOS config to SoC
and make it dependent on MAINBOARD_HAS_CHROMEOS.
BUG=chrome-os-partner:55431
Change-Id: Iafabb6373dfe16aaf0fe2cbc4e978952adeb403e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15822
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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All the mainboards share the same config options for CHROMEOS. Instead
of duplicating those in every mainboard, move the CHROMEOS config to SoC
and make it dependent on MAINBOARD_HAS_CHROMEOS.
BUG=chrome-os-partner:55431
Change-Id: I2d54ff6beac9fca7596a8f104e3c1447cada5c05
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15821
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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The controller for device mode USB is not plan of record
on apollolake. However, one still needs to configure the
one port to be host mode by default such that the devices
work as expected when plugged into the board.
BUG=chrome-os-partner:54581,chrome-os-partner:54656
TEST=Enabled xdci controller. Used USB type C->A dongle to
check that a mass storage device worked on port 0 on
reef.
Change-Id: Ia9ec5076491f31bc5dc3d534e235fb49f7b2efac
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15781
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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The gpio bank irq is not correct and hence gpio
bank handler is never called in case of gpio based irq.
Correct the gpio bank irq to enable gpio based irq.
BUG=chrome-os-partner:55433
TEST=cat /proc/interrupts | grep INT3452 should
output 14.
Change-Id: I54253786425b7d4c2007043d49a91dfa6db0397b
Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Reviewed-on: https://review.coreboot.org/15756
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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