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2018-07-30soc/amd/stoneyridge/northbridge.c: Create a way to change eDP training valueRichard Spiegel
The careena board needs different video settings to pass eye diagram test, which does not affect negatively the grunt board. In preparation for new VBIOS, create code that allows changing eDP training parameter. BUG=b:111673328 TEST=Tested in child patch. Change-Id: Ic0452618bfc5e05b9ef8280bb8ba398ec7b4ce95 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-30soc/intel/common: Add support to configure top swap featureAamir Bohra
RTC BUC control register provides a software interface to configure the top swap feature. This patch adds implementation to enable/disable top swap feature and gets it accessible in romstage as well. The top swap control functions are exposed only if INTEL_HAS_TOP_SWAP is selected. To use the topswap feature a second bootblock has to be added to the cbfs. Below configs aid in doing that, INTEL_HAS_TOP_SWAP INTEL_ADD_TOP_SWAP_BOOTBLOCK INTEL_TOP_SWAP_BOOTBLOCK_SIZE Enabling and Disabling topswap, using the added API enables user to boot alternatively from either bootblock. Change-Id: Iea31b891f81e76d4d623fcb68183c3ad3dcadbad Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/25805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-07-30soc/cavium/cn81xx: Use ATF from blobs repoPatrick Rudolph
Use precompiled BL31 from blobs repo. There's no check for USE_BLOBS here as the included file is "free": The BL31 is Open-Source and licensed under BSD. Change-Id: I7e9eb429d11150d43aa070d1bd6a11ea71951ce3 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-07-30soc/cavium/bootblock: Get rid of register X1Patrick Rudolph
The register X1 isn't used. Document it and remove it. Change-Id: I9324ea9de24ba4baaef9dde890c443dd0f921ad9 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/23792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-07-30soc/intel/fsp_baytrail: Add VBOOT supportPhilipp Deppenwiese
* Add vbnv_cmos_failed function to SoC. * Add VBOOT starts in romstage select. Change-Id: I90a051e2b8d303c918bef976d0bb07aae0b1f5b3 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/27728 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-29soc/intel: Remove legacy static TPM asl codePhilipp Deppenwiese
Since the TPM software stack refactoring static TPM ACPI code isn't needed anymore. Change-Id: I36a99cbc420ecfa55aa5c89787151d482225adf2 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/27715 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-27soc/amd/stoneyridge: Add IGFX device ACPI ASL entryMarc Jones
Add internal graphics device 00.01.00 to the ACPI tables so that the ACPI PCI option ROM save functions have a proper scope to save the ROM to. BUG=b:111697181 TEST=Check coreboot log doesn't have "PCI: 00:01.0: Missing ACPI scope" and check _ROM method is added in the SSDT1. Change-Id: I2c9ef8d9dff76805b1fcde2ccceef958a5b53b4f Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/27653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-07-27mediatek/mt8183: Add SPI supportmengqi.zhang
This patch implements SOC-specific code of mt8183 and link the common code to support SPI bus. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Signed-off-by: mengqi.zhang <mengqi.zhang@mediatek.com> Change-Id: I544e850299c74861313c2425721479fe5b91639e Reviewed-on: https://review.coreboot.org/27498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-27mediatek: Refactor SPI code among similar SOCsTristan Shieh
Refactor SPI code which will be reused amon similar SOCs. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Elm Change-Id: If5a6c554dc8361e729cf5c464325b97b2bfb7098 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/27497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-27mediatek/mt8183: Remove unused MMU stuff from bootblockTristan Shieh
Since we move mtk_mmu_init() from bootblock to decompressor, we don't need to build mmu_opertations.c in bootblock and we don't need to include <soc/mmu_operations.h> in bootblock.c. BUG=b:80501386 TEST=manually flashed into kukui and boots into romstage. Change-Id: I58f97ac1705e4dfde5e2d497d9bec33a1d8d17c2 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/27655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2018-07-26soc/intel/common/block/gpio: Add API for gpio_configure_pads_with_overrideFurquan Shaikh
This function adds support for gpio_configure_pads_with_override which: 1. Takes as input two GPIO tables -- base config table and override config table 2. Configures each pad in base config by first checking if there is a config available for the pad in override config table. If yes, then uses the one from override config table. Else, uses the base config to configure the pad. This is done to allow sharing of GPIO tables across baseboard-variants for various boards i.e. Each board can have a base config table which is provided by the baseboard and an optional override config table that can be provided by a variant to configure certain GPIOs differently. It is helpful when the variant GPIO diff list is not very huge compared to the baseboard. BUG=b:111743717 TEST=Verified that the GPIO config for phaser is same with and without this change. Change-Id: I1c5dc72c8368957201ab53d2e8398ff861341a4c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27640 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-26mediatek/mt8183: Enable bootblock self-decompressionHung-Te Lin
MT8183 only allows booting from eMMC, so we have to do eMMC emulation from an external source, for example EC, which makes the size of bootblock very important. A fully functional bootblock (that can boot into verstage or romstage) is about 38000 bytes. If self decompression (CONFIG_COMPRESS_BOOTBLOCK) is enabled, only 25088 (66%) bytes are needed. Inspired from crosreview.com/1070018. BUG=b:80501386 TEST=manually flashed into kukui and boots into romstage. Change-Id: I7a739866a4ea3bcafe2ff7b9e88d5ed00f3f3e40 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/27599 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-25soc/intel/apollolake: Get rid of power button device in corebootFurquan Shaikh
As per the ACPI specification, there are two types of power button devices: 1. Fixed hardware power button 2. Generic hardware power button Fixed hardware power button is added by the OSPM if POWER_BUTTON flag is not set in FADT by the BIOS. This device has its programming model in PM1x_EVT_BLK. All ACPI compliant OSes are expected to add this power button device by default if the power button FADT flag is not set. On the other hand, generic hardware power button can be used by platforms if fixed register space cannot be used for the power button device. In order to support this, power button device object with HID PNP0C0C is expected to be added to ACPI tables. Additionally, POWER_BUTTON flag should be set to indicate the presence of control method for power button. Chrome EC mainboards implemented the generic hardware power button in a broken manner i.e. power button object with HID PNP0C0C is added to ACPI however none of the boards set POWER_BUTTON flag in FADT. This results in Linux kernel adding both fixed hardware power button as well as generic hardware power button to the list of devices present on the system. Though this is mostly harmless, it is logically incorrect and can confuse any userspace utilities scanning the ACPI devices. This change gets rid of the generic hardware power button from APL and relies completely on the fixed hardware power button. BUG=b:110913245 TEST=Verified that fixed hardware power button still works as expected on octopus. Change-Id: I86259465c6cfaf579dd7dc3560b4c9e676b80b55 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27273 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-25drivers/tpm: Add TPM ramstage driver for devices without vboot.Philipp Deppenwiese
Logic: If vboot is not used and the tpm is not initialized in the romstage makes use of the ramstage driver to initialize the TPM globally without having setup calls in lower SoC level implementations. * Add TPM driver in ramstage chip init which calls the tpm_setup function. * Purge all occurrences of TPM init code and headers. * Only compile TIS drivers into ramstage except for vboot usage. * Remove Google Urara/Rotor TPM support because of missing i2c driver in ramstage. Change-Id: I7536c9734732aeaa85ccc7916c12eecb9ca26b2e Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/24905 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-24cpu/x86/mtrr.h: Rename MSR SMRR_PHYS_x to IA32_SMRR_PHYSxArthur Heymans
This is how these MSR's are referenced in Intel® 64 and IA-32 Architectures Software Developer’s Manual. The purpose is to differentiate with MSR_SMRR_PHYSx. Change-Id: I54875f3a6d98a28004d5bd3197923862af8f7377 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27584 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-23soc/cavium: Enable DRAM testPatrick Rudolph
Enable fast or extended DRAM test based on devicetree setting. The fast DRAM test takes less than a second, while the extended runs about 1 minute. Tested on Cavium Soc. Change-Id: I6a375f3d4c5cea7c3c0cd4592287f3f85dc7d3cf Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-07-23soc/cavium: Apply additional devicetree fixupsPatrick Rudolph
Depends on Change-Id: I0f27b92a5e074966f893399eb401eb97d784850d Apply additional devicetree fixes: * Update SCLK from boot fuses * Updated REFCLKUAA from UART ref clock divider settings * Remove disabled PEM entries * Remove phandle to disabled PEM entries Fixes: * Linux console wrong baud rate once the PL011 driver is started. * thunderx-pem kernel module crash on disable PCIe ports. Tested on Cavium SoC. Change-Id: I7e8eefd913915a879dad28dfb7801a2018ed2985 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-07-20mediatek/mt8183: Add GPIO supportPo Xu
This patch implements gpio_set_pull() and links the common MediaTek GPIO code to support IO config for other drivers (ex. SPI) and the requested functions in src/include/gpio.h. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: Ia2b0d88e9b70c9ad148797d77dc9e79ce1bcb64a Signed-off-by: Po Xu <jg_poxu@mediatek.com> Reviewed-on: https://review.coreboot.org/27417 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-20mediatek: Share GPIO code among similar SOCsTristan Shieh
Refactor GPIO code which will be reused among similar SOCs. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Elm Change-Id: Icdd1f2a1dd1bd64a7218bf9c63bd4a0af1acbcc0 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/27416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-19soc/cavium: Add PCI supportPatrick Rudolph
* Add support for secure/unsecure split * Use MMCONF to access devices in domain0 * Program MSIX vectors to fix a crash in GNU/Linux Tested on Cavium CN81XX_EVB. All PCI devices are visible. Change-Id: I881f38a26a165e6bd965fcd73547473b5e32d4b0 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25750 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-19Kconfig: Add config to insert ucode address in second FITRizwan Qureshi
This config is used to provide the name of a region where a microcode is located. The address of this will be added as the first entry in the FIT of the topswap bootblock. This adds a capability to associate two microcodes for each of the two bootblocks, this allows for the CPU to boot with different microcodes with 2 separate bootblocks. Change-Id: I4ee41d90bae34862aa68c9b8bd69288de1335585 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/27151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-19Kconfig: Add config for creating a second bootblockRizwan Qureshi
Intel PCH/Southbridges have feature that it is possible to have the southbridge/PCH look for the bootblock at a 64K or 128K/256K/512K/1MB (in case of newer SoCs) offset instead of the usual top of flash. Add configs to create a second bootblock and configure its size. Change-Id: I4bbd19c35871891b762a0673f840858d972e129e Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/22533 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-18mainboard/google/Kahlee: Select low-power mode for WiFiSimon Glass
Put the PCIe clock pins in power-saving mode for the WiFi module to save power. Note: This currently does not appear to have any effect on grunt. BUG=b:110041917 BRANCH=none TEST=boot without this patch: $ iotools mem_read32 0xfed80e00 0x0046f3ff With this patch: $ iotools mem_read32 0xfed80e00 0x0046f3f1 Change-Id: I389815bc36b8610a30b0cbb9d73262ad392e0181 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://review.coreboot.org/27465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-18soc/intel/common/block: Add WhiskeyLake W0 CPUIDKrzysztof Sywula
TEST=Boot up with W0 stepping processor. Change-Id: Ia7bcfd5235e57c70aa3f15d0042da8b16cf7e186 Signed-off-by: Krzysztof Sywula <krzysztof.m.sywula@intel.com> Reviewed-on: https://review.coreboot.org/27500 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-18sifive/fu540: add empty sdram init and size functionsPhilipp Hug
Change-Id: I65f900a3277bc8a4a83ebc8883d4a325bd690bf8 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/27438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-07-17riscv: add support for modifying compiler optionsXiang Wang
Each HART of a SoC like fu540 supports a different ISA. In order for the coreboot's code can run on each core, need to modify the compile options. So add this code. Change-Id: Ie33edc175e612846d4a74f3cbf7520d4145cb68b Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/27442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Philipp Hug <philipp@hug.cx>
2018-07-17soc/amd/stoneyridge: Update ACPI external processor nameKevin Chiu
update external processor name to match declaration in SSDT. in SSDT: Processor (\_PR.P000, 0x00, 0x00000410, 0x06) {} Processor (\_PR.P001, 0x01, 0x00000000, 0x00) {} in DSDT: External (_PR_.CP00, UnknownObj) External (_PR_.CP01, UnknownObj) After fix this, ACPI _PSL (Passive List) now can return correct list of processor objects for thermal passive cooling. BUG=b:111478152 BRANCH=master TEST=emerge-grunt coreboot Change-Id: I78c838608c78eb7b5e3f8d5c67589e082c756201 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/27495 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-17bdk: Use Kconfig options instead of getenv()Patrick Rudolph
* Use Kconfig options instead of unusable getenv * Select CAVIUM_BDK_DDR_TUNE_HW_OFFSETS on CN81XX * Fix Coverity CID 1393976 (DEADCODE) Tested on Cavium's cn8100_sff_evb. Change-Id: Ia16c0161b0e9cf5d06418e46556c0fb45532a5b1 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-07-16soc/amd/stoneyridge: Add GPIO functions to SMMMarc Jones
GPIO functions are required by the Grunt SMI handler. Change-Id: Id729139b02c10bdd922b3df298f8f9feb1aff745 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/27485 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-16soc/amd/stoneyridge: Fix gpio_set functionMarc Jones
The gpio_set function was not writing the correct GPIO register address. Change-Id: Ib306773ac72505977b606836bbaf3e2067324894 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/27484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-16soc/cavium: Fix overflow before widenPatrick Rudolph
Fix Coverity CID1393974 Change-Id: I39caea8a248d2f1debfca307f6fb7a2fe3e431b1 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-12Coverity: Fix CID1393976Patrick Rudolph
Cast to u64 to prevent possible integer overflow. Change-Id: I5c7d25278db54523242314cba6c85ac2f7a6c1f3 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-07-12soc/intel/skylake: add a space in printing ME FPF statusPratik Prajapati
This is cosmetic change Before: ME: Power Management Event : Clean global reset ME: Progress Phase State : Unknown phase: 0x08 state: 0x10 ME: Power Down Mitigation : NO ME: FPF status : fused After: ME: Power Management Event : Clean Moff->Mx wake ME: Progress Phase State : Unknown phase: 0x08 state: 0x10 ME: Power Down Mitigation : NO ME: FPF status : fused Change-Id: I15c02045d0f94fdb3f4a028585cad488d4ac9aa6 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/27246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-07-12soc/intel/braswell/acpi/dptf/thermal.asl: Make Thermal event optionalFrans Hendriks
Currently thermal event support can not be disabled at board level. Define and dependent code are placed in same file. Move define of HAVE_THERM_EVENT_HANDLER to mainboard file. Change-Id: Icb532e5bc7fd171ee2921f9a4b9b2150ba9f05c5 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/27415 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-11skylake: Remove "IshEnable"li feng
Remove "IshEnable" from soc_intel_skylake_config since it's not used anymore. Enable/disable ISH by checking if ISH device is turned on or not. Refer to https://review.coreboot.org/#/c/coreboot/+/26485/. BUG=b:79244403 BRANCH=none TEST=Built. Change-Id: I4d2889af118659852431c87cb516fd19b577efc5 Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://review.coreboot.org/26521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-11mediatek/mt8183: add PLL and clock init supportWeiyi Lu
Add PLL and clock init code. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui. Checked with frequency meter in SOC. Change-Id: I1f561f66bcf12de6a95c2f64eecd9508bd9bb26c Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Reviewed-on: https://review.coreboot.org/27031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-11mediatek: Share PLL code among similar SOCsTristan Shieh
Refactor PLL code which will be reused among similar SOCs. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Elm Change-Id: I11f044fbef93d4f5f4388368c510958d2b0ae66c Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/27305 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-11mediatek/mt8183: Add MMU operation supportTristan Shieh
Enable MMU in bootblock for performance, link common code to provide mtk_mmu_after_dram() to update MMU table in romstage after dram ready, implement mtk_soc_disable_l2c_sram(), and call mtk_mmu_disable_l2c_sram() to turn off L2C sram in ramstage. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui. Change-Id: I4e35f8276ca23de7fd13da3515b9f48d944ead32 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/27303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-11mediatek: Share MMU operation code among similar SOCsTristan Shieh
Refactor MMU operation code which will be reused among similar SOCs. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Elm Change-Id: Id8173da0a02e57e863263fcd89c91a9c089e8a0f Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/27349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-10soc/cavium: Add secondary CPU supportPatrick Rudolph
Change-Id: I07428161615bcd3d03a3eea0df2dd813e08c8f66 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-07-10soc/cavium/cn81xx: Set cntfrq_el0Patrick Rudolph
Set cntfrq_el0 to provide correct timer frequency. Change-Id: I4b6d0b0cf646a066fc5a51552a1891eccbd91e5e Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25450 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-10soc/cavium: Clean uart codePatrick Rudolph
* Only init UART_FOR_CONSOLE * Allow UART init with zero baudrate. * Init UART0..3 on Cavium's cn8100_sff_evb to fix kernel panic. Tested on CN8100_SFF_EVB. Change-Id: I1043b30318ec6210e2dd6b7ac313a41171d37f55 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-07-10soc/cavium: Enable MMUPatrick Rudolph
* Configure and enable MMU. * Cover the whole I/O space. * A minimum of 512KB TTB space is required. * Use secure mem attribute as firmware is running in ARM TZ region. Tested on Cavium SoC. Change-Id: I969446da62b4cc7adf9393fab69ff84ebf49220d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-07-10cavium: Add CN81xx SoC and eval board supportDavid Hendricks
This adds Cavium CN81xx SoC and SFF EVB files. Code is based off of Cavium's Octeon-TX SDK: https://github.com/Cavium-Open-Source-Distributions/OCTEON-TX-SDK BDK coreboot differences: bootblock: - Get rid of BDK header - Add Kconfig for link address - Move CAR setup code into assembly - Move unaligned memory access enable into assembly - Implement custom bootblock entry function - Add CLIB and CSIB blobs romstage: - Use minimal DRAM init only devicetree: - Convert FTD to static C file containing key value pairs Tested on CN81xx: - Boots to payload - Tested with GNU/Linux 4.16.3 - All hardware is usable (after applying additional commits) Implemented in future commits: - Vboot integration - MMU suuport - L2 Cache handling - ATF from external repo - Devicetree patching - Extended DRAM testing - UART init Not working: - Booting a payload - Booting upstream ATF TODO: - Configuration straps Change-Id: I47b4412d29203b45aee49bfa026c1d86ef7ce688 Signed-off-by: David Hendricks <dhendricks@fb.com> Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/23037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-07-09src/soc: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS
Change-Id: I21680354f33916b7b4d913f51a842b5d6c2ecef3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-09soc/intel/skylake: config ISH in SOC sideli feng
Config ISH in SOC side by checking if ISH device is turned on. "IshEnable" is not needed anymore since ISH device on/off will tell if ISH should be enabled or not. "IshEnable" will be removed from chip.h in separate CL. Atlas board specific ISH setting is needed, which is committed in separate CL. BUG=b:79244403 BRANCH=none TEST=Verified on Atlas board with ISH rework. ISH log showed on console. Change-Id: I3fc8648b3e6551497617ef1ebd2889245cdd31c3 Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://review.coreboot.org/26485 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-03soc/amd/stoneyridge: correct GPIO emission error in ACPIKevin Chiu
It can not emit byte data without BytePrefix. design to: Or (Local5, GPIO_PIN_OUT, Local5) error due to GPIO_PIN_OUT is 0x40 but 0x40 encoding means nothing in AML spec. so it will include next emitted string in Or: Or (Local5, Local5, \_SB.GPW2) fix: Store (0x40, Local0) Or (Local5, Local0, Local5) BUG=b:110962003 BRANCH=master TEST=emerge-grunt coreboot extract SSDT then check ACPI syntax is correct Change-Id: I7a0704112b77105826de87b14a38ed2f665224d5 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/27306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-02stoneyridge: Enable legacy IORaul E Rangel
Legacy IO enables access to RTC IO 0x70-0x73. This is needed for CMOS to function correctly. BUG=b:110817463 TEST=ran firmware_CorruptFwSigB on grunt Change-Id: I533226ba764f567e348577d7fcf6ebe43336609a Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/27268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-02stoneyridge: Enable IO CF9 in bootblockRaul E Rangel
If IO CF9 is not enabled, hard_reset() won't do anything in bootblock or verstage. BUG=b:110817463 TEST=built on grunt and made sure that hard_reset() reboots. Change-Id: I5f091077a17db3dfe5b8e8367163312db6828360 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/27267 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-02mediatek/mt8183: Add mtcmos init supportTristan Shieh
Using common mtcmos code to power on audio and display modules in SOC. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui. Passes the status check at the end of mtcmos_power_on() Change-Id: I41f16ba36432a8bbc47793cec2979753c9f84b43 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/27030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
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