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path: root/src/soc
AgeCommit message (Expand)Author
2017-07-13soc/intel/cannonlake: Add MakefileAndrey Petrov
2017-07-13soc/intel/cannonlake: Add bootblock PCHAndrey Petrov
2017-07-13soc/intel/cannonlake: Add early CPU initializationAndrey Petrov
2017-07-13soc/intel/skylake: reduce postcar stack usage for fsp 2.0Aaron Durbin
2017-07-12soc/intel/cannonlake: Add PCI dev macros and IDsAndrey Petrov
2017-07-12soc/intel/cannonlake: Add report_platform.cAndrey Petrov
2017-07-12soc/amd/stoneyridge: Update header guards and includesMarshall Dawson
2017-07-12soc/intel/skylake: Remove “disable SaGv” in recovery mode flowSubrata Banik
2017-07-12Revert "soc/intel/skylake: storage: Add 2ms delay before exiting D3"Subrata Banik
2017-07-12soc/intel/skylake: Perform PCR read after all PCR writeSubrata Banik
2017-07-11soc/intel/skylake: Fix PMC address range setup for PCH-HNico Huber
2017-07-11soc/intel/skylake: Set generic I/O decode ranges earlyNico Huber
2017-07-11binaryPI: Define AGESA blob in CBFS as Kconfig stringKyösti Mälkki
2017-07-10sgx: Move SGX code to intel/common/blockPratik Prajapati
2017-07-08soc/amd/stoneyridge/northbridge.c: remove unnecessary null checkMartin Kepplinger
2017-07-03soc/intel/quark: Add I2C debuggingLee Leahy
2017-07-03soc/intel/apollolake: Use common gpio for apollolakeHannah Williams
2017-07-02soc/intel/quark/spi.c: Explain a read in order to flush buffersMartin Kepplinger
2017-07-02soc/intel/cannonlake: Add bootblock.cAndrey Petrov
2017-07-02intel/block/cse: Add Cannon Lake SoC PCI device IDAndrey Petrov
2017-07-02soc/amd/common: Add initial support for AMD PSPMarshall Dawson
2017-07-01soc/intel/skylake: Remove unnecessary P-State and Flex Ratio assignmentBarnali Sarkar
2017-06-29soc/intel/skylake/Kconfig: Drop useless FSP1.1/2.0 promptsNico Huber
2017-06-29soc/intel/cannonlake: Add UART initializationAndrey Petrov
2017-06-29arch/x86: update assembly to ensure 16-byte alignment into CAaron Durbin
2017-06-29soc/intel/common/block/gpio: Port gpio code from Apollolake to commonHannah Williams
2017-06-29soc/intel/cannonlake: Add initial dummy directoryLijian Zhao
2017-06-29soc/amd/stoneyridge: Convert monotonic timerMarshall Dawson
2017-06-28soc/amd/stoneyridge: Revise pci_devs.h fileMarshall Dawson
2017-06-28soc/amd/stoneyridge: Fix device IDsMarshall Dawson
2017-06-28soc/amd/stoneyridge: Enable early cbmemMarshall Dawson
2017-06-27soc/amd/stoneyridge: Add tseg size to KconfigMarshall Dawson
2017-06-27soc/stoneyridge: Remove IDE controllerMarshall Dawson
2017-06-27soc/stoneyridge: Remove FCH PCIe supportMarshall Dawson
2017-06-27soc/amd/stoneyridge: Remove PCIe-PCI bridgeMarshall Dawson
2017-06-27soc/amd/common: Fix most checkpatch errorsMarshall Dawson
2017-06-27soc/amd/stoneyridge: Fix most checkpatch errorsMarshall Dawson
2017-06-27soc/amd/stoneyridge/acpi: Fix checkpatch errorsMarshall Dawson
2017-06-27vendorcode/amd: Unify Porting.h across all targetsStefan Reinauer
2017-06-27soc/intel/common/opregion: Use enum cb_err as return valuePatrick Rudolph
2017-06-27soc/intel/quark: We're not Broadwell anymoreStefan Reinauer
2017-06-27soc/intel/skylake: storage: Use word access for power state registersDuncan Laurie
2017-06-27soc/intel/skylake: storage: Add 2ms delay before exiting D3Duncan Laurie
2017-06-26soc/intel/fsp_baytrail/include/soc/pci_devs.h: Add brackets around macroElyes HAOUAS
2017-06-26soc/amd/stoneyridge: Add northbridge supportMarc Jones
2017-06-26soc/amd/stoneyridge: Add CPU filesMarc Jones
2017-06-26soc: Add AMD Stoney Ridge southbridge codeMarc Jones
2017-06-26rockchip/rk3399: update the ddr 200MHz frequency configurationCaesar Wang
2017-06-23soc/intel/skylake: Remove post SMM Relocation uCode loadingBarnali Sarkar
2017-06-23soc/intel/skylake: Use CPU MP Init Common codeBarnali Sarkar