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AgeCommit message (Expand)Author
2017-08-22soc/intel/cannonlake: Define soc_intel_cannonlake_configPratik Prajapati
2017-08-22soc/intel/skylake: Lock sideband access in coreboot and not in FSPBarnali Sarkar
2017-08-21soc/intel/cannonlake: Enable common PMC code for CNLLijian Zhao
2017-08-21soc/intel/skylake: Fix SGX init sequencePratik Prajapati
2017-08-21intel/common/block/sgx: Refactor SGX common codePratik Prajapati
2017-08-21intel/common/mp_init: Refactor MP Init code to get rid of microcode paramPratik Prajapati
2017-08-21intel/common/sgx: Use intel_mp_current_microcode() to get microcode pointerPratik Prajapati
2017-08-21soc/intel/cannonlake: Add support for all UART port indexSubrata Banik
2017-08-21soc/intel/skylake: Add support for all UART port indexSubrata Banik
2017-08-21soc/intel/cannonlake: Add Kconfig option to select UART indexSubrata Banik
2017-08-21soc/intel/skylake: Add Kconfig option to select UART indexSubrata Banik
2017-08-21soc/intel/apollolake: remove duplicate gpio GPE definesAaron Durbin
2017-08-21intel/common/cpu: Add function to get microcode patch pointerPratik Prajapati
2017-08-21soc/intel/common/smbus: Don't clear random bitsNico Huber
2017-08-19arch/x86: Sanity checking on HAVE_SMI_HANDLERKyösti Mälkki
2017-08-19soc/intel/skylake: Enable power button SMI when jumping to payloadFurquan Shaikh
2017-08-18Reinvent I2C opsNico Huber
2017-08-18include/device: Split i2c.h into threeNico Huber
2017-08-17soc/intel/common/block: Add functions to common CPU library codeShaunak Saha
2017-08-17soc/intel/cannonlake: Add SPI flash controller driverLijian Zhao
2017-08-17intel/cannonlake/chip: Add initial PCI enum supportPratik Prajapati
2017-08-17intel/common/block/fast_spi: Add config option to disable write statusDuncan Laurie
2017-08-17soc/intel/apollolake: Fix CONFIG_FSP_CAR build errorMarshall Dawson
2017-08-17soc/intel/skylake: Configure FSP to skip ME MBP stepDuncan Laurie
2017-08-16soc/intel/cannonlake: Add proper support to enable UART2 in 16550 modeSubrata Banik
2017-08-16soc/intel/skylake: Add proper support to enable UART2 in 16550 modeSubrata Banik
2017-08-15soc/intel/cannonlake: Rectify LPC Lock Enable (LE) bit definitionSubrata Banik
2017-08-15soc/intel/common/block: Fix PMC common block dependencyShaunak Saha
2017-08-15soc/intel/apollolake: Rename SRAM BAR0 and BAR2 macrosV Sowmya
2017-08-15soc/intel/apollolake: Provide option to use Common MP InitBarnali Sarkar
2017-08-15soc/intel/cannonlake: Call into FSP siliconinitLijian Zhao
2017-08-15soc/intel/cannonlake: Add postcar stage supportLijian Zhao
2017-08-15soc/intel/common/block: Add LPC Common code and use it for APLRavi Sarawadi
2017-08-15soc/intel/{cannonlake,skylake}: fix PCH_P2SB_EPMASK macroAaron Durbin
2017-08-14stoneyridge: Fix CPU ASL \_PR tableMarc Jones
2017-08-14i2c: Move to Linux like `struct i2c_msg`Nico Huber
2017-08-14soc/intel/cannonlake: Remove unused systemagent registersSubrata Banik
2017-08-14soc/intel/cannonlake: Initialize struct member to 0Subrata Banik
2017-08-14common/block/lpss: Add CLK read function into LPSS commonSubrata Banik
2017-08-14stoneyridge: Rename hudson to southbridgeMarc Jones
2017-08-11soc/cannonlake: Enable SMM code for Cannon LakeBrandon Breitenstein
2017-08-11soc/intel/cannonlake: Add missing _PCH_DEV definitionsFurquan Shaikh
2017-08-10soc/intel/apollolake: Enable UART debug controller on S3 resumeFurquan Shaikh
2017-08-10soc/intel/skylake: Enable UART debug controller on S3 resumeFurquan Shaikh
2017-08-10soc/intel/common/uart: Add support for enabling UART debug controller on resumeFurquan Shaikh
2017-08-10soc/intel/common/lpss: Add lpss_is_controller_in_resetFurquan Shaikh
2017-08-10soc/intel/common/uart: Refactor uart_common_initFurquan Shaikh
2017-08-10soc/intel/common/block: Add CNL, APL and GLK CPU device IDsBarnali Sarkar
2017-08-10soc/intel/apollolake: Add file path checkHannah Williams
2017-08-09intel/common/block/smm: Update smihandler to handle gpiBrandon Breitenstein