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AgeCommit message (Expand)Author
2020-06-30soc/intel/tigerlake: Add CpuReplacementCheck to chip optionsJamie Ryu
2020-06-30soc/intel/tigerlake: Avoid NULL pointer dereferenceJohn Zhao
2020-06-30src: Remove whitespaces before tabsElyes HAOUAS
2020-06-29soc/amd/picasso: add NULL-pointer check to root_complex_fill_ssdtFelix Held
2020-06-29soc/amd/picasso/soc_util: add comment on the silicon and soc typesFelix Held
2020-06-29soc/amd/common: Refactor GPIO SCI/SMI interruptsKyösti Mälkki
2020-06-29soc/amd/common: Refactor GPIO_MASTER_SWITCH interrupt enableKyösti Mälkki
2020-06-29soc/amd/common: Drop ACPIMMIO GPIO bank separationKyösti Mälkki
2020-06-29soc/intel/tigerlake: Run pmc_set_acpi_mode() during .init in pmc_opsWilliam Wei
2020-06-28vendorcode/intel/fsp/fsp2_0/cpx_sp: Update to FSP ww24 release and adapt socJonathan Zhang
2020-06-28soc/amd/common: Allow runtime mapping of ACPIMMIO banksKyösti Mälkki
2020-06-28soc/amd/common: Access ACPIMMIO via proper symbolsKyösti Mälkki
2020-06-28soc/intel/common: add TCC activation functionalitySumeet R Pawnikar
2020-06-28soc/xeon_sp/cpx: Define MSR PPIN related registersJohnny Lin
2020-06-28soc/amd/picasso/soc_util: rework reduced I/O chip detectionFelix Held
2020-06-27soc/intel/broadwell: Use common early SPI codeAngel Pons
2020-06-26soc/rockchip: Use (Q) instead of @Stefan Reinauer
2020-06-25Revert "soc/amd/common/block/acpimmio: Update acpimmio for psp_verstage"Kyösti Mälkki
2020-06-25soc/intel/cannonlake: Add PchPmPwrCycDur to chip optionsSridhar Siricilla
2020-06-25drivers/intel/fsp2_0: decouple FSP_PEIM_TO_PEIM_INTERFACE from FSP 2.1Jonathan Zhang
2020-06-25soc/intel/xeon_sp: use edk2-stable202005 headersJonathan Zhang
2020-06-25soc/intel/xeon_sp/cpx: display UPDs and CPX-SP specific HOBsJonathan Zhang
2020-06-25soc/intel/cannonlake: Add missing USB_PORT_WAKE_ENABLE defineEdward O'Callaghan
2020-06-24soc/amd/picasso: fix host bridge bus numbersAaron Durbin
2020-06-24soc/amd/picasso: Add UPD xhci0_force_gen1Chris Wang
2020-06-24soc/intel/tigerlake: Fix unresolved symbol CDW1 errorJohn Zhao
2020-06-24soc/intel/broadwell/adsp: Fix 8-bit write on PCI_INTERRUPT_LINE registerElyes HAOUAS
2020-06-24src: Report byte-sized access for GPE0Angel Pons
2020-06-24soc/amd/stoneyridge: Correct ACPI CPU string prefixMatt DeVillier
2020-06-24ACPI: Replace smm_setup_structures()Kyösti Mälkki
2020-06-24ACPI: Replace uses of CBMEM_ID_ACPI_GNVSKyösti Mälkki
2020-06-23src/*: Update makefiles to exclude x86 code from psp-verstageMartin Roth
2020-06-22soc/amd/picasso: Set BERT_SIZE to 0 when no table generatedMarshall Dawson
2020-06-22soc/amd/picasso: Convert BERT reserved region from cbmemMarshall Dawson
2020-06-22soc/intel/tigerlake: Add CmdMirror option in chip.hDavid Wu
2020-06-22soc/intel/xeon_sp/cpx: rename xeon_sp_get_cpu_count()Jonathan Zhang
2020-06-22mb/google/volteer: Override power limits with SKU-specific limitsTim Wawrzynczak
2020-06-22amd/picasso/acpi: Add power resources for I2C and UARTRaul E Rangel
2020-06-22soc/intel/xeon_sp/cpx: consider stack personalityJonathan Zhang
2020-06-22soc/intel/xeon_sp/cpx: update ACPI xSDTJonathan Zhang
2020-06-22soc/intel/jasperlake: add processor power limits control supportSumeet R Pawnikar
2020-06-22soc/amd/picasso: don't increment boot count twiceAaron Durbin
2020-06-22soc/intel/xeon_sp/cpx: Finalize PCU configurationJonathan Zhang
2020-06-22soc/intel/tigerlake: Update platform.asl to ASL2.0 syntaxV Sowmya
2020-06-22soc/amd/picasso: Enable IDT in all stagesFurquan Shaikh
2020-06-22device/smbus_host: Declare common early SMBus prototypesKyösti Mälkki
2020-06-22cpu/x86/lapic: Support x86_64 and clean up codePatrick Rudolph
2020-06-22soc/amd/picasso/bootblock: Clear BSS sectionRaul E Rangel
2020-06-22soc/amd/picasso/bootblock: Write EIP to secure S3Raul E Rangel
2020-06-22soc/qualcomm/sc7180/qupv3_config.c: Add missing includesElyes HAOUAS