coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2021-01-18	soc/intel/xeon_sp/uncore.c: Remove duplicated include	Elyes HAOUAS
2021-01-18	soc/intel/xeon_sp/skx/soc_acpi.c: Remove duplicated include	Elyes HAOUAS
2021-01-18	soc/amd/stoneyridge/romstage.c: Remove repeated word	Elyes HAOUAS
2021-01-18	soc/intel/broadwell/bootblock.c: Remove repeated word	Elyes HAOUAS
2021-01-18	soc/intel/common/block/include/intelblocks/pmc_ipc.h: Remove repeated word	Elyes HAOUAS
2021-01-18	soc/intel/common/block/itss/itss.c: Remove repeated word	Elyes HAOUAS
2021-01-18	soc/intel/skylake/chip.h: Remove repeated word	Elyes HAOUAS
2021-01-18	soc/nvidia/tegra124/spi.c: Remove repeated word	Elyes HAOUAS
2021-01-18	soc/nvidia/tegra210/spi.c: Remove repeated word	Elyes HAOUAS
2021-01-18	soc/amd/common/block/smi/smi_util.c: Remove repeated word	Elyes HAOUAS
2021-01-18	soc/intel/alderlake: Update PCH and CPU PCIe RP table	Eric Lai
2021-01-18	soc/intel/common: Move L1_substates_control to pcie_rp.h	Eric Lai
2021-01-18	soc/intel/common/pcie: Allow pcie_rp_group table to be non-contiguous	Furquan Shaikh
2021-01-18	ACPI: Select ACPI_SOC_NVS only where suitable	Kyösti Mälkki
2021-01-15	build system: Always add coreboot.pre dependency to intermediates	Patrick Georgi
2021-01-15	build system: Remove flock calls from intermediate processing	Patrick Georgi
2021-01-15	soc/mediatek/mt8183: Support byte mode and single rank DDR	Shaoming Chen
2021-01-15	soc/amd/picasso: Generate ACPI CRAT objects in cb	Jason Glenesk
2021-01-15	soc/intel/braswell: Prevent NULL pointer dereference	Angel Pons
2021-01-15	cpu/x86/mpinit: Serialize microcode updates for HT threads	Patrick Rudolph
2021-01-15	soc/amd/cezanne,picasso/uart: remove unneeded struct name	Felix Held
2021-01-14	soc/intel/tgl: Add configurable value for UsbTcPortEn	Brandon Breitenstein
2021-01-14	soc/amd/picasso: Remove printf in asl	Raul E Rangel
2021-01-14	build system: Structure and serialize INTERMEDIATE	Patrick Georgi
2021-01-14	soc/amd/picasso/uart: add missing device/device.h include	Felix Held
2021-01-14	soc/amd/cezanne: add remaining non-ACPI parts of UART support	Felix Held
2021-01-14	soc/amd/cezanne: add AOAC support	Felix Held
2021-01-14	soc/amd/cezanne: add console UART support	Felix Held
2021-01-14	soc/amd/stoneyridge: use SOC_AMD_COMMON_BLOCK_UART	Felix Held
2021-01-14	soc/amd/common/block/uart/Makefile: use all target	Felix Held
2021-01-14	soc/amd/piasso/uart: move get_uart_base prototype to common code header	Felix Held
2021-01-14	soc/amd/common/uart: move CONSOLE_UART_BASE_ADDRESS back to SoC code	Felix Held
2021-01-14	soc/amd/picasso: remove broken and unused legacy UART support	Felix Held
2021-01-13	soc/amd/picasso: Disable CBFS MCACHE	Raul E Rangel
2021-01-13	ACPI: Have single call-site for acpi_inject_nvsa()	Kyösti Mälkki
2021-01-13	ACPI: Add common acpi_fill_gnvs()	Kyösti Mälkki
2021-01-13	soc/amd: Rename to soc_fill_gnvs()	Kyösti Mälkki
2021-01-13	soc/amd: Rename to pm_fill_gnvs()	Kyösti Mälkki
2021-01-13	soc/intel/tigerlake: Disable TC cold support	Srinidhi N Kaushik
2021-01-12	soc/intel: rename uart_max_index	Michael Niewöhner
2021-01-12	soc/intel/denverton_ns: Drop redundant `DEFAULT_ACPI_BASE`	Angel Pons
2021-01-12	soc/intel/common/pcie: Add helper function for getting mask of enabled ports	Furquan Shaikh
2021-01-12	soc/intel/alderlake: Add PCH ID 0x5182	Subrata Banik
2021-01-11	soc/intel/{icl,tgl,jsl,ehl}: add LPIT support	Michael Niewöhner
2021-01-11	soc/intel/skl: add SLP_S0 residency register and enable LPIT support	Michael Niewöhner
2021-01-11	soc/intel/cnl: add SLP_S0 residency register and enable LPIT support	Michael Niewöhner
2021-01-11	acpi,soc/intel/common: add support for Intel Low Power Idle Table	Michael Niewöhner
2021-01-11	{soc,vc,mb}/intel: Drop support for Cannon Lake SoC	Felix Singer
2021-01-11	soc/amd/cezzane: Add a minimal chipset tree	Furquan Shaikh
2021-01-11	soc/intel/common/uart: Use simple(_s_) variants of PCI functions	Furquan Shaikh