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2019-02-05bootmem: add new memory type for BL31Ting Shen
After CL:31122, we can finally define a memory type specific for BL31, to make sure BL31 is not loaded on other reserved area. Change-Id: Idbd9a7fe4b12af23de1519892936d8d88a000e2c Signed-off-by: Ting Shen <phoenixshen@google.com> Reviewed-on: https://review.coreboot.org/c/31123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-02-05intel/quark: Fix COMMONLIB_STORAGE in CARKyösti Mälkki
The allocation is not required before romstage, so it can be just another CAR_GLOBAL instead of polluting the linker script. Change-Id: I0738a655f6cc924fbed92ea630f85406e3f58c0b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31191 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-05src/soc/intel/common: Clear GPIO driver ownership when not requestedKeith Short
The default state of the HOSTSW_OWN register in the PCH is zero, which configures GPIO pins for ACPI ownership. The board variabt GPIO tables can request specific pins to be configured for GPIO driver ownership. This change sets the HOSTSW_OWN ownership bit when requested and explicitly clears the ownership bit if not requested. BUG=b:120884290 BRANCH=none TEST=Build coreboot on sarien. Verified UEFI to coreboot transition boots successfully. Change-Id: Ia82539dbbbc7cf5dfb9223902d563cafec1a73e5 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://review.coreboot.org/c/31209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-05soc/intel/apl: Call mca_configure() on cold boots onlyNico Huber
By APL BIOS Spec, we must not do this on warm boots. The TODO comment seems stale and copied over. So the actual requirements for SGX are unknown and we add a guard for that case. Change-Id: I09b4a2fe22267d7318951aac20a3ea566403492e Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/31200 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-05soc/intel/cpulib: Add debug message to mca_configure()Nico Huber
Change-Id: Idfe93e454cc0ce0d8e06e23beaddee2f11f5eedd Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/31199 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-05intel/apollolake: Add parameter to enable VTD in devicetreeWerner Zeh
The FSP has a parameter to enable or disable the VTD feature (Intel's Virtualization Technology for Directed I/O). In current header files for FSP-S (Apollo Lake and Gemini Lake) this parameter is set to disabled per default. Therefore, if the FSP was not modified via BCT, this feature is most likely disabled on all mainboards. Add a chip parameter so that VTD can be enabled on mainboard level in devicetree and therefore this feature can be activated if needed. Change-Id: Ic0bfcf1719e1ccc678a932bf3d38c6dbce3556bc Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/31194 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-05soc/intel/apollolake: Update XHCI ports for GLK in ACPI tablesFurquan Shaikh
GLK has a dedicated USB2 port that is used specifically for CNVi BT. This requires that the ACPI tables define an additional USB 2 port which results in _ADR for USB 3 ports being different for GLK than APL. This change splits the ports in xhci.asl into APL and GLK specific ports.asl and selects the appropriate file based on CONFIG_SOC_INTEL_GLK. It also adds support for returning HS09 for GLK if ACPI name is requested for that port. BUG=b:123670712 BRANCH=octopus TEST=Verified that generated DSDT for octopus (GLK) includes HS09 and for reef (APL) does not include HS09 definition. Change-Id: I2d3d3690ec9ea1f6e35c38c3b3cbb82e961b7950 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/31172 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-04soc/amd/stoneyridge: Reboot if missing MRC cache infoMarshall Dawson
AGESA doesn't detect invalid NV data during AmdInitResume(). In cases where the data has been erased, or cannot be found, reboot the system. Otherwise the user will experience a hang when cbmem isn't recovered and the postcar frame cannot be initialized. BUG=b:122725586 TEST=Write S3 NV save data with 0xff and force reboot Change-Id: Ib3cf2515f300decd3de198f7741660d95ee4c744 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/31160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-02-04soc/intel/cannonlake: Remove SOC_INTEL_CANNONLAKE_MEMCFG_INIT KconfigSubrata Banik
This patch removes duplicate selects of same SOC_INTEL_CANNONLAKE_MEMCFG_INIT from various CFL/WHL SoC based boards to include cnl_memcfg_init.c file and include the cnl_memcfg_init.c file by default in CNL SoC Makefile.inc. Change-Id: Ib21ea305871dc859e7db0720c18a9479100346c3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/31134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-01soc/amd/stoneyridge: Add generic PM1 register clear functionMarshall Dawson
Convert vboot_platform_prepare_reboot() to call a function in soc//stoneyridge. A subsequent patch will add another call to the new function, and this change removes any inference of a dependency on vboot. BUG=b:122725586 Change-Id: I634fcd030e206c790bda697a3dbef4e8cc21b3a8 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/31159 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-01soc/intel/icelake: Make correct C-state entries for S0ix and non-S0ixSubrata Banik
TEST=Dump SSDT entries to verify _CST between S0ix enable and disable. >> iasl -d SSDT # to generate SSDT.dsl Change-Id: I82d8bf9d143263a80a544f6e11186a3bc9c41052 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/31153 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-01-31soc/intel/cannonlake: Make correct C-state entries for S0ix and non-S0ixRonak Kanabar
TEST=Dump SSDT entries to verify _CST between S0ix enable and disable. Change-Id: I25e8f8c13bb91c2645e8e9fdfdf9ba4d7022f1b1 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/31154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-01-31soc/intel/apollolake: Fix XHCI device name in ACPIKarthikeyan Ramasubramanian
XHCI is currently named as XHC1. This leads to namespace lookup error in the kernel when children USB ACPI devices are added under the scope of XHCI device. BUG=b:123296264 BRANCH=octopus TEST=Boot to ChromeOS; Ensure that the below error is resolved in the kernel dmesg [ 0.001000] ACPI Error: [\_SB_.PCI0.XHCI.RHUB.HS03] Namespace lookup failure, AE_NOT_FOUND (20170728/dswload-210) Change-Id: Ia4921547fee6fb51333319b9e881501a7e75ebce Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/31147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-01-30soc/intel/apollolake: Sync fsp upd structure updateJohn Zhao
FSP 2.0.9 provides UPD interface to adjust integrated filter value, usb3 LDO and pmic vdd2 voltage. Change coreboot upd structure to sync with fsp 2.0.9 release. BUG=b:123398358 CQ-DEPEND=CL:*817128 TEST=Verified yorp boots to kernel. Change-Id: I3d17dfbe58bdc5222378459723da8e9ac0573510 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/31131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-30soc/amd/stoneyridge: Access SMBUS through MMIORichard Spiegel
Currently SMBUS registers are accessed through IO, but with stoneyridge they can be accessed through MMIO. This reduces the time of execution by a tiny amount (MMIO write is faster than IO write, though MMIO read is about as fast as IO read) as most of the time consumed is actually transaction time. Convert code to MMIO access. BUG=b:117754784 TEST=Used IO to write and MMIO to read, to confirm a one to one relationship between IO and MMIO. Then build and boot grunt. Change-Id: Ibe1471d1d578611e7d666f70bc97de4c3b74d7f8 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/29258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-01-29google/kukui: Move some initialization from bootblock to verstageYou-Cheng Syu
MT8183 only allows booting from eMMC, so we have to do eMMC emulation from an external source, for example EC, which makes the size of bootblock very important. This CL moves some initialization steps from bootblock to verstage. This will save us about 2700 bytes (before compression) / 1024 bytes (after LZ4 compression) in bootblock. In case of CONFIG_VBOOT is disabled, these initialization steps will be done in romstage. BRANCH=none BUG=b:120588396 TEST=manually boot into kernel Change-Id: I9968d88c54283ef334d1ab975086d4adb3363bd6 Signed-off-by: You-Cheng Syu <youcheng@google.com> Reviewed-on: https://review.coreboot.org/c/30331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-29soc/intel/apollolake: Add GLK usb2eye configuration overrideSeunghwan Kim
Now we have usb2eye configuration register in FSPUPD, so we need to add an interface to override usb2eye setting. BRANCH=octopus BUG=NONE TEST=Verified usb2eye custom setting works Change-Id: I5c500964658072eaaf59364242aa928df25d99d1 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/c/31060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-01-29mediatek: Separate WDT reset function from WDT driverTristan Shieh
Separate WDT reset function from WDT driver, then we can use the common WDT driver and have a board-specific reset function on different boards. In Kukui, we plan to use GPIO HW reset, instead of WDT reset. Add config "MISSING_BOARD_RESET" in Kukui to pass the build for now. BUG=b:80501386 BRANCH=none TEST=emerge-elm coreboot; emerge-kukui coreboot; Change-Id: Ica07fe3a027cd7e9eb6d10202c3ef3ed7bea00c2 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/c/31121 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-29soc/intel/icelake: Remove unnecessary USB charging ASL entriesSubrata Banik
This patch removes stale ASL entries added in past due to chromeos requirement. BUG=115755982 TEST=Build and boot ICL platform without any problem. Change-Id: I18b57822ce3198fb96aae977f0b552ff2d4a14ee Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/31117 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-28intel/apollolake: Add IPU to disable_dev functionWerner Zeh
The SoC has an Image Processing Unit which is located on PCI 00:03.0. There is a corresponding parameter for FSP which handles enabling/disabling of this functionality (IpuEn). Add this device to the disable_dev() function of the chip so that if this device is disabled in devicetree the matching FSP parameter will be disabled as well. As this parameter is only valid for Apollo Lake, use the config switch CONFIG_SOC_INTEL_GLK to disable this code if compiled not for Apollo Lake. As this issue is regarding a missing structure member, this check needs to be done on preprocessor level and not at runtime. Test=Verified this function on mc_apl2. Change-Id: I75444bf483de32ba641f76ca50e9744fdce2e726 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/30992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-28intel/apollolake: Add fixed resources for VTd to system resourcesWerner Zeh
If the VTd feature is enabled, there will be up to two fixed resources which are set up by the FSP. Add these resources to the list of system resources so that the PCI enumerator will know them. Change-Id: If96fc1c93746e3c7f510e5b3095ea3090e1b8807 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/30991 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-28soc/apollolake: Generate DMAR tableWerner Zeh
Generate DMAR table if VTd feature is enabled. Test=Booted into Linux on mc_apl2 and verified the DMAR table contents. In addition turned off Vtd and verified that no DMAR table is generated at all. Change-Id: Ie3683a2f3578c141c691b2268e32f27ba2e772fa Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/30990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-28intelblocks/systemagent: Add ACPI table generation hookWerner Zeh
In preparation of generating DMAR tables, provide the hook in SoC scope for the systemagent to write ACPI tables. The complete functionality is SoC-specific. Therefore the entry hook is defined as a weak function which can be overridden by SoC code. If the SoC does not have support for generating DMAR tables this hook will do no harm. Change-Id: I1333ae2b79f1a855e6f3bb39bf534da170ddc9e1 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/30989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-28src: Don't use a #defines like Kconfig symbolsElyes HAOUAS
This is spotted using ./util/lint/kconfig_lint To work around the issue, rename the prefix from `CONFIG_` to `CONF_`. Change-Id: Ia31aed366bf768ab167ed5f8595bee8234aac46b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-28soc/intel/skylake: select FSP_M_XIP if MAINBOARD_USES_FSP2_0Matt DeVillier
Select FSP_M_XIP if MAINBOARD_USES_FSP2_0, since all SkyKabylake boards require FSP-M XIP when FSP 2.0 is used, and since not having it selected results in a non-booting image. Also, put select FSP_T_XIP if FSP_CAR in proper alphabetical order. Change-Id: I6d3986eda18297b12490cefb236f5de5faca6550 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/31110 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-28amd/stoneyridge: Disable GPIO MASK STATUSRaul E Rangel
MASK_STATUS disables interrupt status generation for the entire GPIO controller when any debounce register is configured. This causes problems when the kernel is loading drivers because we could lose interrupts for previously loaded devices. sb_program_gpios is also not setup to wait when configuring PAD_DEBOUNCE, so there is a potential that we could lose the interrupt status enable bit for other registers. By disabling MASK_STATUS we avoid that problem. BUG=b:113880780 BRANCH=none TEST=Ran a reboot stress test that concluded that we are no longer losing TPM interrupts while booting. Change-Id: Ife1db3b1449f205092509595cbc3eca511bff57a Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/c/31082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Daniel Kurtz <djkurtz@google.com>
2019-01-28soc/intel/denverton_ns: Add ACPI T-States and P-StatesJulien Viard de Galbert
Also make soc_get_tss_table public and weak instead of static in intelblock so it can be overridden in denverton. Change-Id: Id9c7da474a81417a5cebd875023f7cd3d5a77796 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/c/25430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Vanny E <vanessa.f.eusebio@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: David Guckian Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
2019-01-28soc/intel/{apl,skl}: Drop redundant `select RTC`Nico Huber
RTC is now implicitly selected through SOC_INTEL_COMMON_BLOCK_RTC and SOC_INTEL_COMMON_PCH_BASE. Change-Id: I1885c419cfe318b75f3bda6220d4a6f6a8e26575 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/31113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-01-28soc/intel/common/rtc: Enable RTC in common code RTCLijian Zhao
Intel RTC common code driver need to turn on RTC itself.After the change, cannonlake and icelake platform will have RTC enabled. BUG=b:123372643 TEST=build and boot up on sarien platform, check .config to see CONFIG_RTC is set. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I0c8c5cf9e6f7f338b1f2f784c04254649d257536 Reviewed-on: https://review.coreboot.org/c/31112 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-28src/soc/intel/cnl/chip.h: Fix preprocessor conditionAngel Pons
Commit dc666f5 (soc/intel/cannonlake: Change in SaGv options) added a conditional preprocessor directive, but its condition was incorrect because SOC_INTEL_CANNONLAKE is selected for CNL, CFL and WHL. Thus, an explicit check for !SOC_INTEL_COFFEELAKE is required. While we are at it, clean up the comment above a bit. BUG=b:123184474 Change-Id: I8a6959bb615fb5668cbfe54339747d135bd5a005 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/31095 Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-27src: Fix the warning "type 'hex' are always defined"Elyes HAOUAS
This is spotted using "./util/lint/kconfig_lint" While at it, do the check in C and not the preprocessor. Change-Id: Icfda267936a23d9d14832116d67571f42f685906 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31050 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-25soc/intel/denverton_ns: Enable ACPI using intelblockJulien Viard de Galbert
- Port the existing denverton tables to intelblock - Add C-States table for denverton Note: Removed code is functionally identical to corresponding common code. Tested-on: scaleway/tagada Change-Id: Iee061a258a7b1cbf0a69bcfbf36ec2c623e84399 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/c/25428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-25soc/intel/cannonlake: Export function to set After G3 stateDuncan Laurie
Export the SOC level function to set the After G3 state so it can be changed by the mainboard. The setting will be restored by a normal boot but in some circumstances coreboot wants to ensure that it will be powered up again after a reset. BUG=b:121380403 TEST=update cr50 firmware on sarien and reboot and ensure the host does not power off after the cr50 initiated reset. Change-Id: I6cd572ac91229584b9907f87bb4b340963203c32 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/31056 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-25soc/intel/cannonlake: Disable CpuRatio and SaGv in recoveryDuncan Laurie
Disabling CpuRatio UPD for FSP will ensure it does not force a hard reset to set the CPU Flex Ratio at boot. This is important in a recovery mode boot where the SOC will lose power and need to set the flex ratio again. Disabling SaGv makes recovery mode training faster and mirrors the setting that was done on Skylake. BUG=b:123305400 TEST=reliably enter recovery mode on sarien Change-Id: Ie9664493a980af9acce82faff81f4c4b1355be73 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/31055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-01-25soc/intel/apollolake: Override GLK usb clock gating registerJohn Zhao
It was observed system suspend/resume failure while running RunInDozingStress. Apply correct GLK usb clock gating register value to mitigate the failure. BRANCH=octopus BUG=b:120526309 TEST=Verified GLK clock gating register value after booting to kernel. Change-Id: I50fb16f5ab0e28e79f71c7f0f8e75ac8791c0747 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/30918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-24Revert "soc/intel/denverton_ns: Rewrite pmutil using pmclib"Patrick Georgi
This reverts commit ab1227226ebd78b40783cb200e60711b900352f0. There were significant changes around soc_reset_tco_status() that this code needs to be adapted to. Change-Id: I563c9ddb3c7931c2b02f5c97a3be5e44fa873889 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/31071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-24riscv: ARCH_RISCV_RV{32,64} selects ARCH_RISCVRonald G. Minnich
ARCH_RISCV_RV{32,64} will now select ARCH_RISCV. Change-Id: Ia7a1a8f0bfab20e91b8429dd6dd3e9a4180a0a5b Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/c/31042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Hug <philipp@hug.cx>
2019-01-24soc/intel/denverton_ns: Configure MCAJulien Viard de Galbert
Change-Id: I101eb4f008a13af92bac5ed738a8d1f1f8c65eba Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/c/25433 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-24soc/intel/denverton_ns: Use cpulib in cpu.cJulien Viard de Galbert
Also remove duplicate code Change-Id: I45da6363a35cf6f5855906bb97ed023681d36df7 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/c/25432 Reviewed-by: Vanny E <vanessa.f.eusebio@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Guckian Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-24soc/intel/denverton_ns: Enable Fast StringsJulien Viard de Galbert
Change-Id: I7cee3c40299abf14a24128b1ac14f1823f87a0e1 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/c/25431 Reviewed-by: Vanny E <vanessa.f.eusebio@intel.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: David Guckian Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-24soc/intel/denverton_ns: Rewrite pmutil using pmclibJulien Viard de Galbert
Change-Id: If31e7102bf1b47c7ae94b86d981b762eda0a19e5 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/c/25427 Reviewed-by: David Guckian Reviewed-by: King Sumo <kingsumos@gmail.com> Reviewed-by: Vanny E <vanessa.f.eusebio@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-24soc/intel/common/block/acpi: fix P-States extra entryJulien Viard de Galbert
The ratio_max step is appearing twice when (ratio_max - ratio_min) is evenly divisible by the ratio step. This is because in this case there are no rounding down of ratio_max in the for loop. Thanks Jay Talbott for the step calculation algorithm. Change-Id: I91090b4d87eb82b57055c24271d679d1cbb3b7a7 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/c/25429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-24soc/intel/gpio: Enable configuring GPIO debounce durationKarthikeyan Ramasubramanian
Add new helper macros to enable configuring debounce duration for a GPIO input. Also ensure that the debounce configuration is not masked out. BRANCH=octopus BUG=b:117953118 TEST=Ensure that the system boots to ChromeOS. Ensure that the debounce duration is configured as expected. Change-Id: I4e3cd7744867bcfbaed7d3d96fed4e561afb2cec Signed-off-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-on: https://review.coreboot.org/c/30450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-24soc/intel/common/gpio_defs: Enable configuring GPIO_DW2 pad registerKarthikeyan Ramasubramanian
Currently all the helpers support configuring GPIO_DW0/1 registers. In some architectures there is an additional configuration GPIO_DW2 register that can be used to configure debounce duration etc. Add a helper macro to enable configuring GPIO_DW2 pad register. BRANCH=octopus BUG=b:117953118 TEST=Ensure that the system boots to ChromeOS. Ensure that the current configuration is not disturbed by turning on the GPIO_DEBUG option and verifying the debug output before and after the change. Change-Id: I3e5d259d007fdc83940a43cc4cd4a2b8a547d334 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-on: https://review.coreboot.org/c/30449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-24cbmem_top: Fix comment and remove upper limitPatrick Rudolph
There's no such limit on 64 Bit coreboot builds. * Fix comment in cbmem.h * Remove 4 GiB limit on Cavium SoCs Tested on opencellular/elgon. Still boots Linux as payload. Change-Id: I8c9c6a5ff81bee48311e8bf8e383d1a032ea3a6d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/30609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-01-24soc/cavium/cn81xx: Replace uses of dev_find_slot()Kyösti Mälkki
Change-Id: I9f176caff3b6423121676eb895f5f68a5b926de4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-01-24mediatek/mt8183: Move some initialization into mt8183_early_initYou-Cheng Syu
MT8183 only allows booting from eMMC, so we have to do eMMC emulation from an external source, for example EC, which makes the size of bootblock very important. This CL adds a new function mt8183_early_init, which includes all initializations that should be done in early stages. All mainboards using MT8183 should manually call it in either bootblock or verstage. BRANCH=none BUG=b:120588396 TEST=manually boot into kernel Change-Id: I35d7ab875395da913b967ae1f7b72359be3e744a Signed-off-by: You-Cheng Syu <youcheng@google.com> Reviewed-on: https://review.coreboot.org/c/31024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-01-23soc/intel/cannonlake: Replace device name B0D4 with TCPUSumeet Pawnikar
Replace device name from B0D4 with TCPU for DPTF sensor. This helps to maintain consistency between coreboot and UEFI BIOS. Change-Id: I962d74fc1baa07581d065734aaabb4dcd5e3d247 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/31029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-23soc/amd/stoneyridge/gpio: Allow specifying 0 value for debounce timeoutDaniel Kurtz
It is possible to configure debounce, but leave it disabled by specifying a 0 value for the timeout. Add a define for allowing to do so via the PAD_DEBOUNCE() macro. Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> BUG=b:113880780 BRANCH=none TEST=compile Change-Id: I9de61297b0677cc904535a51c16970eecb52021d Reviewed-on: https://review.coreboot.org/c/30998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2019-01-23soc/intel/baytrail/romstage: Remove unneeded white spaceElyes HAOUAS
Change-Id: I6725d1130a40d3c458a3cd5a116d6e91354ec41b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 06:16:27 +0000