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2015-08-29intel/braswell: allow dirty cache line evictions for SMRAM to stickChiranjeevi Rapolu
The BUNIT controls the policy for read/write access to physical memory. For the SMRAM range the policy was not allowing dirty evictions to the SMRAM when the core causing the eviction was not in SMM mode. This could happen when the SMM handler dirtied a line and then RSM'd back into non-SMM mode. The cache line was dirtied while in SMM mode, but when that particular cache line was evicted it would be silently dropped. Fix this by allowing the BUNIT to honor writes to the SMRAM range while the evicting core is not in SMM mode. The core SMRR msr provides the mechanism for disallowing general access to the SMRAM region while it is not in SMM mode. BUG=chrome-os-partner:43091 BRANCH=None TEST=Run suspend_stress_test and ensure there is no hang SMI handler on suspend-path. Signed-off-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com> Change-Id: Ie794aa3afd54b5e21d0d59a2a7388d507f233537 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 9c481ab339b4e5ab063e2c32b1f0a48b521142b2 Original-Change-Id: I3e7d41c794c6168eb2ad4eb047675bdb1728f72f Original-Reviewed-on: https://chromium-review.googlesource.com/292890 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Hannah Williams <hannah.williams@intel.com> Original-Tested-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: http://review.coreboot.org/11412 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29intel/braswell: Adding conditional statements to turn on/off DPTF WIFI and WWANPrince Agyeman
TEST=Builds and boot on Cyan verified by DPTF team BUG=None BRANCH=None Change-Id: I38ddf4a104eb3183d424b5df6b5eab9d406327ef Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 47cbf3893f7d5f1dfad73f57a71ade9382b0a06a Original-Change-Id: Ide4b3987bfa5e7ec60ee4f47d0663bb71f8330b9 Original-Signed-off-by: Prince Agyeman <prince.agyeman@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/291063 Original-Commit-Queue: Prince Agyeman <popagy@gmail.com> Original-Tested-by: Prince Agyeman <popagy@gmail.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11411 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29intel/braswell: remove CBFS_SIZE option in SoC directoryAaron Durbin
CBFS_SIZE is living as a mainboard attribute. Because of the Kconfig include ordering the SoC *cannot* set the default. BUG=chrome-os-partner:43419 BRANCH=None TEST=None Change-Id: If34e8fd965573fdc7f57b63201dbcb5256e132d6 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: a820b11a0aa3b820c79b1f76b15370d969153175 Original-Change-Id: I7ba637e66878f5ae9caedb63fdd37ed7e375224e Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/289832 Original-Reviewed-by: Martin Roth <martinroth@google.com> Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11410 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29soc/intel/common/fsp_ramstage.c: Don't die when printing HOB infoAlexandru Gagniuc
It doesn't make sense to die() when printing information. In fact the die() are protected by DISPLAY_HOBS config option. This can get confusing, so replace die() calls with printk(). Also since these messages are designed to be informational, keep them at BIOS_INFO log level. Change-Id: Id75b9a54f4aea23074a7489d12809cc2da05f1cd Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11456 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-29soc/intel/common: Add mrc.cache file to CBFS when appropriateAlexandru Gagniuc
The code in mrc_cache.c doesn't check for the presence of 'mrc.cache', and just returns hardcoded value for he location of he MRC cache. This becomes a problem when there is a CBFS file at the same location, which can get overwritten. A CBFS file is created to cover this region so that nothing can be added there. This has the advantage of creating a build time error if another cbfs file is hardcoded over the same region. The default location of the MRC cache is also moved to 4G - 128K to ensure that it defaults to something within CBFS. Change-Id: Ic029c182f5a2180cb680e09b25165ee303a448a3 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11440 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-28soc/*/Makefile.inc: Do not add soc/common as a subdirAlexandru Gagniuc
Aaron Durbin found that soc/common is already included as a subdir via the wildcard in Makefile.inc: subdirs-y += $(wildcard src/soc/*/*) Since the entire file is protected by CONFIG_SOC_INTEL_COMMON, there is no problem with including it for every platform. On the other hand, when it is included by the skylake and braswell makefiles, any rule is duplicated. As a result fix the braswell and skylake makefiles. Change-Id: If5bad903c78dbce418852935ee55cdc7162b3b2d Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11439 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-08-28t210: sdram_lp0: also save EmcBctSpare2 fieldYen Lin
Need to save EmcBctSpare2 field to scratch register. Without it, system may not resume from LP0 suspend. BUG=chrome-os-partner:43797 BRANCH=none TEST=able to suspend/resume >30 times on a known failed board Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 6d1623c4c791f79e097193dfbc4bc894ef63e230 Original-Change-Id: I53ebf8c4d4c7cd19827128a84fbd97a377d78ff7 Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/294765 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-(cherry picked from commit ce38d902e889068d0068150c9352c2ecdb2f8815) Original-Reviewed-on: https://chromium-review.googlesource.com/294864 Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Change-Id: I2ff21afbe9278413033101877c2581df51913709 Reviewed-on: http://review.coreboot.org/11401 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-28t210: lp0_resume: apply mbist WAR for audio on resumeChristopher Freeman
When power is cut/restored to audio block, mbist workaround must be reapplied or I2S will not function. Handle this in lp0 resume firmware with the rest of the mbist WAR. This sequence for audio is also present in boot block code for T210. BUG=chrome-os-partner:41249 BRANCH=None TEST=lp0 suspend/resume with audio playback Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 84933da8188f8263c19f38ba37e88e32ca46cb3d Original-Change-Id: Ia6432e8556ee64f528d94f2dc3279b152294e132 Original-Signed-off-by: Christopher Freeman <cfreeman@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/293618 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Anatol Pomazau <anatol@google.com> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Anatol Pomazau <anatol@google.com> Original-Tested-by: Anatol Pomazau <anatol@google.com> Original-(cherry picked from commit 1e529c3e2ff929975fd654ef75396bc98d3b785c) Original-Reviewed-on: https://chromium-review.googlesource.com/293886 Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Change-Id: I3e72bc10f7e2bea2fa5f946e25803a7928ce9276 Reviewed-on: http://review.coreboot.org/11394 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-28rockchip: rk3288: multiple NPLL rate in pll_para_configYakir Yang
Due to HDMI need to set dclk_rate to 27Mhz, and we can't caclu a suitable config paramters for this rate, so we need to multiple rate unless the vco larger then VCO_MAX. When NPLL rate multiple to 54MHz, pll_para_config could caclu a right paramters, and I have verify the clock jitter is okay to HDMI output. Jitter Reports: Dclk Rate NPLL Rate nr/no/nf jitter Margin 27MHz 54MHz 2/10/45 449.0ps +51.0% BRANCH=None BUG=chrome-os-partner:42946 TEST=Mickey board, show right recovery picture on TV, and 480p clock jitter test passed Change-Id: Iaa0a6622e63d88918ed465900e630bdf16fde706 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 59f1552026889f61167cfeaec3def668ba709c10 Original-Signed-off-by: Yakir Yang <ykk@rock-chips.com> Original-Change-Id: Iab274b41f163d2d61332df13e5091f0b605cb65c Original-Reviewed-on: https://chromium-review.googlesource.com/288416 Original-Commit-Queue: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290331 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/11393 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-28rk3288: Set HDMI display mode to 480pYakir Yang
If an HDMI display is detected (EDID can be read), set the display mode to 480p. If for some reason 480p is not supported then we'll fall back to the automatically detected display mode. BUG=chrome-os-partner:42946 BRANCH=firmware-veyron TEST=dev mode screen shows up on Mickey at 480p resolution Change-Id: I2c431eff6673392d3c09e1b66c66ba12ecc6eeb0 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 76203a683c4501f368c50fe24101f68746ddb7f0 Original-Change-Id: I90dea37daa2d78628230d7d47f7ef0e917cbd7bb Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290554 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/11392 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-28rk3288: Ignore EDID errors for HDMIDavid Hendricks
Assume that HDMI implies usage of an external display, and that we want to try bringing up display if we can read an EDID. BUG=chrome-os-partner:42946 BRANCH=firmware-veyron TEST=none; need a display with corrupt EDID to test with Change-Id: I11cc61140d905d70798a7b46db7847f3a1b3c886 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: ace7773623eac57f068ecd50baa9108ce028cf1b Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I9e22984a98b1a5f8cd9645b92dc9b87e8d968f01 Original-Reviewed-on: https://chromium-review.googlesource.com/293548 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/11391 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-28edid: Use edid_mode struct to reduce redundancyDavid Hendricks
This replaces various timing mode parameters parameters with an edid_mode struct within the edid struct. BUG=none BRANCH=firmware-veyron TEST=built and booted on Mickey, saw display come up, also compiled for link,falco,peppy,rambi,nyan_big,rush,smaug [pg: extended to also cover peach_pit, daisy and lenovo/t530] Change-Id: Icd0d67bfd3c422be087976261806b9525b2b9c7e Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: abcbf25c81b25fadf71cae106e01b3e36391f5e9 Original-Change-Id: I1bfba5b06a708d042286db56b37f67302f61fff6 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/289964 Original-Reviewed-by: Yakir Yang <ykk@rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/11388 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-28T210: Add 128MB VPR allocation/carveoutTom Warren
The NV security team requested that coreboot allocate a 128MB region in SDRAM for VPR (Video Protection Region). We had previously just disabled the VPR by setting BOM/SIZE to 0. Once allocated, the VPR will be locked from further access. The ALLOW_TZ_WRITE_ACCESS bit is _not_ set, as dynamic VPR config is not supported at this time (i.e. trusted code can _not_ remap or resize the VPR). BUG=None BRANCH=None TEST=Built and booted on my P5 A44. Saw the VPR region in the boot spew (ID:3 [f6800000 - fe800000]). Dumped the MC VideoProtect registers and verified their values. Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: a7481dba31dc39f482f8a7bfdaba1d1f4fc3cb81 Original-Change-Id: Ia19af485430bc09dbba28fcef5de16de851f81aa Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/290475 Original-Reviewed-by: Hyung Taek Ryoo <hryoo@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Hridya Valsaraju <hvalsaraju@nvidia.com> Original-(cherry picked from commit 9629b318eb17b145315531509f950da02483114f) Original-Reviewed-on: https://chromium-review.googlesource.com/291095 Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Change-Id: I19a93c915990644177c491c8212f2cf356d4d17d Reviewed-on: http://review.coreboot.org/11384 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-28t210: Move page tables to end of TZDRAMFurquan Shaikh
BL31 makes an assumption that TZDRAM always starts at its base. This was not true in our case since coreboot page tables were located towards the start of TZDRAM. Instead move page tables to the end, thus satisfying the assumption that BL31 base is the base of TZDRAM as well. BUG=chrome-os-partner:42989 BRANCH=None TEST=Compiles successfully and boots to kernel prompt Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: aabed336da6e9aea426650c5ca5977ccfc83a21b Original-Change-Id: Ic4d155525dbb4baab95c971f77848e47d5d54dba Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/291020 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-(cherry picked from commit a57127f1655ef311b82c41ce33ffc71db5f9db35) Original-Reviewed-on: https://chromium-review.googlesource.com/290987 Change-Id: Ie7166fd0301b46eb32f44107f7f782c6d79a278c Reviewed-on: http://review.coreboot.org/11383 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-28t210: Pass in required BL31 parametersFurquan Shaikh
BUG=chrome-os-partner:42989 BRANCH=None TEST=Compiles successfully and boots to kernel prompt. Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: ff42f0b4e7f81ea97e571ec03adac16b412e4a37 Original-Change-Id: If78857abfb9a348433b8707e58bea1f58416d243 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/291021 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-(cherry picked from commit 68eeb4bb4b817184eb42f4ee3a840317ede07dae) Original-Reviewed-on: https://chromium-review.googlesource.com/290988 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Change-Id: Id555198bc8e5d77f8ceee710d1a432516bd1ae4c Reviewed-on: http://review.coreboot.org/11382 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-28Smaug: Add NVDEC and TSEC carveoutsTom Warren
The NV security team requested that coreboot allocate the NVDEC and TSEC carveouts. Added code to set up NVDEC (1 region, 1MB) and TSEC (2 regions, splitting 2MB), and set their lock bits. Kernel/trusted code should be able to use the regions now. Note that this change sets the UNLOCKED bit in Carveout1Cfg0 and Carveout4Cfg0/5Cfg0 (bit 1) to 0 in the BCT .inc files (both 3GB and 4GB BCTs) so that the BOMs can be written. Any future revisions to these BCT files should take this into account. BUG=None BRANCH=None TEST=Built and booted on my P5 A44. Saw the carveout regions in the boot spew, and CBMEM living just below the last region (TSEC). Dumped the MC GeneralizedCarveoutX registers and verified their values (same as BCT, with only BOM/CFG0 changed). Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: a34b0772cd721193640b322768ce5fcbb4624f23 Original-Change-Id: I2abc872fa1cc4ea669409ffc9f2e66dbbc4efcd0 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/290452 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-(cherry picked from commit f3bbf25397db4d17044e9cfd135ecf73df0ffa60) Original-Reviewed-on: https://chromium-review.googlesource.com/291081 Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Change-Id: I924dfdae7b7c9b877cb1c93fd94f0ef98b728ac5 Reviewed-on: http://review.coreboot.org/11381 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-28rockchip: rk3288: fix phsync & pvsync bugYakir Yang
Struct edid defien pvsync & phsync as an character, like '+' or '-', so we need to check sync polarity by comparing with characters '+' and '-' instead of treating as boolean. BRANCH=None BUG=chrome-os-partner:42946 TEST=Mickey board, light monitor normally Change-Id: I92d233e19b6df8917fb8ff9a327ccb842c152d65 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 2d22d4b6e7108474f67200e0fb1e4894cd88db85 Original-Change-Id: I14c72aa8994227092a1059d2b25c1dd2249b9db1 Original-Signed-off-by: Yakir Yang <ykk@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/289963 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/11380 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-27skylake: only generate ACPI cpu entries onceAaron Durbin
The acpi_fill_ssdt_generator function pointer is evaluated for each device. As there are multiple cpus in the system the acpi_fill_ssdt_generator was being called more than once creating duplicate ACPI entries because there was more than 1 cpu device. Fix this by only generating them once by removing the acpi_fill_ssdt_generator for the cpu devices, but add the generator to the cpu cluster device. BUG=chrome-os-partner:44084 BRANCH=None TEST=Built and booted on glados. Noted ACPI entries only generated once. Original-Change-Id: I695c30e6150f6d3a79d13744c532f1b658b10402 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294240 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com> Change-Id: I7c85f44ba65398bda668e13db8be531535a983c5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11285 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-08-27skylake: make PAD_CFG_GPI default to GPIO ownershipAaron Durbin
The prior implementation of PAD_CFG_GPI kept the pad ownership as ACPI. The gpio driver in the kernel then wouldn't allow one to export those GPIOs through sysfs in /sys/class/gpio. Fix this by setting the ownership to GPIO. BUG=chrome-os-partner:44147 BRANCH=None TEST=Built and boot glados. PCH_WP gpio is properly exported by crossystem. Original-Change-Id: I9fc7ab141a3fd74e0ff8b3ff5009b007b8a0d69b Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294081 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Ifbb61c5d64bb6a04f140685c70f4681e2babecef Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11283 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-08-25Intel: Remove CACHE_MRC_BIN - 'selected' everywhere in KconfigMartin Roth
The Kconfig symbol CACHE_MRC_BIN was getting forced enabled everywhere it existed. Remove the Kconfig symbol and get rid of the #if statements surrounding the code. This fixes the Kconfig warning for Haswell & Broadwell chips: warning: (NORTHBRIDGE_INTEL_HASWELL && NORTHBRIDGE_INTEL_SANDYBRIDGE && NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE && NORTHBRIDGE_INTEL_IVYBRIDGE && NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE && CPU_SPECIFIC_OPTIONS) selects CACHE_MRC_BIN which has unmet direct dependencies (CPU_INTEL_SOCKET_RPGA988B || CPU_INTEL_SOCKET_RPGA989) Change-Id: Ie0f0726e3d6f217e2cb3be73034405081ce0735a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11270 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-21ChromeOS: Fix Kconfig dependenciesMartin Roth
Add CHROMEOS dependencies to selects for the following Kconfig symbols: CHROMEOS_RAMOOPS_DYNAMIC CHROMEOS_RAMOOPS_NON_ACPI CHROMEOS_VBNV_CMOS CHROMEOS_VBNV_EC CHROMEOS_VBNV_FLASH EC_SOFTWARE_SYNC LID_SWITCH RETURN_FROM_VERSTAGE SEPARATE_VERSTAGE VBOOT_DISABLE_DEV_ON_RECOVERY VBOOT_EC_SLOW_UPDATE VBOOT_OPROM_MATTERS VBOOT_STARTS_IN_BOOTBLOCK WIPEOUT_SUPPORTED This gets rid of these sorts of Kconfig errors: warning: BOARD_SPECIFIC_OPTIONS selects CHROMEOS_VBNV_EC which has unmet direct dependencies (MAINBOARD_HAS_CHROMEOS && CHROMEOS) Note: These two boards would never actually have CHROMEOS enabled: intel/emeraldlake2 has MAINBOARD_HAS_CHROMEOS commented out google/peach_pit doesn't have MAINBOARD_HAS_CHROMEOS Change-Id: I51b4ee326f082c6a656a813ee5772e9c34f5c343 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11272 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-21soc/intel/common: CACHE_MRC_SETTINGS doesn't depend on HAVE_MRCMartin Roth
The FSP platforms use CACHE_MRC_SETTINGS without setting HAVE_MRC, which caused a Kconfig warning. Since CACHE_MRC_SETTINGS doesn't really depend on HAVE_MRC anymore, remove the dependency in Kconfig. Fixes Kconfig warnings: warning: (CPU_SPECIFIC_OPTIONS && CPU_SPECIFIC_OPTIONS && CPU_SPECIFIC_OPTIONS && CPU_SPECIFIC_OPTIONS) selects CACHE_MRC_SETTINGS which has unmet direct dependencies (SOC_INTEL_BROADWELL && HAVE_MRC || SOC_INTEL_COMMON && HAVE_MRC) Change-Id: Id1c108f73d19cbd53b91e1671d57e7752be5d96d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11288 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-08-19Skylake: update cbmem_topRizwan Qureshi
cbmem_top was using CHIPSET_RESERVED_MEM_BYTES to w/a unknown memory regions reserved by fsp for chipset use. With that being removed, the function needs to properly walk though the memory map resulted from fsp memory init to find out the usable address for cbmem root. Refer the FSP 1.3.0 Integartion guide for more details on the Memory Map. systemagent should also use the same mechanism to create the reserved RAM resource. BRANCH=None BUG=None TEST=Build and Boot kunimitsu (FAB3) CQ-DEPEND=CL:*226035,CL:*226045,CL:291573 Original-Change-Id: Id0954cf8e6388e549c7d4df67b468572b5bea539 Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/291611 Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Robbie Zhang <robbie.zhang@intel.com> Change-Id: I4e716170f40936081ce9d4878bf74c75f469f78d Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: http://review.coreboot.org/11239 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-19skylake: Update Memory and Silicon Init paramsRizwan Qureshi
Update the MemoryInit and SilicoInit params as per FSP 1.3.0 release. Note: add SvGv and Rmt to Upd. BRANCH=None BUG=None TEST=Build and Boot FAB3 (Kunimitsu) CQ-DEPEND=CL:*226035, CL:*226045 Original-Change-Id: I62000f6a485fee42ef733c3b548192f2bedfce49 Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/291573 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Change-Id: Iaafa658b4e710fe512526a521cf6c529efb19bf0 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Reviewed-on: http://review.coreboot.org/11238 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-19skylake: correct IO-APIC redirection entry countAaron Durbin
The skylake IO-APIC supports up to 120 redirection entries. In practice it seems FSP has already written to this write-once register. However, it doesn't hurt to actually be correct within the source. BUG=chrome-os-partner:43522 BRANCH=None TEST=Built and booted glados. Original-Change-Id: I666b1b6034f0d37a37ea918f802317f9d5f15718 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/293251 Original-Reviewed-by: Robbie Zhang <robbie.zhang@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I6ddbc89c98c262e2dd0f9f0b76adb092d3043602 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11235 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-19skylake: add gpe.h for ASL generationAaron Durbin
One thing that is brittle is lining up GPE0 bits in ASL and with a board's design proper. This results in open calculated magic numbers. To help alleviate this provide just #defines that C preprocessor can use before handing the source off to the ASL compiler. BUG=chrome-os-partner:43522 BRANCH=None TEST=Built and booted glados. Everything's intact. Original-Change-Id: I359616ebe4bfc83c05bafe0ca36b766efd16dcca Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/293410 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I32513c324b923fa0adbd6a0ee920c27e9b97dd1b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11233 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-17Fix Kconfig: ALWAYS_LOAD_OPROM has unmet dependency VGA_ROM_RUNMartin Roth
Broadwell and Skylake chipsets, along with a few mainboards were selecting ALWAYS_LOAD_OPROM without making sure that the dependency for that symbol was met as well. Looking at the dependencies for VGA_RUN_ROM, we see: PCI && !PAYLOAD_SEABIOS && !MAINBOARD_DO_NATIVE_VGA_INIT Since ARCH_X86 selects PCI, that's always met here. Since Broadwell and Skylake don't have native VGA init yet, that's not needed. - Make sure that VGA_RUN_ROM is selected as well. - Add dependency on !PAYLOAD_SEABIOS for both ALWAYS_LOAD_OPROM and VGA_RUN_ROM symbols where they're selected. Fixes Kconfig warning for these boards and chipsets: warning: (BOARD_SPECIFIC_OPTIONS && BOARD_SPECIFIC_OPTIONS && BOARD_SPECIFIC_OPTIONS && CPU_SPECIFIC_OPTIONS && CPU_SPECIFIC_OPTIONS) selects ALWAYS_LOAD_OPROM which has unmet direct dependencies (VGA_ROM_RUN) Change-Id: I787a87e9467e1fc7afe8b04864b2a89b54824b9f Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11246 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-17soc/intel/skylake/Kconfig: Fix recursive Kconfig dependencyMartin Roth
Change the dependency on CONSOLE_SERIAL to select CONSOLE_SERIAL based on this question. The dependency was causing multiple warnings on every platform tested. src/console/Kconfig:21:error: recursive dependency detected! src/console/Kconfig:21: symbol CONSOLE_SERIAL depends on DRIVERS_UART_8250MEM src/drivers/uart/Kconfig:16: symbol DRIVERS_UART_8250MEM is selected by UART_DEBUG src/soc/intel/skylake/Kconfig:198: symbol UART_DEBUG depends on CONSOLE_SERIAL Change-Id: Ia0426cd150561694081b5ea7c6797d36022c1f57 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11243 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-08-14skylake: fix SMI GPI status handlingAaron Durbin
The current construction for processing SMI GPI events didn't allow for the mainboard to query the state of a particular GPI for the snapshotted SMI event. The skylake part can route GPIs from any (there are design limitations) GPIO group. Those status and enable registers are within the GPIO community so one needs to gather all the possibilities in order to query the state. The call chain did this: southbridge_smi_gpi( clear_alt_smi_status() -> reset_alt_smi_status() -> print_all_smi_status() -> return 0) As a replacement the following functions and types are introduced: struct gpi_status - represent gpi status. gpi_status_get() - per gpi query on struct gpi_status gpi_clear_get_smi_status() - clear and retrieve SMI GPI status mainboard_smi_gpi_handler() - mainboard handler using gpi_status Also remove gpio_enable_all_smi() as that construct was never used, but it also is quite heavy handed in that it would enable SMI generation for all GPIs. BUG=chrome-os-partner:43778 BRANCH=None TEST=Built. Original-Change-Id: Ief977e60de65d9964b8ee58f2433cae5c93872ca Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/291933 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Ida009393c6af88ffe910195dc79a4c0d2a4c029e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11208 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14skylake: enable SMI routed GPIsAaron Durbin
The first pass of the GPIO configuration patch didn't enable the SMI# generation for GPIs marked as SMI routed. Now when a pad is configured as SMI routed the bit for the SMI enablement is set accordingly. BUG=chrome-os-partner:43778 BRANCH=None TEST=Built and booted glados. Confirmed SMI_EN being set for SMI routed GPIOs. Original-Change-Id: I796b68accb7a49b03ef18539861e72fa9d169c26 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/292010 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I3be770234d3f605ae630ecd5cd4cfe4867243999 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11207 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14skylake: clarify and fix gpio macrosAaron Durbin
The gpio pad configuration currently defaults to ACPI owned GPIs. A '0' was used which wasn't so clear. Add a comment and explicitly set it to ACPI. Also, PAD_CFG_GPI_ACPI_SMI wasn't using the _PAD_CFG_ATTRS macro which causes compliation errors if attempted to be instantiated. No piece of code tried to use it so the error was overlooked. Lastly, allow for soc/gpio.h to be included during ASL compilation. That allows for gpio_defs.h to be included and those macros utilized without needing to know the file name and where it lives; just use the generic gpio.h. BUG=chrome-os-partner:43778 BRANCH=None TEST=Built and booted glados. Original-Change-Id: I9dbadb0b494683ab38babfc1ac5e13093ee37730 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/291935 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Id4fa8b65ec1e1537dbf09824c2155119a768807e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11206 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14skylake: provide clarification for FADT gpe0_blk_lenAaron Durbin
Instead of using a hard-coded value leverage the existing definitions to perform GPE0 block length calculations. There are 4 pairs of 32-bit status/enable registers. BUG=chrome-os-partner:43522 BRANCH=None TEST=Built and booted glados. Original-Change-Id: I14d08298b5750c91ce0ac3fa33569813396f7089 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/291932 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I127f026f15180fa79625d4cad96d5e35f85e5090 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11205 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14skylake: remove ec_smi_gpio and alt_gp_smi_enAaron Durbin
The ec_smi_gpio and alt_gp_smi_en devicetree options are goign to be removed. The plan for skylake is to set the settings by the mainboard through either gpio pad configuration or through helper functions. Moreover, these values only allow *1* SMI GPIO configuration in that the following has to be true: alt_gp_smi_en = 1 << (ec_smi_gpio % 24) If not, then another gpio(s) from the same group has the SMI_EN bit set for it. Lastly, remove all the subsequent dependencies as they are no longer used: enable_alt_smi() and gpio_enable_group(). BUG=chrome-os-partner:43778 BRANCH=None TEST=None Original-Change-Id: I749a499c810d83de522a2ccce1dd9efb0ad2e20a Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/291931 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I2e1cd6879b76923157268a1449c617ef2aada9c4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11204 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14skylake: provide GPE0 routing devicetree configurationAaron Durbin
On skylake the GPE0 routing can be dynamically changed to a particular GPIO group. Provide the ability for the mainboard to set the route accordingly. If any of the values in the devicetree are the same the current setting in the PMC register is used. The GPIO communities need to have matching configuration for the plumbing to work properly. BUG=chrome-os-partner:43778 BRANCH=None TEST=Built and booted glados w/ and w/o devicetree changes. Fields are set accordingly. Original-Change-Id: I263d648c8ea8a70b21570f01b333d05a5fa2a4e3 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/291930 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I966d38bc197dbb52a2ba50927c06e243e169afbe Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11203 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14skylake: remove IedSize from chip.hAaron Durbin
IedSize is not used in replace of IED_REGION_SIZE. Drop it from chip.h. BUG=chrome-os-partner:43636 BRANCH=None TEST=Built, booted, suspended, resumed on glados. Original-Change-Id: I38f6518701306c0ffc6d2b2e3fe01624a5eadf54 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290933 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Trybot-Ready: David James <davidjames@chromium.org> Change-Id: I9dd9e689d4d4f7b4770369dcd042d3325990ae32 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11201 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14skylake: pass IED_REGION_SIZE Kconfig to FSPAaron Durbin
Ignore the devicetree.cb setting and use the already existing IED_REGION_SIZE Kconfig option. BUG=chrome-os-partner:43636 BRANCH=None TEST=Built, booted, suspended, resumed on glados. Original-Change-Id: Ic1e760493635218faddeee4003303949305bc529 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290931 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Trybot-Ready: David James <davidjames@chromium.org> Change-Id: I416d4eb186a42d3258682e02a0a2e1db5bb668ac Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11199 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14intel/common: fix stage_cache_external_region()Aaron Durbin
The stage_cache_external_region() calculation is actually dependennt on the properties of the chipset. The reason is that certain regions within the SMRAM are used for chipset-specific features. Therefore, provide an API for abstracting the querying of subregions within the SMRAM. The 3 subregions introduced are: SMM_SUBREGION_HANDLER - SMM handler area SMM_SUBREGION_CACHE - SMM cache region SMM_SUBREGION_CHIPSET - Chipset specific area. The subregions can be queried using the newly added smm_subregion() function. Now stage_cache_external_region() uses smm_subregion() to query the external stage cache in SMRAM, and this patch also eliminates 2 separate implementations of stage_cache_external_region() between romstage and ramstage. BUG=chrome-os-partner:43636 BRANCH=None TEST=Built, booted, suspended, resumed on glados. Original-Change-Id: Id669326ba9647117193aa604038b38b364ff0f82 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290833 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Idb1a75d93c9b87053a7dedb82e85afc7df6334e0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11197 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14skylake: use smm_subregion() during SMM relocationAaron Durbin
The smm_subregion() support allows the SMM relocation to not use duplicated math by calling out the specific regions it wants. IED base is now correct and not pointing outside from SMRAM. BUG=chrome-os-partner:43636 BRANCH=None TEST=Built, booted, suspended, resumed on glados. Original-Change-Id: Ief8940c2ab6320449500ced2121d0cd7ed73af4b Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290930 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Trybot-Ready: David James <davidjames@chromium.org> Change-Id: I00c3284cfacb2a73942640ccfa7912b7d65efb9d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11198 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14intel/common: use external stage cache for fsp_ramstageAaron Durbin
The fsp_ramstage.c code was not taking advantage of the stage cache which does all the accounting and calculation work for the caller. Remove the open coded logic and use the provided infrastructure. Using said infrastructure means there's no need for the FSP_CACHE_SIZE Kconfig variable. Therefore, remove it. BUG=chrome-os-partner:43636 BRANCH=None TEST=Built, booted, suspended, and resumed on glados. Original-Change-Id: I4363823c825b4a700205769f109ff9cf0d78b897 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290831 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Ifd3cc4a538daac687949c5f4cab2c687368d6787 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11196 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14skylake: clean up SMM region calculationsAaron Durbin
The TSEG is defined to be from TSEG->BGSM in the host bridge registers. Use those registers at runtime to calculate the correct TSEG size. Lastly, use a few helper macros to make constants more readable. BUG=chrome-os-partner:43522 BRANCH=None TEST=Built, booted, suspended, resumed on glados. Original-Change-Id: I6db424a0057ecfc040a3cd5d99476c2fb8f5d29b Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290832 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I6890fa450ce8dc10080321aa1a7580e0adc48ad5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11195 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14fsp1_1: fsp_relocate: use struct region_device and struct progAaron Durbin
Using struct prog and struct region_device allows for the caller to be none-the-wiser about where FSP gets placed. It also allows for the source location to be abstracted away such that it doesn't require a large mapping up front to do the relocation. Lastly, it allows for simplifying the intel/commmon FSP support in that it can pass around a struct prog. BUG=chrome-os-partner:43636 BRANCH=None TEST=Built, booted, suspended, and resumed on glados. Original-Change-Id: I034b04ab2b7e9e01f5ee14fcc190f04b90517d30 Original-Signed-off-by: Aaron Durbin <adurbin@chroumium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290830 Original-Tested-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Change-Id: Ibe1f206a9541902103551afaf212418fcc90e73c Signed-off-by: Aaron Durbin <adurbin@chroumium.org> Reviewed-on: http://review.coreboot.org/11193 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14Skylake: Add ASL code to enable GPIO controllerArchana Patni
This patch enables GPIO controller for skylake. It adds community base addresses and offset for Community0, Community1, and Community3. Community2 is not exposed in BIOS or enabled in the kernel driver. Also, clean up the carry over GWAK implementation from BDW. BRANCH=None BUG=chrome-os-partner:42393 TEST=cat /sys/kernel/debug/gpio should list of GPIOs TEST=export a GPIO pin using /sys/class/gpio/export Original-Change-Id: I891c40589d3dbd796cf593626472c7b5674a1ae0 Original-Signed-off-by: Archana Patni <archana.patni@intel.com> Original-Signed-off-by: Subramony Sesha <subramony.sesha@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/291230 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Change-Id: I7481ce682ccae872fddf81b3188c3415d5d3f7d9 Signed-off-by: Archana Patni <archana.patni@intel.com> Signed-off-by: Subramony Sesha <subramony.sesha@intel.com> Reviewed-on: http://review.coreboot.org/11191 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14intel/common: use acpi_is_wakeup_s3() in fsp_ramstage.cAaron Durbin
acpi_is_wakeup_s3() was introduced in upstream coreboot while the FSP support code was written. Move to using that instead of using the romstage_handoff structure directly. BUG=chrome-os-partner:43636 BRANCH=None TEST=Built, booted, suspended, and resumed on glados. Original-Change-Id: I71601a4be3c981672e25e189c98abb6a676462bf Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290720 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I2ae4d9906e0891080481fb58b941921922a989d3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11190 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14skylake: clear write-1-to-clear fields in power regsAaron Durbin
Explicitly clear all write-1-to-clear fields in the appropriate power state registers. That way stale state isn't left around from boot to boot. The MMIO PMC registers are always added such that the resource can be accessed from reg_script. It doesn't hurt to add the resource, and it's actually more informative by attaching the actual resources owned by the device. BUG=chrome-os-partner:43625 BRANCH=None TEST=Built and boot glados. Did global reset. Noticed bits set. Did normal reset and saw those same bits no longer set. Original-Change-Id: Idd412bd6bf2c6c57b46c74f9411bdf8413ddd83e Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290339 Change-Id: Ibef1aefedf6ba006f17f9f94998a10b39cc6bfec Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11186 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14skylake: fix invalid GNVS base addressAaron Durbin
Leaving a sentinel 0xC0DEBABE and fixing it up is is the old way of setting the correct base address for GNVS. One just needs to reference NVSA which is already filled in by the skylake ACPI code. BUG=chrome-os-partner:43611 BUG=chrome-os-partner:43522 BRANCH=None TEST=Built and booted glados. /sys/firmware/log shows up as well as ramoops using the correct address. Original-Change-Id: I1d4979b1bb65faa76316a4ec4c551a7b9b9eed32 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290338 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I25efea73a383215f9365ce91230f79516b0201a6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11185 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14skylake: enumerate the SMI status fieldsAaron Durbin
Provide #defines for the bit fields in the SMI status register. This allows for one to set the callback accordingly without hard coding the index. BUG=chrome-os-partner:43522 BRANCH=None TEST=Built and booted glados. Original-Change-Id: I3e61d431717c725748409ef5b543ad2eb82955c4 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/289802 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I1a91f2c8b903de4297aaa66f5c6ff15f1b9c54f6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11184 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14skylake: set DISB in GEN_PMCON_A register properlyAaron Durbin
DISB (bit 23) in GEN_PMCON_A represents to MRC that DRAM training is complete. However, as a 8-bit write was being performed the bit was never being set. BUG=chrome-os-partner:43516 BRANCH=None TEST=Built and booted to kernel. Rebooted. Noted full memory training was not being peformed. Original-Change-Id: If2a9cc2f80bc38ea86fb0d7ff855ef95540b561b Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290337 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Ic7973e0ec279304797e0b3d83d7378f620f2b548 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11183 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14skylake: fill out gen_pmcon_* bitfieldsAaron Durbin
Open coding bitfields is really annoying as no one knows what they are unless you have a doc in front of you. Fill in the bitfields for the GEN_PMCON_A and GEN_PMCON_B registers. BUG=chrome-os-partner:43522 BRANCH=None TEST=Built and booted glados. Original-Change-Id: Id48de68eaa3896c17d5da2ffb0bcf17062f73e5e Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290336 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I968be9736419e26a771e0a0c3c964d540fbb1efe Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11182 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14skylake: do not overlap resourcesAaron Durbin
FSP was setting up the TCO registers to be mapped at 0x400. However, the SMBus initialization in romstage was mapping its I/O BAR to 0x400 as well. The result seemed to cause the TCO register to be hidden. However, the board was rebooting in depthcharge when the SMBus device was enabled from a TCO timeout. As the TCO timer was halted before the double resource assignment it's not clear how the TCO was getting re-enabled. In either case, the current behavior is wrong. BUG=chrome-os-partner:42407 BRANCH=None TEST=Built and booted glados w/ SMBus enabled. Original-Change-Id: I43c0d67a76abac51ccfd5105245792981fbcd04c Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290363 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I3839290768c27626c3fd2d67d5de94c291c1386e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11180 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14skylake: use native gpio configuration for uartAaron Durbin
Instead of open coding the UART2 gpio configuration use the support library. BUG=chrome-os-partner:42982 BRANCH=None TEST=Built and booted glados. Original-Change-Id: I9637cb995d51b67eb320650d92f8518de0280dca Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/289801 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I7f0e6599df983323f773f1ec6600537c20c15b11 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11176 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 00:25:44 +0000