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2020-07-25soc/intel/baytrail/bootblock/bootblock.c: Move functionsAngel Pons
This reduces the differences between Bay Trail and Braswell. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: I34079985e165ce8d10c7a2b4f0dde15060132208 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43188 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25soc/intel/baytrail: Retype some pointersAngel Pons
This reduces the differences between Bay Trail and Braswell. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: Ia21b588a3ce07e33a7a8d36e1464c0ff5e456c3e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43187 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25soc/intel/tigerlake: Update Pkg C-State latenciesRavi Sarawadi
Update to recommended C-state entry/exit latencies as per BWG(611569) Rev 0.8: section 4.5.3.2.2 BUG=none TEST=Boot to OS and check C-State latencies "cat /sys/devices/system/cpu/cpu0/cpuidle/state*/{name,latency}" Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: Ic1258ecbb355b94889b30d01bceca586525bbe5e Reviewed-on: https://review.coreboot.org/c/coreboot/+/43316 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Shreesh Chhabbi <shreesh.chhabbi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25soc/intel/tigerlake: Set power limits for Tiger Lake Y-SKUSumeet R Pawnikar
Set power limits in devicetree for Tiger Lake Y-SKU based volteer variant boards. BUG=b:152639350 BRANCH=None TEST=Built and tested power limits on volteer variant board. Change-Id: If4f1226473b48365e5962df9fff29910c99007fc Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43607 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25soc/intel/tigerlake: Update Tiger Lake SA IDsDerek Huang
This patch updates Tiger Lake SA DID and report platform. According to doc #613584, remove PCI_DEVICE_ID_INTEL_TGL_ID_U_1 and add below definitions of SA ID for TGL-UP4 skus: TGL-UP4(Y) (4+2): PCI_DEVICE_ID_INTEL_TGL_ID_Y_4_2 0x9A12h TGL-UP4(Y) (2+2): PCI_DEVICE_ID_INTEL_TGL_ID_Y_2_2 0x9A02h Change-Id: Id9d9c9ac3bf39582b0da610e6ef912031939c763 Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43061 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-24soc/amd/picasso: mark usb2_phy_tune struct as packedFelix Held
Since the binary layout of this struct matters, it should be marked as packed. Since all struct elements are uint8_t, this shouldn't result in a different layout though. BUG=b:161923068 Change-Id: I6a390c3a3f35eaf8a72928b4cef0e9f405770619 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43780 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-24soc/intel/common/gpio_defs: Remove unused macro for NFMaxim Polyakov
Since the bufdis parameter (bit 9:8 in Pad Configuration DW0 register) does not affect the pad in native function mode, PAD_CFG_NF_BUF_IOSSTATE_IOSTERM() macro is not required to configure the pad. This macro has not been used, so deleting it will not affect anything. Change-Id: Icce6f130308dbe7032b99539f73688bae8ac17e0 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42913 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-24soc/intel/common/gpio_defs: Undo set TxDRxE in GPI_TRIG_OWN()Maxim Polyakov
IO Standby State can use various settings independently of PAD_CFG_GPI_TRIG_OWN (). Instead, use other existing macros to set this parameter: - PAD_CFG_GPI_IOSSTATE_TRIG_OWN() - PAD_CFG_GPI_TRIG_IOS_OWN() Change-Id: I0f5fbd79f892981eb4534f50ac96a7d0c190f59e Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42912 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-24soc/intel/common/gpio_defs: Improve some GPI macrosMaxim Polyakov
The patch updates existing macros for the GPI: - PAD_CFG_GPI_IOSSTATE_IOSTERM() - PAD_CFG_GPI_IOSSTATE() to allow the user to set the RX Level/Edge Configuration (trig) and the Host Software Ownership (own) fields in addition to IO Standby State (iosstate) and IO Standby Termination (iosterm) in the pad configuration using these macros. Change-Id: I8a70a366e816d31720d341a5d26880dc32ff9b8d Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner
2020-07-24soc/amd/picasso/sb: Gate FCH AL2AHB clocksMatt Papageorge
Gate the A-Link to AHB Bridge clocks to save power. These are internal clocks and are unneeded for Raven/Picasso. This was previously performed within the AGESA FSP but this change relocates it into coreboot. BUG=b:154144239 TEST=Check AL2AHB clock gate bits at the end of POST before and after change with HDT. Change-Id: Ifcbc144a8769f8ea440cdd560bab146bf5058cf9 Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-24soc/amd/picasso/fsp_params: add missing newline between functionsFelix Held
Change-Id: If5d798a410f092e0ce99c16c84809b6b2e30cc2e Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43779 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-24soc/amd/picasso/fsp_params: add asserts for descriptor countFelix Held
With the updated FSP UPD headers there are enough DXIO descriptor slots in the UPD, so we can now add asserts to make sure that the mainboard doesn't pass more DXIO/DDI descriptors than the UPD has slots for. This is part of the DXIO/DDI descriptor handling cleanup. BUG=b:158695393 Change-Id: Ia220d5a9d4ff11707b795b04662ff7eead4e2888 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43435 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-23soc/amd/common/gpio: Fix definition of GPIO_INT_ENABLE_STATUS_DELIVERYFurquan Shaikh
This change fixes the definition of `GPIO_INT_ENABLE_STATUS_DELIVERY` to use `GPIO_INT_ENABLE_DELIVERY` instead of `GPIO_INT_ENABLE_STATUS_DELIVERY`. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I64d912200779875cf121cec4476fd39de74c0223 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-23amd/picasso: rename PCIe descriptor to DXIO descriptorFelix Held
Most of the DXIO descriptors are used to configure PCIe engines and lanes, but on Picasso system some of the DXIO lanes can also be configured as SATA or XGBE ports. Change-Id: I28da1b21cf0de1813d87a6873b8d4ef3c1e0e9dd Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43675 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-23soc/intel/xeon_sp/cpx: display SystemMemoryMapHob fieldsJonathan Zhang
SystemMemoryMapHob is necessary for SMBIOS type 17 among other things. It is a fairly large structure, so the pointer to the data instead of the structure itself, is included in the HOB. Use pointer to SystemMemoryMapHob structure to interpret SystemMemoryHob HOB body. Adjust the structure definition to match with CPX-SP ww28 release. Display more fields to ensure the structure definition is correct. TEST=Boot DeltaLake server, and check field values of SystemMemoryMapHob to make sure they are correct: 0x7590a090, 0x00000020 bytes: HOB_TYPE_GUID_EXTENSION f8870015-6994-4b98-95a2bd56da91c07f: FSP_SYSTEM_MEMORYMAP_HOB_GUID ================== MEMORY MAP HOB DATA ================== hob: 0x777f7000, structure size: 0x6c88 lowMemBase: 0x0, lowMemSize: 0x20, highMemBase: 0x40, highMemSize: 0x5d0 memSize: 0x600, memFreq: 0xb76 NumChPerMC: 3 SystemMemoryMapElement Entries: 2, entry size: 16 memory_map 0 BaseAddress: 0x0, ElementSize: 0x20, Type: 0x1 memory_map 1 BaseAddress: 0x40, ElementSize: 0x5d0, Type: 0x1 BiosFisVersion: 0x0 MmiohBase: 0x80000 0x777f7000: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ ... Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I271bcbd6030276b8fcd99d5b4f2c93f034dd9b52 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43336 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-23soc/intel/jasperlake: Add the SkipCpuReplacementCheck configurationV Sowmya
Add SkipCpuReplacementCheck config to control the FSPM UPD used for skipping the CPU replacementment check to avoid the forced MRC training for the platforms with soldered down SOC. BUG=b:160201335 TEST=Build and verify CSE Lite SKU on Waddleddo. Cq-Depend: chrome-internal:3142530 Change-Id: I63fcdab3686322406cf7c24fc26cbb535cc58c8d Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42453 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2020-07-22soc/intel/jasperlake: Move tco_configure to bootblockTim Wawrzynczak
Similar to CB:43313 (SHA bb50c672278), it seems possible for the same problem to come up on jasperlake. Again, it should be harmless to configure the TCO device earlier in the boot flow. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: If95e46124660b4ed457434f727c9f9f7b02b0327 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43539 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-22soc/intel/cannonlake: Move tco_configure to bootblockTim Wawrzynczak
Similar to CB:43313 (SHA bb50c672278), it seems possible for the same problem to come up on cannonlake. Again, it should be harmless to configure the TCO device earlier in the boot flow. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ib8883d27b2a0994a67ec5e044a692a2e853fd680 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43538 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-21soc/intel/tigerlake: Select PLATFORM_USES_FSP2_2Subrata Banik
This patch performs below operations 1. Add support for FSP 2.2 2. Set EnableMultiPhaseSiliconInit to ensure bootloader can call FspMultiPhaseSiInit() API. 3. Provide placeholder to perform require chipset programming (example TCSS) before calling FspMultiPhaseSiInit() API. Change-Id: I15252d2db3f8e75d430b84e86cc5141225a3f981 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-07-21src: Use ACPI macrosElyes HAOUAS
Change-Id: I2cf11b784299708f02fd749dcb887b6d25f86f5b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-21soc/intel/baytrail: Add new CPUID 0x30679Mate Kukri
This ID is reported by newer mfg date SOCs. Needed for newer GBYT4 boards. Change-Id: I6af746d66a15f67553de1dc1c925e5cb0b181898 Signed-off-by: Mate Kukri <kukri.mate@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-21soc/intel/xeon_sp/cpx: remove unused gpio.hMaxim Polyakov
This file does not contain useful information and is not used to build the image. The common GPIO driver from soc/intel/common uses layout in lewisburg_pch_gpio_defs.h [1,2] file, which is correct for all chipsets from the Lewisburg family: C621, C621A, C622, C624, C625, C626, C627, C627A, C628, C629, C629A [3] [1] src/soc/intel/xeon_sp/include/soc/lewisburg_pch_gpio_defs.h [2] https://review.coreboot.org/c/coreboot/+/39425 [3] Intel document #547817 Change-Id: I1f3ac4afff9e628890df8cec075fd3e42a590172 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43535 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com> Reviewed-by: Bryant Ou <bryant.ou.q@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20src: Report word-sized access for PM1a_EVTAngel Pons
According to the ACPI specification, version 6.3: Accesses to the PM1 status registers are done through byte or word accesses. The same is said about the PM1 Enable registers. Therefore, reporting dword-sized access is wrong and means nothing anyway. Since some other platforms use word-sized access, use word everywhere for consistency. Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of the patch train, both operating systems are able to boot successfully. Change-Id: I6f85c9a4126f37ab2a193c3ab50a6c8e62cf6515 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43432 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20src: Make HAVE_CF9_RESET set the FADT reset registerAngel Pons
All supported x86 chips select HAVE_CF9_RESET, and also use 0xcf9 as reset register in FADT. How unsurprising. We might as well use that information to automatically fill in the FADT accordingly. So, do it. To avoid having x86-specific code under arch-agnostic `acpi/`, create a new optional `arch_fill_fadt` function, and override it for x86 systems. Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of the patch train, both operating systems are able to boot successfully. Change-Id: Ib436b04aafd66c3ddfa205b870c1e95afb3e846d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-07-20src: Drop useless cache flush settings in FADTAngel Pons
They are ignored if the ACPI_FADT_WBINVD flag is set, which is required on current ACPI versions and only maintained for ACPI 1.0 compatibility. Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of the patch train, both operating systems are able to boot successfully. Change-Id: Ief1219542ba71d18153b64180e0ff60bd1e7687b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-07-20soc/amd/stoneyridge: Select HAVE_CF9_RESETAngel Pons
Looks like some preparation is needed before reset. However, Picasso also needs some special handling and still selects this option without selecting HAVE_CF9_RESET_PREPARE. So, just add HAVE_CF9_RESET for now. Change-Id: I0c6da9a43a28dbee916fd6bda9ae380ebd619edf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43388 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20src: Never overwrite `fadt->flags`Angel Pons
Instead, just flip the desired bits using bitwise operations. As this is initially zero, the resulting value is the same. This allows flags to be set from anywhere regardless of execution order. Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of the patch train, both operating systems are able to boot successfully. Change-Id: Icfd580a20524936cd0adac574331b09fb2aea925 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43387 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20soc/intel/xeon_sp/skx: Clean up FADTAngel Pons
Both `acpi_fill_fadt` and `soc_fill_fadt` set many FADT fields. Since the latter runs later, the values programmed in it overwrite any other values. Drop unused assignments and consolidate everything in a single function. Use `acpi_fill_fadt` as it is mandatory (no weak definition). Change-Id: Ia8248f20dae2b93426f309605bb2076592b08df4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43386 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20amd/{hudson,stoney,picasso}: Drop PM2 settings from FADTAngel Pons
The PM2_CNT register block is no longer needed, as explained in some comments. While they may have been copy-pasted around a lot, they are at least true for Hudson, and it makes sense to assume that they are true for newer chipsets as well. As per the ACPI specification, version 6.3, section 4.8.1.3 (PM2 Control Register): This register block is optional, if not supported its block pointer and length contain a value of zero. Since the FADT struct defaults to zero in coreboot, we don't need to do anything to indicate PM2_CNT is not supported. So, drop unneeded values. Change-Id: Iabc7985c84aabe40ad98fdc9fc6ccbbab0a516c1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43381 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20src: Drop useless PM1b settings from FADTAngel Pons
None of the currently-supported chips has PM1b_EVT nor PM1b_CNT event register blocks. According to the ACPI specification, version 6.3, sections 4.8.1.1 and 4.8.1.2 (PM1 Event/Control Registers): If the PM1b_EVT_BLK is not supported, its pointer contains a value of zero in the FADT. If the PM1b_CNT_BLK is not supported, its pointer contains a value of zero in the FADT. Since the FADT struct defaults to zero in coreboot, we don't need to do anything with PM1b for now. So, drop unneeded writes to PM1b fields. Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of the patch train, both operating systems are able to boot successfully. Change-Id: Iff788b2ff17ba190a8dd9b0b540f1ef059a1a0ea Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43380 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20src: Drop useless GPE1 settings from FADTAngel Pons
None of the currently-supported chips has a GPE1 block. The ACPI spec, version 6.3, section 4.8.1.6 (General-Purpose Event Registers) says: If a generic register block is not supported then its respective block pointer and block length values in the FADT table contain zeros. Since the FADT struct defaults to zero in coreboot, we don't need to do anything with GPE1 for now. So, drop the unneeded writes to GPE1 fields. Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of the patch train, both operating systems are able to boot successfully. Change-Id: Iefc4bbc6e16fac12e0a9324d5a50b20aad59a6cd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43379 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20soc/intel/cannonlake: Add configs for USB 3.1 Gen2 EV settingsJamie Chen
Add configs for USB 3.1 Gen2 EV settings so that people can set the EV settings per board in device tree. BUG=b:150515720 BRANCH=none TEST=build coreboot and fsp with enabled fw_debug. Flashed to puff and checked the log. All usb configs were set correctly. Signed-off-by: Jamie Chen <jamie.chen@intel.com> Change-Id: Id4860665619095139c329565d433d9eb495cac02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39448 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-19soc/intel/common/gpio_defs: Fix coding styleMaxim Polyakov
Tested with BUILD_TIMELESS=1, Kontron COMe-mAL10 on T10-TNI carrierboard does not change. Change-Id: Ib4b4c28153398b6275728b28bda90e527d97e823 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41035 Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com> Reviewed-by: Michael Niewöhner Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17soc/amd/picasso: Drop the addition of I2S machine device from ACP driverFurquan Shaikh
I2S machine device has its own driver now. So, this change drops the support for adding I2S machine device ACPI node from ACP driver. BUG=b:157708581 Change-Id: I9069d92ae991e05fddcc7d45a2fd21e98c3b0de8 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-17soc/amd/picasso: Add .scan_bus operation for ACP deviceFurquan Shaikh
This change adds `.scan_bus` device operation for ACP device to allow mainboards to add devices under it. BUG=b:157708581 Change-Id: I088bf81d7c7c5f59ade1d2f0dd24e5fc2b1ff876 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43542 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17soc/amd/common/gpio: Add macro for PAD_NCFurquan Shaikh
This change adds a macro `PAD_NC` for configuring no-connect pads. This configures the pad as input with pull-down. Change-Id: I47c41c88ccfebe2c5dd9a24f85a120af9c8f56b5 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-17soc/amd/picasso: Drop _INI and OSFL methodsFurquan Shaikh
This change drops _INI and OSFL methods under \_SB since they are not doing anything useful. _INI only calls OSFL and OSFL initializes OSVR if not already initialized and returns OSVR value. However, OSVR is not used anywhere and hence both these functions can be dropped. BUG=b:153879530 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I4f3e1c93a855006cc115087fded20bfb76c1133e Reviewed-on: https://review.coreboot.org/c/coreboot/+/43515 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17soc/amd/picasso: Move PMOD global variable to globalnvs.aslFurquan Shaikh
Global variable `PMOD` that stores the interrupt mode used by OS is required by all mainboards. This change moves the variable definition to globalnvs.asl under picasso. Additionally, ACPI spec says that BIOS should assume interrupt mode as PIC until _PIC() method is called by OS. Thus, this change also updates the default value of PMOD as 0 i.e. PIC mode. BUG=b:153879530 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I731c03d965882281a7a23f55894451210ba72274 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43514 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17soc/amd/picasso: Drop empty method CIRQFurquan Shaikh
This change drops empty method CIRQ() from pci_int.asl. BUG=b:153879530 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ib342dcbc52cfacbd73a8a50ee087d97562d94c97 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43513 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17soc/amd/picasso: Use read-modify-write for ACP_I2S_PIN_CONFIGFurquan Shaikh
This change uses read-modify-write to update ACP_I2S_PIN_CONFIG instead of a write operation since the other bits in the register are reserved. Change-Id: Ic64e1907858ec293c5f759e627d19c00d748a30e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43503 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17soc/amd/picasso: Configure ACP_PME_EN and ACP_I2S_WAKE_ENAkshu Agrawal
This change adds support for configuring ACP_PME_EN and ACP_I2S_WAKE_EN using the mainboard setting for `acp_pme_enable` and `acp_i2s_wake_enable` in the devicetree. This is required to get I2S_Wake event on headset jack plug/unplug when using CODEC_GPI pad. BUG=b:146317284,b:161328042 Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Change-Id: I522d7497940f499fbc3181d866f2b44e979bba7a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/1969104 Reviewed-by: Raul E Rangel <rrangel@chromium.org> Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43495 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16soc/amd/picasso: remove unused fadt_pm_profile devicetree settingFelix Held
commit 56da63c3dc3f50cfac541c779b608e1bae9e635c removed overriding that field in the FADT. Change-Id: I0c8ff9ab125129dc856949c47a3a0c14e4109c73 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43417 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16soc/amd/common: Don't get eSPI address from PCI if not on x86Martin Roth
Exclude lpc_get_spibase() on the PSP. This also simplifies the espi_get_bar() function. BUG=b:159811539 TEST=Build & boot trembyle; Verify address in PSP & x86 Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I5927dd40610860b54bb35a7e5b03ddb731597745 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43468 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16soc/amd/picasso: Get rid of VERSTAGE_SIZEMartin Roth
Currently, the code and data in psp_verstage is ~59K. Adding the code to save vbnv to the SPI rom increases that to 66K. Getting rid of VERSTAGE_SIZE allows verstage to grow as it needs to. BUG=b:161366241 TEST=Build & Boot Morphius with VBOOT_VBNV_CMOS_BACKUP_TO_FLASH enabled Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ic6853b70073f9e781fc10402a2a47c9c8e0d49d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43486 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16soc/amd/stoneyridge: Remove unused SPI #definesMartin Roth
These #defines are not used, and conflict with #defines in amdblocks/spi.h BUG=None TEST=Build stoney platforms Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I29b77a6b21a4deda6f28f5b057988cf3921540e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43485 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-07-16soc/amd/picasso/acpi,mb/{zork,mandolin}: Stop clearing PciExpWakeStatusRaul E Rangel
The kernel already clears this: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/master:src/third_party/kernel/v5.4/drivers/acpi/acpica/hwregs.c;l=390 No reason to have the firmware do it as well. BUG=b:153001807, b:154756391 TEST=Build Trembyle, boot, suspend, and resume and didn't see any ACPI errors. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia5c79fb95dc885eaef8abc4257b6ba18c1ef1b66 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-16soc/amd/picasso,mb/{zork,mandolin}: Remove invalid UPWS variableRaul E Rangel
PMx0EE is not defined in the Picasso PPR. BUG=b:153001807, b:154756391 TEST=None Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I98caf0cd2d0bdcf19de2b945dcf74f5cf7354769 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-16soc/amd/picasso: Drop mainboard_romstage_entry_s3Furquan Shaikh
mainboard_romstage_entry_s3() was dropped from zork (CB:43476). This function call in picasso does not do anything and hence is being dropped. BUG=b:154351731 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I10e15422d7eef5af9c19737c32e433718b6479d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43477 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16soc/intel/common/block/pmc: Select PMC on mainboard basisTim Chu
Currently the common soc code automatically selects POWER_STATE_DEFAULT_ON_AFTER_FAILURE which making other mainboard options unselectable. However, there're some cases that power state should change to different states after reapplying power. Make POWER_STATE_DEFAULT_ON_AFTER_FAILURE default y but do not select it in soc code so that we can disable it and select other options in the mainboard code. Tested on OCP Delta Lake. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: Ifa853d81ee9477d2440ceaa67b2bd6b863ee52c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43338 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-16mb/ocp/deltalake: Config PCH PCIe ports in devicetreeMorgan Jang
Tested on OCP Delta Lake with lspci checking if PCIe speed is changed are expected. Change-Id: I189027c403814d68db2b7c5f41fc254a293fe3a1 Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-26 13:01:29 +0000