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2021-02-12soc/amd/picasso: move bert_reserved_region to common/block/cpu/noncarFelix Held
The same functionality will eventually be needed on Cezanne. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib49124c2c774ad3352ea2f7d8d827388029be041 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-12soc/amd: select ACPI_AMD_HARDWARE_SLEEP_VALUES in common ACPI codeFelix Held
Change-Id: Ib03c6799017c9f51f3ffac8400c85675ac5d63f1 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-12soc/amd/picasso/psp: move to common code and rename to psp_smm_gen2Felix Held
Change-Id: I771a7d36eea7307754386824190624a09c0e38f7 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-12soc/intel/broadwell: Use southbridge common RCBAAngel Pons
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I94953bed3f331848271464bee829f8209167f150 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-12soc/amd/*/Kconfig: remove redundant SMM_TSEG conditionFelix Held
Since SMM is in TSEG on the platforms which is the default, drop the SMM_TSEG condition for the default of SMM_TSEG_SIZE. Change-Id: I7bd965c0794efa12ea4886a55522cc5193a1d3ac Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50498 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11soc/amd/common/block/acpi/pm_state: don't rely on undefined behaviorFelix Held
Change-Id: I5a76a38f8d84666f6b9c0bfffecca064fa82d593 Found-by: Coverity CID 1445994 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-11soc/amd/picasso/fch: remove comment about ForceStpClkRetryFelix Held
The corresponding bit is marked as reserved in the PPR. Also there's no BKDG for Picasso any more; the BKDG was mostly replaced by the PPR. Also fix the style of the comment. Change-Id: Iffdbb9e951cb140e4352ab0f198f72a71ba798dc Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50495 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11soc/amd/common: Fix missing header in amd_pci_utils.hRaul E Rangel
This was causing a build error because size_t wasn't defined. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia467c7d6cc0f71580d0b323cb560c444d53bd7f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50508 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-11ACPI: Move PICM declarationKyösti Mälkki
Variable PICM was not inside GNVS region and can use a static initialisation value. For most AMD platforms PICM default changes from 1 to 0. Fix comments about PICM==0 used to indicate use of i8259 PIC for interrupt delivery. Change-Id: I525ef8353514ec32941c4d0c37cab38aa320cb20 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49905 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11sb,soc/intel: Drop OSYS from GNVSKyösti Mälkki
The value should be set by OSPM using some combination of _OSI() queris in the \_SB._INI() method. To maintain previous behaviour with this commit, boards where GNVS osys initialisation was removed now do the same in ASL. Change-Id: Id4957b12a72fbf7fa988e7ff039e47abcc072e1c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49353 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11mainboards: Drop PWRS from GNVSKyösti Mälkki
Initialize variable to 1 to indicate AC power supply. If platform has EC it will set this correctly based on whether plugged on the charger or not. Change-Id: I3f834cf7563b9e512fcab34cdb7a27a9f0fd31c0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49352 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11soc/amd/cezanne/smihandler: add basic SMI APMC and sleep handlerFelix Held
Only the ACPI enable/disable functionality is implemented and sleep is also not implemented yet. This will be added in future patches. Change-Id: I7701944023ce2e86586679c32c4138d4488768a1 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50488 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11soc/amd/cezanne: select soc-specific ACPI functionalityFelix Held
This doesn't select HAVE_ACPI_TABLES, so no ACPI tables will be generated for now. There's also no globalnvs.asl that corresponds to nvs.h yet. The added nvs.h has some currently unused fields, but still having them in the struct aligns it with Picasso and also might reduce the noise in future ACPI patches a bit. When most of the ACPI code for Cezanne has landed, we need to do a cleanup though. Change-Id: I3d658d284fa67e4da43a89d74686445fd5e93b1f Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-11soc/amd/*/smihandler: use size_t and unsigned intFelix Held
signed int should only be used when we need negative values and in those cases the value shouldn't became negative. Change-Id: Iefac021260ff363c76bf5cd3fe3619ea1dbabdba Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50486 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11soc/amd/*/smihandler: remove replace southbridge references with fchFelix Held
Change-Id: I96fc8082263800b731f1d4d9ecdc8a99c28bff32 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50485 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11soc/amd/cezanne/chip: set device operations for UART MMIO devicesFelix Held
Change-Id: I5df3a61741f05364e2c20725b0b85164b197dbdc Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50484 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11soc/amd/cezanne: add empty mp_init_cpusFelix Held
Change-Id: I845a7e2cfea58ca08cd2a6f0d884dbbbe1a7bdef Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50483 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11soc/amd/cezanne/cpu: add basic zen_2_3_init functionalityFelix Held
The MCA MSRs aren't getting cleared and no microcode update gets applied for now. Both will be added later. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I38ce5d11787ffefdd0183c5540ae2683158cbee8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50482 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11src: Remove unused <arch/cpu.h>Elyes HAOUAS
Change-Id: I1112aa4635a3cf3ac1c0a0834317983b4e18135a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-11soc/intel/broadwell: Remove _ADR from SerialIO ACPI devicesAngel Pons
SerialIO is in ACPI mode for google/auron and intel/wtm2, and is disabled for google/jecht and purism/librem_bdw. Since Broadwell SerialIO is never used in PCI mode, _ADR can safely be dropped. Change-Id: I9a99b8209b5c139146012aa4a92f563692b62c5e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-02-11soc/intel/xeon_sp; Remove unneeded whitespace before tabElyes HAOUAS
Change-Id: I56f0d4aa627155ee318362f626347d7990571dcb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50435 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-11soc/amd: fully commonize clear_tvalidFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I90526a566a5fbc19a7368f90421067a6c716614e Reviewed-on: https://review.coreboot.org/c/coreboot/+/50466 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11soc/amd/cezanne/smihandler: add missing southbridge_io_trap_handlerFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4140fbf93e84a2620ffb88e5c65df17b23135553 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50465 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11soc/amd: include cpu/x86/smm directory in common SMM MakefileFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id6be7aa7f295e61f873bfae1fca42260d3b0db78 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50464 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11soc/amd: move southbridge_smi_handler to common codeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I650498321736eee3d33af51216eda1b650f11744 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50463 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11soc/amd: factor out common SMM relocation codeFelix Held
The common code gets moved to soc/amd/common/block/cpu/smm, since it is related to the CPU cores and soc/amd/common/block/smi is about the SMI/ SCI functionality in the FCH part. Also relocation_handler gets renamed to smm_relocation_handler to keep it clear what it does, since it got moved to another compilation unit. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I45224131dfd52247018c5ca19cb37c44062b03eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/50462 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11soc/amd*/smihandler: factor out and rename clear_smi_sci_statusFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifd6c3bebee1ccf7e7e7987d8ae3d9fa654019791 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50460 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11soc/amd*/smihandler: factor out and rename clear_all_smi_statusFelix Held
The old name was misleading, since it doesn't disable the generation of SMIs, but clears the status registers. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iddadbec013091c2e5993a6303e291451c3d1e7ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/50459 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11soc/amd/cezanne: add empty SMM-handlerFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I95908fac3b1e17a16542e5d80001fac3d22d839a Reviewed-on: https://review.coreboot.org/c/coreboot/+/50455 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11soc/amd/stoneyridge: drop empty sb_enableFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9b6e0bd5c7358e2f18f929d5b098d95acbf59a5c Reviewed-on: https://review.coreboot.org/c/coreboot/+/50437 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10soc/amd/cezanne/fch: add HAVE_SMI_HANDLER case to fch_init_acpi_portsFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie7bab29ae8d0e28c392210f8dcbaa4441ca61114 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50454 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10soc/amd/stoneyridge/chip: rewrite enable_dev as switch case statementFelix Held
This also aligns Stoneyridge with Picasso and Cezanne. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I35bf9915e3502c22e9dd9efa80b00a1ce70f187d Reviewed-on: https://review.coreboot.org/c/coreboot/+/50436 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10soc/amd/cezanne: Add verstage supportRaul E Rangel
Setup the config required to support verstage. The offsets are the same as picasso. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I82874d649db3c9c370e32841e6a9898efb70082e Reviewed-on: https://review.coreboot.org/c/coreboot/+/50342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-02-10soc/amd/common/psp_gen2: print error for uninitialized MSR_PSP_ADDRFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8b6362a9eb2344293dad22357651f646774af789 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50448 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10soc/amd/common/block/psp: factor out soc_get_psp_base_addressFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib73ac92e69f1be5852a1406ba714acb6a8a04989 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-10soc/amd/cezanne: Enable SOC_AMD_COMMON_BLOCK_SPIRaul E Rangel
Required so we pass SPI information down to depthcharge. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4ce819b537333c28d394c925331e3dbf260b7732 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-10soc/amd/common/blocks/lpc: Remove common SPI registersRaul E Rangel
Use the SoC versions instead. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia0b8129b165f8a2e6be6706ab2e3f2d39e1025a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-10soc/amd/cezanne: Add SPI registersRaul E Rangel
These are identical to picasso. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I3ef4c51ef6d656b3b035d97a56b1875b40e89210 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50445 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-10soc/amd/picasso: Add SPI registersRaul E Rangel
The picasso SPI registers are different than the ones defined in amdblocks/lpc.h. The BASE_ALIGNMENT has changed and the PSP_SPI_MMIO_SEL bit has been added. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I0b5a0c88c6dbb95cdbc62b949a7d30bfad1fa725 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-10soc/amd/stoneyridge: Add SPI registersRaul E Rangel
This is a copy/paste of amdblocks/lpc.h. The registers are different for picasso and cezanne, so I'm moving them to soc. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4dfadcdc025d3581cb1423e9793a9b2181742b9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/50443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-10soc/intel/xeon_sp/include/soc/acpi_asl.h: Convert to ASL 2.0Elyes HAOUAS
Change-Id: Ie1d31b9d02584b97b85afe970894cfe557174733 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50324 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-02-10soc/intel/skylake: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: Iea915b60d8ec9a1a7a2aa5926b0277cae58113a6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-02-10soc/intel/skylake/acpi: Add PEP tableBenjamin Doron
PEP table is applicable to Skylake platform as well. It is required to make the kernel load `intel_pmc_core`. Skylake boards can also use S0ix hooks. Tested on an out-of-tree Acer Aspire VN7-572G (Skylake-U), intel_pmc_core kernel module is loaded and reports statuses predictably via debugfs. Change-Id: I08d8c1fde4f447e9292a0508649f802fdc2721e1 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49140 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10soc/amd/common/block: Fix guards for PSP transfer bufferRaul E Rangel
The transfer buffer is only required when using VBOOT_STARTS_BEFORE_BOOTBLOCK. The VBOOT workbuffer is only required when VBOOT_STARTS_BEFORE_BOOTBLOCK or VBOOT_STARTS_IN_BOOTBLOCK. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I444bede3f2b716e1900e7621453351d7fddadaa3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-10soc/amd/common/block/cpu/noncar: Remove unneeded whitespace before tabElyes HAOUAS
Change-Id: Ib88358ca26876cd25247cd9619fb2b70f6859ac2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-10soc/amd/picasso/smihandler: replace southbridge.c in comment with fch.cFelix Held
southbridge.c was renamed and split into early_fch.c and fch.c. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie439e746fb3dfe9ec865481a76a09eab378242bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/50458 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10soc/amd/cezanne/chip: add empty set_mmio_dev_opsFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2ac5fcd17b6aed464a0d1e55f2860574501f7a8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/50439 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-10soc/amd/cezanne/chip: add empty cpu_bus_opsFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I658294c84d64c7de0ccfa74b0e830d787a3a42fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/50438 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10soc/amd/block/psp/psp: raise log level of PSP failure messagesFelix Held
If the PSP didn't like a command this should be at least a warning on the console and not just a debug message. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If7e5f6320631cca86813e98f82b8c0c21bf18af1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-10soc/intel/broadwell/pch: Simplify PCI RMW operationsAngel Pons
This reduces the differences between Lynx Point and Broadwell. Change-Id: Ib53d73e3f89c538ba0f052a98c7aabe815a59472 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46891 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-14 18:44:24 +0000