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2021-01-21soc/intel/quark: Add pwrs in <soc/nvs.h>Kyösti Mälkki
For the time being every soc/intel selects ACPI_SOC_NVS and pwrs is a required field for the common initialisation implementation of followup work. Change-Id: I4a0c7eb35f0646898e49fad15c6448607c398731 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49493 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-21soc/intel/cannonlake: Allow RP#1 usage for ClkSrcJeremy Soller
0 is converted to not used, so use a special value to allow using PCIe root port #1. Change-Id: I2d64afc9bb4627913492edad8f36566e7fb18166 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-01-21soc/intel/common/pcie_rp.h: Fix comment styleFurquan Shaikh
This change updates pcie_rp.h to reflow the comment blocks to fit within 80 columns to match the original style of the file. This addresses comment received on CB:49370 (https://review.coreboot.org/c/coreboot/+/49370/comment/0f3fe10d_4e218b5f/). Change-Id: I565ad602e0e3a2ee09e8345479d82e2ce0a31fd0 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-01-21soc/intel/alderlake: Disable Internal Gfx based on SOC_INTEL_DISABLE_IGDSubrata Banik
Make IGD disable when mainboard user selects SOC_INTEL_DISABLE_IGD. TEST=Able to get depthcharge pre-OS splash screen with AMD Radeon RX 5700 PCI-E DGPU when mainboard user selects SOC_INTEL_DISABLE_IGD. Change-Id: Ibbe9c8c4d77018de83815d7d203284b1fbc0da58 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-21soc/intel/common/graphics: Add new Kconfig SOC_INTEL_DISABLE_IGDSubrata Banik
This SOC_INTEL_DISABLE_IGD Kconfig will allow to skip IGD initialization using FSP GOP and eventually disable the IGD. TEST=Able to get depthcharge pre-OS splash screen when mainboard user selects SOC_INTEL_DISABLE_IGD with below HW/FW/SW configuration: HW: ADLRVP + AMD Radeon RX 5700 PCI-E DGPU FW: coreboot with depthcharge as payload for ADLRVP and OpRom for AMD PCI-E DGPU SW: Chrome OS RC10 release Change-Id: I465541cb45c9022d53a5beb3fff1f80660c357c9 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49470 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-20soc/amd/cezanne/Kconfig: select IDT_IN_EVERY_STAGEFelix Held
This adds interrupt handlers that end up calling x86_exception(). Change-Id: I3dce539b6f1ef300cf16f20224744a75100f60b8 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49726 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-01-20soc/amd/picasso/Kconfig: drop EHCI_BARFelix Held
Picasso doesn't have any EHCI controllers, so it can't support EHCI debug, so there is no need to specify a MMIO address for the early EHCI BAR configuration. Change-Id: I5e904c160c68805a8606a8b2d1ab4fb6172066e7 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-01-20soc/amd/picasso/Kconfig: drop HAVE_USBDEBUG_OPTIONSFelix Held
Picasso doesn't have any EHCI controllers, so it can't support EHCI debug. Change-Id: I2dae22c0db294f5334d9796d90f432d6c8d304df Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-01-20soc/intel: fix indentation in intelblocks/lpc_lib.hMichael Niewöhner
Change-Id: I28be6091097f713472d5ca3b8b0921ee71238cf0 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-01-20soc/intel/*: drop broken LPC mmio codeMichael Niewöhner
The code for setting the LPC generic memory range uses an array of fixed address ranges not needing explicit decoding, to decide if the address needs to be written to the LGMR register. Most platforms only mistakenly add the PCH reserved mmio range, that is not decoded generally, effectively breaking the mechanism. Only APL uses the array correctly. That code, in it's current state, does not work (except for APL) and currently, there is not a single user. Thus, drop it before people start using it. Change-Id: I723415fedd1b1d95c502badf7b0510a1338b11ac Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-20soc/amd/picasso/mrc_cache.c: Remove unused <bootstate.h>Elyes HAOUAS
Change-Id: Ied235972d24276d7c88a2f50f192d69d24ae6e05 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-01-20soc/mediatek/mt8192: pmic: unlock key protection before initial settingHsin-Hsiung Wang
We need to write some special values to key protection registers before applying init_setting table and lp_setting table to PMIC. Otherwise, those settings won't take effect. After applying init_setting table and lp_setting table, we lock the settings by writing zero to key protection registers. Reference datasheet: MT6359_PMIC_Data_Sheet_V1.5.docx, RH-D-2018-0205. BUG=b:172636735 BRANCH=none TEST=boot asurada correctly Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Change-Id: I593d4e02bf0b62ac297957caf4ae1c1837f1f38d Reviewed-on: https://review.coreboot.org/c/coreboot/+/48954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-20soc/mediatek/mt8192: pmic: add scp voltage initializationHsin-Hsiung Wang
Add scp voltage initialization. BUG=none BRANCH=none TEST=boot asurada correctly Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Change-Id: I68302715ae804fed11bb54f4dfc4e90cde5224df Reviewed-on: https://review.coreboot.org/c/coreboot/+/49355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-20ACPI GNVS: Drop most dev_count_cpu()Kyösti Mälkki
Only amd/picasso and amd/stoneyridge have reference to PCNT and that could be replaced with acpigen. Remove the PCNT name from GNVS OperationRegion elsewhere. Change-Id: I7dd45a840b3585fd24c31fd923b991c34ab4d783 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-19soc/amd: Drop unnecessary <soc/nvs.h> includeKyösti Mälkki
Change-Id: Ia27bc256376c61a7330196a5b4a331dd79386fb6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-19soc/amd/picasso,stoneyridge: Unify set_nvs_sws()Kyösti Mälkki
Change-Id: I673f038b4ce3c4141db128a65be71e7a242dfd28 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-19soc/amd/stoneyridge: Add struct chipset_stateKyösti Mälkki
Struct will be synced with picasso with followups. Change-Id: I5f460cc3849bf1fad1f6da61169893488ccb2b40 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48855 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-19soc/amd/picasso: move HAVE_ACPI_TABLES from mainboards to SoCFelix Held
The SoC code has in implicit dependency on this option, so select it in the SoC code instead of the mainboard code. Change-Id: Iea908c142f4a94a107cf74a31d9f5e29668d4b5b Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-19intel/xeon_sp, mb/ocp/deltalake: Rework get_stack_busnos()Maxim Polyakov
- Return the busno based on the stack number. - Replace pci_mmio_read_config32 with pci_io_read_config32 to get the register value before mapping the MMIOCFG space. - Remove the plural `s` as the function now provides one bus number. Change-Id: I6e78e31b8ab89b1bdcfdeffae2e193e698385186 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-19soc/mediatek/mt8173/dramc_pi_calibration_api.c: Use __func__Elyes HAOUAS
Change-Id: I461012b164bbd6f2d1162a793903aafe0b15e234 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-01-19soc/mediatek/mt8173/pmic_wrap.c: Use __func__Elyes HAOUAS
Change-Id: I3fb4db3fbb72d1444c84b9b66193c26a07561a3f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-01-19soc/mediatek/mt8192: pmic: enable pwrkey long-press shutdown settingHsin-Hsiung Wang
Update the settings of long press shutdown to avoid rtc alarm boot. BUG=b:174546890 BRANCH=none TEST=boot asurada correctly Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Change-Id: I0841e55674f6b26f355ab678a73d4060fe93f27c Reviewed-on: https://review.coreboot.org/c/coreboot/+/49354 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-19soc/mediatek/mt8192: pmic: update initial settingHsin-Hsiung Wang
We found that the switch frequency of vgpu is at 4~5Mhz with high current case (> 3.5A) and is at 2.5Mhz with low current case(< 2.8A). The switch frequency of vgpu should be kept at 2.5Mhz. The root cause is that phase config of vcore is not disabled, it will affect the switch frequency of vgpu. Corret the phase setting at initialization. BUG=b:172636735 BRANCH=none TEST=boot asurada correctly Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Change-Id: I48d3729302de9e3343dce79fe6f5ed045d0296a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49005 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-19soc/mediatek/mt8192: add clkbuf and srclken_rc MT6359P driverYuchen Huang
Add clkbuf and srclken_rc init for low power. Reference datasheet: Document No: RH-D-2018-0205. TEST=boot asurada Signed-off-by: Ran Bi <ran.bi@mediatek.com> Change-Id: I947bf14df7a307bf359c590c2a20265882b3f1be Reviewed-on: https://review.coreboot.org/c/coreboot/+/46878 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-19soc/mediatek/mt8192: Save dramc shuffle result after calibrationHuayang Duan
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: Icfd0923d4bd34ebb082e00e87f262b0d908fe342 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44714 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-19soc/mediatek/mt8192: Add dramc ac timing settingHuayang Duan
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: I10e704868e4cd36a938a669879bb1a8632e73e1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/44713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-19soc/mediatek/mt8192: Get DDR base information after calibrationHuayang Duan
After calibration, we can get ddr vendor id or density info from MR5 or MR8, this helps to make sure the DDR HW is as we expected. Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: Ie62948368716d309aab8149372b2b6093fc33552 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44712 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-18ACPI: Refactor ChromeOS specific ACPI GNVSKyösti Mälkki
The layout of GNVS has expectation for a fixed size array for chromeos_acpi_t. This allows us to reduce the exposure of <chromeos/gnvs.h>. If chromeos_acpi_t was the last entry in struct global_nvs padding at the end is also removed. If device_nvs_t exists, place a properly sized reserve for chromeos_acpi_t in the middle. Allocation from cbmem is adjusted such that it matches exactly the OperationRegion size defined inside the ASL. Change-Id: If234075e11335ce958ce136dd3fe162f7e5afdf7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-18soc/intel/braswell/chip.c: Use __func__Elyes HAOUAS
Change-Id: I96b302f5a1f10daaed017a2453d1568a2e49e4ad Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-01-18soc/intel/xeon_sp/uncore.c: Remove duplicated includeElyes HAOUAS
Change-Id: I2ac1035585b32ba65d0725067cff0c12c9f748c1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-01-18soc/intel/xeon_sp/skx/soc_acpi.c: Remove duplicated includeElyes HAOUAS
Change-Id: Icf4247a0a5fb7950c69c8f229a6629a4fa6980f7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-01-18soc/amd/stoneyridge/romstage.c: Remove repeated wordElyes HAOUAS
Change-Id: I38974b532f41830f49b54444d98e6bd7aa417aba Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18soc/intel/broadwell/bootblock.c: Remove repeated wordElyes HAOUAS
Change-Id: I3aec07d782e4315120a4365a65bdbcbf4a22e6f2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18soc/intel/common/block/include/intelblocks/pmc_ipc.h: Remove repeated wordElyes HAOUAS
Change-Id: I646583f7f0d0e0f6a91bc99b7edda964337d837e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49520 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18soc/intel/common/block/itss/itss.c: Remove repeated wordElyes HAOUAS
Change-Id: Icc4954bcc1540f1935b0e34107febb4a1e947a36 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49519 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18soc/intel/skylake/chip.h: Remove repeated wordElyes HAOUAS
Change-Id: Id5bf9255e9a16a4f311e3b15eb77ad6e4bb13f66 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18soc/nvidia/tegra124/spi.c: Remove repeated wordElyes HAOUAS
Change-Id: I0018ea16f304a0d2cedfbd55525ecabbf2d89aa1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18soc/nvidia/tegra210/spi.c: Remove repeated wordElyes HAOUAS
Change-Id: Iea0c973b2bd493eb69ef76289b5b4fc66ac622f6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49516 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18soc/amd/common/block/smi/smi_util.c: Remove repeated wordElyes HAOUAS
Change-Id: Ifeac919ac7214c1baf877a36fd3d57636fc83563 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-18soc/intel/alderlake: Update PCH and CPU PCIe RP tableEric Lai
According ADL EDS to update the PCH and CPU PCIe RP table. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Idcc21d8028f51a221d639440db4cf5a4e095c632 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-01-18soc/intel/common: Move L1_substates_control to pcie_rp.hEric Lai
L1_substates_control is common define. Move out of soc level. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I54574b606985e82d00beb1a61cce3097580366a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-01-18soc/intel/common/pcie: Allow pcie_rp_group table to be non-contiguousFurquan Shaikh
In case of CPU PCIe RPs, the RP numbers might not be contiguous for all the functions in a slot. Example: In ADL, RP1 is 00:06.0, RP2 is 00:01.0 and RP3 is 00:06.2 as per the FSP expectations. Hence, this change updates the defintion of `struct pcie_rp_group` to include a `start` member which indicates the starting PCI function number within the group. All common functions for PCIe RP are accordingly updated to take the `start` member into account. Thus, in the above example, ADL can provide a cpu_rp_table as follows: { { .slot = PCIE_SLOT_6, .start = 0, .count = 1 }, { .slot = PCIE_SLOT_1, .start = 0, .count = 1 }, { .slot = PCIE_SLOT_6, .start = 2, .count = 1 }, } Since start defaults to 0 when uninitialized, current PCH RP group tables don't need to be updated. Change-Id: Idf80a0f29e7c315105f76a7460c8e1e8f9a10d25 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49370 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-18ACPI: Select ACPI_SOC_NVS only where suitableKyösti Mälkki
Having some symmetry with <soc/nvs.h> now allows to reduce the amount of gluelogic to determine the size and cbmc field of struct global_nvs. Since GNVS creation is now controlled by ACPI_SOC_NVS, drivers/amd/agesa/nvs.c becomes obsolete and soc/amd/cezanne cannot have this selected until <soc/nvs.h> exists. Change-Id: Ia9ec853ff7f5e7908f7e8fc179ac27d0da08e19d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lance Zhao
2021-01-15build system: Always add coreboot.pre dependency to intermediatesPatrick Georgi
They all operate on that file, so just add it globally. Change-Id: I953975a4078d0f4a5ec0b6248f0dcedada69afb2 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-01-15build system: Remove flock calls from intermediate processingPatrick Georgi
Now that intermediate coreboot.pre manipulation is serialized within the build system, remove the flock calls. Change-Id: I8a767918aec5fcb7127ebb19ac46e58bed7967fb Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-01-15soc/mediatek/mt8183: Support byte mode and single rank DDRShaoming Chen
1. Add emi setting to support byte mode and single rank ddr sample 2. Modify initial setting for DDR with different architecture BUG=b:165768895 BRANCH=kukui TEST=DDR boot up correctly on Kukui Signed-off-by: Shaoming Chen <shaoming.chen@mediatek.corp-partner.google.com> Change-Id: Id2845b2b60e2c447486ee25259dc6a05a0bb619b Reviewed-on: https://review.coreboot.org/c/coreboot/+/48300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-15soc/amd/picasso: Generate ACPI CRAT objects in cbJason Glenesk
Add code to collect all required information and generate ACPI CRAT table entries. Publish tables generated from cb, rather than use the tables created by FSP binary. BUG=b:155307433 TEST=Boot trembyle and compare coreboot generated tables with tables that FSP published previously. BRANCH=Zork Change-Id: If64fd624597b2ced014ba7f0332a6a48143c0e8c Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-15soc/intel/braswell: Prevent NULL pointer dereferenceAngel Pons
Exit early if the chipset power state info isn't in CBMEM. Return -1 in order to ensure the one caller of this function exits early as well. Found-by: Coverity CID 1442304 Change-Id: Ifa42ba3024d3144de486d90ed7752820482549bf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49359 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-15cpu/x86/mpinit: Serialize microcode updates for HT threadsPatrick Rudolph
This change affects Intel CPUs only. As most platforms are doing uCode update using FIT, they aren't affected by this code either. Update microcode in MP-init using a single spinlock when running on a Hyper-Threading enabled CPU on pre FIT platforms. This will slow down the MP-init boot flow. Intel SDM and various BWGs specify to use a semaphore to update microcode on one thread per core on Hyper-Threading enabled CPUs. Due to this complex code would be necessary to determine the core #ID, initializing and picking the right semaphore out of CONFIG_MAX_CPUS / 2. Instead use the existing global spinlock already present in MPinit code. Assuming that only pre-FIT platforms with Hyper-Threading enabled and at most 8 threads will ever run into this condition, the boot delay is negligible. This change is a counterproposal to the previous published patch series being much more unsophisticated. Change-Id: I27bf5177859c12e92d6ce7a2966c965d7262b472 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-15soc/amd/cezanne,picasso/uart: remove unneeded struct nameFelix Held
This struct isn't used anywhere else, so there's no need to name it. Change-Id: I22eda07f14096d2b7400e6ab715641ffd68fbc08 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reported-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49444 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-02 18:17:05 +0000