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Change-Id: Iadb4c3c77ecda4df8e48415d246e769ede2ce86d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50648
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Variable OSVR had a static value of 3 and OSFL() did not
actually call _OSI or _OS methods.
The conditional in HDA _INI method of OSVR is dropped and
use of DMA NoSnoop attribute remains disabled to retain
previous behaviour. For soc/amd/picasso a different decision
was made in CB:40782 as HDA _INI method was just dropped and
default configuration enables use of DMA NoSnoop attribute.
Change-Id: I967b7b2afbb43253cccb4b77f6c44db45e2989e4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50592
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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CB:40785 ("soc/amd/hda: Move HDA PCI device from DSDT to SSDT") moved
the HDA device in ACPI from DSDT to SSDT. During this, _INI method
generated in SSDT incorrectly inverted the values for NSEN, NSDO and
NSDI. This change fixes the mistake so that the _INI in SSDT matches
the original _INI in DSDT for HDA device.
Change-Id: I294b561a479b77ab8afb5f3e0de367ad24f3a764
Reported-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Introduce a new flag to disable turbo called 'cpu_turbo_disable'.
Keep the default and enable turbo on all platforms.
Change-Id: Ia23ce4d589b5ecc5515474eea52a40788ae3d3b5
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Add rank_mask based on the rank number and iterate based on that rather
than iterating all values.
Note: LPDDR4 uses a different rank mask.
Ported from u-boot.
Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: I1bff9d20d3d66984c49073aa21212708039d578f
Signed-off-by: Moritz Fischer <moritzf@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Add rank_mask based on the rank number and iterate based on that rather
than iterating all values.
Note: LPDDR4 uses a different rank mask.
Ported from u-boot.
Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: I85f449af9f946ad677808800cdbe59e2001202c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50887
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If1b65ae3dd2b5c8fe7bc29a267d108e4d3a3e567
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50883
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This adds the SMM finalization to Cezanne.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1a2b433d92df2a76979e2e6a3d1dde996303ba78
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50801
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I38d52394b5f6ffb837fa753fc9e82c0450c6aae3
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50505
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This adds the rkclk_ddr_reset() function equivalent for the RK3399.
Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: If1da85064d75bdf49b7555d09257409443c25e8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50889
Reviewed-by: ron minnich <rminnich@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add support for resetting PHY PCTRL for both channel 0 and 1.
On the ROCKPro64 board this allows getting past a pctl_cfg() failure.
Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: I9f807e318ffc63c568d04518c3edd02c1064e185
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50890
Reviewed-by: ron minnich <rminnich@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Clear PI_175 interrupts before attempting training in all relevant
calls.
Ported from u-boot.
Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: Ib73f58265db62494282dbec42ec4bf2950617e12
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50886
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The new name is more consistent with the rest of the MSR definitions.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5666d9837c61881639b5f292553a728e49c5ceb2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50855
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5bd6f74bc0fbe461fa01d3baa63612eaec77b97a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50854
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch changes the memlayout macro infrastructure so that the size
of a region "xxx" (i.e. the distance between the symbols _xxx and _exxx)
is stored in a separate _xxx_size symbol. This has the advantage that
region sizes can be used inside static initializers, and also saves an
extra subtraction at runtime. Since linker symbols can only be treated
as addresses (not as raw integers) by C, retain the REGION_SIZE()
accessor macro to hide the necessary typecast.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ifd89708ca9bd3937d0db7308959231106a6aa373
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Also remove one macro that was only used inside that function.
Change-Id: Id798e08375c5757aa99288ca4a7df923309f4d67
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: Iff6111ab379229daec7a3892c330de6b5f0e5157
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Move WDQL training into its own function to enable better error handling.
Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: I8544d6956ca1ce655093a549e7d2928ac9b279bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50865
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move RL training into its own function to enable better error handling.
Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: I02ffbd9deb3fff3bfd8d6e28d6e6d84a4b8c39ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50864
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move RG training into its own function to enable better error handling.
Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: I12f17123bc963ffa2dec1559343a141406a5e98d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50863
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move WL training into its own function to enable better error handling.
Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: I7917846c51982a2473f11d14c51c270e59e59d74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50862
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move CA training into its own function to enable better error handling.
Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: Iefaec3121afbb3b29858e03f903d2ffc5ac75da0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50861
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Order and group tsel variables in a meaningful way.
No functional changes.
Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: I417e0fbc129c2d9ad1b345bcff2e25ca6eca83bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50866
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This shortens the use of sdram_params variable names to params.
No functional changes.
Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: I122035078ce37fe65b16bb1f3a2b2d58956431aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50860
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Calling data_fabric_write32 with BROADCAST_FABRIC_ID as instance_id
would have caused an infinite recursion, so call the right function
data_fabric_broadcast_write32 for that case instead.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If7f0a80f0430e8bfb29ee510ef86c278e3a42063
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Move this function into the compilation unit where it is called.
Change-Id: Ia4bdcd545827c2564430521a98246fc96bf0ba92
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50796
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reverts commit 64d0ad347b5c9c698547f0ff15779e88a10014f4. In the
current revision 3.001 of the PPR #56569 the register exists and the bit
definitions match.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie7a97843c3dac897f79f229b660b7e30b34eef93
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7f17348b1146a07fcb3e905122d7185b60da962f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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We were missing this, so we ran into the scope assert in
acpi_device_write_pci_dev for the data fabric PCI devices.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I566791527ba839ba52ec5fa28f0f6c25f547d1da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50815
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Now that all ACPI names are moved to the corresponding PCI devices, the
functionality in the chip code isn't needed any more.
TEST=No warnings or errors on coreboot console or in the Linux ACPI
parser.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2d39b6d4bd53cd0ca189fb6f55ca26dab68793fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50822
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0f1dce92475ce0ee05a8d090fc3b3d1e613f62c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50821
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5471f7be41683ef4a14107f38e93339080d01bdd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50820
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I47415be02571240d3cecfdb91cb9f8097c5b7fde
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50819
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7517d81d41422cfa10fabd12ab3da4f61c3f9034
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50818
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This function isn't used outside of the same compilation unit.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I332046341bc7a5a499355f2147296e8c09d7e0ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50817
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Both the IO-APIC and PIC mode PCI IRQ tables are incorrect for ADL; the
2nd field in each package is supposed to be pin, not function number,
and some of the IRQ #s differ from what the FSP programs, therefore
align the ACPI table to match what the FSP is currently programming.
BUG=b:180105941
TEST=boot brya, no more `GSI INT` or `failed to derive IRQ routing`
errors seen in dmesg
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I182be69e8d9ebd854ed74dbb69f4d1f1a539cf2f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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TEST=Boot majolica to linux and see IO-APIC logs
ACPI: Local APIC address 0xfee00000
ACPI: LAPIC_NMI (acpi_id[0xff] high edge lint[0x1])
IOAPIC[0]: apic_id 16, version 33, address 0xfec00000, GSI 0-23
ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)
ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 low level)
ACPI: IRQ0 used by override.
ACPI: IRQ9 used by override.
Using ACPI (MADT) for SMP configuration information
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib8094c3edf401659d9d740e2cc6266ddd5f91da9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic63ca41ae484cc34c560cf78de37dc1cde32f364
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50805
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Since all bridges to the internal buses have the same PCI ID, we can
just add this one ID to the pci_driver struct and don't need to use a
list of PCI IDs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ice024b91f49f03995acbd8dfc8b33d3ae3559dde
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50804
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Without the cast the left shift is done on a 32 bit variable that gets
extended to 64 bits afterwards which results in missing MSBs. To avoid
this, do the cast to 64 bits before the left shift.
Found-by: Coverity CID 1443793, 1443794
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7cfa5b9b6ad71f36445ae2fa35140a8713288267
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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This only makes sense if relocation via MSR is possible, to relocate
APs in parallel. xeon_sp hardware does not support these MSR.
TESTED: ocp/deltalake boots fine. SMM is relocated on CPU 0 just like
all other cores.
Change-Id: Ic45e6985093b8c9a1cee13c87bc0f09c77aaa0d2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0faa94fb20daa50c69f25eae3e99e4519323bf5b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic033fc2817d44ff873f93a45e069c0e8aa0be99f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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The `data->spd_len` option always needs to be initialised. However, it
did not get set when using a mixed memory topology. Correct this bug.
Fixes: commit 859ca18ced83ed3b8b529112da5f214ede3d38b0
Change-Id: I8a165f000e5d52e49de18d7648d02fe76d2dd296
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50786
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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TEST=Able to build and boot ADLRVP.
Change-Id: Ic92271700185977f0be83cbc1d3adde37d5b6253
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50747
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This was replaced by APM_CNT defined in src/include/cpu/x86/smm.h, so
remove the now unused definitions.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibd25dcdb57de14fe42352f01067cedca53712d56
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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n is the default of bool Kconfig options, so no need to have that added
to each option.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8775d84caee6fda95eb7749e96090fe05417e764
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50779
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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I also removed the unnecessary #include in soc.asl.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ifbd79871fd49b18f45d97f64ccd68fa96eaaebce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50572
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This fixes the undefined reference for NVB0, NVB1, and NVB2.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib4ba24b66b9ae7899ccd40f91cdd23074f6afc4b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Add MMCONF_BUS_NUMBER=256 as this was not defined for
this SoC.
Change-Id: I6ba861d3b7d5ac083c9b16c8f6ad179efd403bcd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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