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Update IRQ routing settings.
Extra reference:
- ACPI spec 6.2.13 _PRT
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I53feeab81e82c539fa8e39bf90d3f662f75e6d53
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Update USB & PCIe devices in ASL files as per EHL EDS.
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I8b567127fbdd880ccc0a5e0ca334162f9f4f5164
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Update Pre-emphasis, Transmitter Emphasis & Preemphasis Bias values
for USB_PORT_MID.
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I43eeb0fc410197a559df97b340135fac65c00aa5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48541
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add I2C #6 & #7 and remove GSPI #3 as per EHL EDS.
Also update device function number for GSPI #2 in asl file.
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: If166fefe567a857ca29527d0367197139efbf6c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48540
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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For EHL, SpiProtectionMode is added to HFSTS register #1.
The original Manufacturing Mode is detected via FpfSocConfigLock
instead. If FpfSocConfigLock=1, means it is in Menufacturing Mode,
and it is in EOM (End Of Manufacturing) when FpfSocConfigLock=0.
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I9d1d004a6b5b276e33be80f02cd1197b88d379ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48539
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change updates PCI device definition according to EHL EDS.
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: Ibf7ef3c30deab5398361bc18fc63ac39fc914d8c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48444
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add ddp (display controller) driver that supports overlay, read/write
DMA, etc. The output goes to display interface DSI, DPI or DBI directly.
BUG=b:155713214
BRANCH=none
TEST=Boots correctly on asurada
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
Change-Id: I1ad13175b8304beed9965d609ea3bd721311f154
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46577
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable dsi driver for display.
BUG=b:155713214
BRANCH=none
TEST=Boots correctly on asurada
Signed-off-by: Huijuan Xie <huijuan.xie@mediatek.corp-partner.google.com>
Change-Id: I067db08f5600aeee216f482fec49ab75f75a602a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46574
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The mt8183 dsi driver can be shared with mt819x SoC.
Move dsi.c to common/ folder and rename it to dis_v2.c to
differentiate it from mt8173's dsi driver.
TEST=emerge-kukuki coreboot
Change-Id: I722d3e67f230ab8eb729900cdf15b922eb91a072
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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Add I2C controller for MT8192, and revise the common I2C driver
to support I2C controller running in APDMA async mode. In that
case we have to initiate a different handshake protocol and reset
I2C differently.
BUG=b:155715435
TEST=Asurada boots up to shell
Signed-off-by: Qii Wang <qii.wang@mediatek.com>
Change-Id: I13835e00eb674a93aa5496a9870d1e601e263368
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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Change-Id: I9e91f28659c49927aaa4c7cd67f73bb11258c27c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Change-Id: Ib77e3d088cc07da4e43a63afb863bb90796f9a37
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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The code can likely be factored out to common code, but since I'm not
entirely sure yet that there will be no differences, I'll copy for now
instead.
Change-Id: I5fc158518cf9534ab9727f3305abeb4b34049e76
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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SMBus controller has byte-wide registers. Remove
the word accessors.
Change-Id: If396108308bc8303d84458039b9529ecd83276c9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: Ic1a5c17c789dd79fea8f348d1a9d32d4301ced88
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42825
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reverts commit f38af663d2c2c854859715803da249e6c24032db.
The build error was a spurious ENV_X86 guard in <cbmem.h> that
called for a different clean up.
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Change-Id: I0a995301404b67224be6addbeebf984c4b5c47d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43067
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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We took the assumption the APCB(0x60) and APCB_BK(0x68) are the
same file. For picasso, they are. For later programe, they are not.
Change-Id: Idea7847691c2b511b489c306f04a8cb8945fd057
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Add new helper function to support reading a register from the data
fabric.
BUG=b:155307433
TEST=Boot trembyle with If64fd624597b2ced014ba7f0332a6a48143c0e8c and
confirm read values match expected values.
BRANCH=Zork
Change-Id: If0dc72063fbb99efaeea3fccef16cc1b5b8526f1
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47726
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ibb78661c102e0d0327f3e74173bf98bc40e13960
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48488
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The FSP integration code needs this function to be present. It's not
supposed to be called, but if it is, it'll print an error and call the
SoC's cold reset function.
Change-Id: I15f2622d9d9d0f22e3cf8e6283b578f5933b1a9f
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Skip the ACPI UART debug table if common block UART isn't selected.
Change-Id: I8d627998ca450c32496c90e51aad48f332b40e23
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48247
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move the southbridge_write_acpi_tables declaration from acpi.h to common
lpc_lib.h, as common LPC is always the caller. This removes a duplicate
declaration since all soc/intel devices use common LPC, but not all use
common ACPI. The southbridge_write_acpi_tables function is defined in acpi.c
with the other acpi functions.
Note that this would have the reverse problem if there is ever a non-common
LPC device.
Change-Id: I0590a028b11f34e423d8f0007e0653037b0849a0
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48251
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I24454aa9e2ccc98b2aceb6b189e072e6e50b8b30
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Change-Id: Ibc9a4c05bdfc7cd3cd0eada67563386c95d2b50e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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The actual UART initialization code will be factored out in follow-up
commits.
Change-Id: Ie4ddf1951b230323c5480c4389376c62dd74b0e1
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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This allows factoring out the common initialization for the integrated
UARTs.
Change-Id: I7399a13b9280b732086c6f8e6dfd9f1207d8c8ff
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48508
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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all-y will also add a compilation unit to the verstage on PSP build that
runs on an ARM code instead of a x86 one. At the moment Cezanne doesn't
have verstage on PSP support yet, but since it'll eventually land it
doesn't hurt to already add the comment now.
Change-Id: I15fb66e796cab48737ba5ac463c4c973794a005a
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48521
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Since aoac gets also linked into verstage on PSP, all-y can be used
here.
Change-Id: I74607123ebc8115aa7efbb9a364d9632372b52cb
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48506
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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FCH_AOAC_UART_FOR_CONSOLE will only be used in the code if
PICASSO_CONSOLE_UART is selected, so only check if it's a valid value in
this case.
Change-Id: I103dd8d469a084c7dc7dcf55175b1f77f900adc5
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48485
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Wakes from TBT ports and TCSS devices will show up as PME_B0_STS wakes,
so add checks for wakes from these devices in
pch_log_pme_internal_wake_source.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ie9904c3c01ea85fcd83218fcfeaa4378b07c1463
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47396
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently this XHCI driver assumes the PCH XHCI controller, but the TCSS
or North XHCI block has a similar enough PCI MMIO structure to make this
code mostly reusable.
1) Rename everything to drop the `pch_` prefix
2) xhci_update_wake_event() now takes in a pci_devfn_t for the XHCI
controller
3) soc_get_xhci_usb_info() also now takes a pci_devfn_t for the XHCI
controller
BUG=b:172279037
TEST=plug in USB keyboard while in S0, enter S0ix and verify entry via
EC; type on keyboard, verify it wakes up, eventlog contains:
39 | 2020-12-10 09:40:21 | S0ix Enter
40 | 2020-12-10 09:40:42 | S0ix Exit
41 | 2020-12-10 09:40:42 | Wake Source | PME - XHCI (USB 2.0 port) | 1
42 | 2020-12-10 09:40:42 | Wake Source | GPE # | 109
which verifies it still functions for the PCH XHCI controller
Change-Id: I9f28354e031e3eda587f4faf8ef7595dce8b33ea
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47411
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The xeon_sp ACPI NVS and ramstage NVS were out of sync. Since there
isn't anything uncommon with the soc NVS, use the Intel common NVS.
This covers the NVS cases of common code used by xeon_sp. Update
the mainboards for this change.
Change-Id: Icf422f5b75a1ca7a3d8f3d63638b8d86a56fdd7b
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
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The register name and the name of one bit are slightly different, but
have the same functionality.
Change-Id: Ie49975bb43868cbb2dc986e66dc5b7291e70222f
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48507
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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SSPM is "Secure System Power Manager" that provides power control in
secure domain. The initialization flow is to load SSPM firmware to
its SRAM space and then enable.
Signed-off-by: TingHan.Shen <tinghan.shen@mediatek.com>
Change-Id: Ia834852af50e9e7e1b1222ed1e2be20e43139c62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47786
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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DPM is a hardware module for DRAM power management and for better
power saving in low power mode.
BUG=none
TEST=Boots correctly on Asurada
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Change-Id: I16b341ad63940b45b886c4a7fd733c1970624e40
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46393
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update memory parameters based on memory type supported by
Elkhart Lake CRB:
1. Update spd data for EHL LPDDR4X memory
- DQ byte map
- DQS CPU-DRAM map
- Rcomp resistor
- Rcomp target
2. Add configurations for vref_ca & interleaved memory
3. Add EHL CRB on board LPDDR4X SPD data bin file
4. Update mainboard related FSPM UPDs as part of memory
initialization
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: Ifd85caa9ac1c9baf443734eb17ad5683ee92ca3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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When EHL initial mainboard patch is uploaded, there are some build
errors caused by EHL soc codes. Here are the fixes:
1. include gpio_op.asl to resolve undefined variables in scs.asl
2. remove unused variables in fsp_params.c
3. rearrage sequences of #includes to fix build dependency of
soc/gpio_defs.h in intelblocks/gpio.h
4. add the __weak to mainboard_memory_init_params function
5. add the missing _len as per this patch changes
https://review.coreboot.org/c/coreboot/+/45873
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: Idaa8b0b5301742287665abde065ad72965bc62b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47804
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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MCUPM is the MediaTek proprietary firmware for MCU power management.
TEST=1. emerge-asurada coreboot chromeos-bootimage;
2. See following log during booting.
load_blob_file: Load mcupm.bin in 35 msecs, size 115668 bytes
3. Test suspend/resume by:
a. suspend (on DUT): powerd_dbus_suspend
b. resume (on host): dut-control power_state:on
Change-Id: I50bea1942507b4a40df9730b4e1bf98980d74277
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46392
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds support for loading spm firmware from cbfs to spm sram.
Spm needs its own firmware to enable spm suspend/resume function which
turns off several resources such as DRAM/mainpll/26M clk when linux
system suspend.
BUG=b:159079649
TEST=suspend with command `powerd_dbus_suspend` and
wake up the DUT by powerkey
Signed-off-by: Roger Lu <roger.lu@mediatek.com>
Change-Id: I6478b98f426d2f3e0ee919d37d21d909ae8a6371
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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Use mtk_init_mcu API to load and run sspm firmware.
TEST=emerge-kukui coreboot
Change-Id: I63c4b99342bdebb2a94cbf0c6380b0a6817853e7
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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mtk_init_mcu uses DRAM_DMA section as CBFS buffer.
The change "mediatek/mt8183: Remove DRAM_DMA section" is reverted
for using mtk_init_mcu.
On mt8173 and mt8192, this region is used by DMA hardware and is
marked as non-cacheable resource. On mt8183, this region is reserved
as CBFS buffer, so it is not necessary to be marked as non-cacheable
resource.
Change-Id: I7ce9f68883e2787ee7f3c5066f4c47c5ca315633
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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Add mtk_init_mcu to load the firmware to the specified memory address
and run the firmware. This function also measures the load time and the
blob size. For example:
mtk_init_mcu: Loaded (and reset) dpm.pm in 15 msecs (14004 bytes)
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: Ie94001bbda25fe015f43172e92a1006e059de223
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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The register name and the name of one bit are slightly different, but
have the same functionality.
Change-Id: I025f1c7b2c7643afe245f2275ae6ef45e64b951a
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48487
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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On Stoneyridge some PCI registers were accessed in this compilation
unit, but on Picasso this is no longer the case.
Change-Id: Ifbf65f9724a14d4847af98930759c865453775b4
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48486
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I457188c905167affc1ebcea835a36df822ecb23c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Change-Id: I1c6d32a5498a7adcee3c8c3145f85e9dba26bf7e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Since the IOAPIC in the FCH gets set up in the SMBus code, also select
IOAPIC in Kconfig.
Change-Id: I4163e28ca9e68e5fd36421d90aafc20bce43a174
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48474
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Iaac661fcb7581236ace4b5bf057b3e70289f1c8b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48473
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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The two Socs don't use this functionality and biosram.c in the common
code is the only place where those defines are used, but it doesn't
include soc/iomap.h and has its own definitions instead.
Change-Id: I973df4ab39a94e89ea2ed6ffb639c5a85b8df456
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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The number at the end actually means the max MiB/s. So 52 MHz clock @ 8x
data width, sampled on each clock edge = 104 MiB/s.
According to JEDEC Standard No. 84-B51A (JESD84-B51A), maximum bandwidth
& clock frequency for various MMC bus speed modes are (at x8 bus width):
MMC_Legacy: 26 MB/s at 26 MHz Single Data Rate (SDR)
MMC_HS: 52 MB/s at 52 MHz SDR
MMC_DDR52: 104 MB/s at 52 MHz Dual Data Rate (DDR)
MMC_HS200: 200 MB/s at 200 MHz SDR
MMC_HS400: 400 MB/s at 200 MHz DDR
BUG=b:159823235
BRANCH=zork
TEST=build zork
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7818d8cb5ed5974c60a900477a0aa2ecc904db0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48309
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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