coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2021-01-01	nb/intel/hsw,soc/intel/{bdw,skl,apl},mb/*: unify dt panel settings	Michael Niewöhner
2021-01-01	soc/intel/bdw,nb/intel/hsw: convert panel delays to ms representation	Michael Niewöhner
2021-01-01	soc/mediatek: dsi: Fix EoTp flag	Shaoming Chen
2020-12-31	soc/intel/skylake: Remove device_nvs.h	Kyösti Mälkki
2020-12-31	soc/mediatek/mt8192: Move flash_controller.c to common/	Yidi Lin
2020-12-31	soc/mediatek/mt8192: Add DDR mode register init	Huayang Duan
2020-12-31	soc/mediatek/mt8192: Do dramc duty calibration	Huayang Duan
2020-12-31	soc/mediatek/mt8192: Add dramc 8 phase calibration	Huayang Duan
2020-12-31	soc/mediatek/mt8192: Update initial settings of dramc	Huayang Duan
2020-12-30	drivers/intel/gma: Include gfx.asl by default for all platforms...	Matt DeVillier
2020-12-30	soc/intel/common: Move gfx.asl to drivers/intel/gma	Matt DeVillier
2020-12-30	soc/mediatek/mt8192: eint: unmask eint event mask register	G.Pangao
2020-12-30	soc/intel/cnl: add Kconfig values for GMA backlight registers	Michael Niewöhner
2020-12-30	soc/intel: hook up new gpio device in the soc chips	Michael Niewöhner
2020-12-29	soc/intel/bdw,nb/intel/hsw: correct mask for panel power cycle delay	Michael Niewöhner
2020-12-29	soc/intel/alderlake: Update chipset.cb for TCSS and USB	Eric Lai
2020-12-29	soc/intel/skylake: Add 4 missing root ports to chipset dt	Felix Singer
2020-12-29	sec/intel/txt/Kconfig: Make TXT HEAP and SINIT size configurable	Arthur Heymans
2020-12-29	soc/mediatek/mt8192: Implement dramc base settings for each frequency	Huayang Duan
2020-12-28	soc/intel/apl: Fix indents	Felix Singer
2020-12-28	soc/intel/xeon_sp: Lock PAM and SMRAM registers	Arthur Heymans
2020-12-28	soc/intel/xeon_sp: Lock down IIO DFX Global registers	Arthur Heymans
2020-12-28	soc/intel/xeon_sp: Lock down DMI3 PCI registers	Arthur Heymans
2020-12-28	soc/mediatek/mt8192: add rtc MT6359P driver	Yuchen Huang
2020-12-28	soc/mediatek/mt8192: devapc: add basic devapc drivers	Nina Wu
2020-12-28	soc/mediatek/mt8192: Do dramc pre-settings before calibration	Huayang Duan
2020-12-28	kconfig: remove non-existent source	Jack Rosenthal
2020-12-28	soc/intel/skylake: Enable CHAP device depending on devicetree	Benjamin Doron
2020-12-25	ACPI: Fix some GNVS field comments	Kyösti Mälkki
2020-12-25	sb,soc/intel: Fix GNVS OperationRegion	Kyösti Mälkki
2020-12-25	soc/intel/common/gfx: rename and guard graphics_soc_init()	Matt DeVillier
2020-12-24	soc/intel/xeon_sp/cpx: Disable isoch operation for performance	Johnny Lin
2020-12-23	soc/intel/common: Remove unused SOC_INTEL_COMMON_ACPI	Marc Jones
2020-12-23	src/soc/intel/xeon_sp/acpi.c: Remove unnecessary .h	Marc Jones
2020-12-23	Makefile: Add $(xcompile) to specify where to write xcompile	Raul E Rangel
2020-12-23	soc/intel/alderlake: Enable support for extended BIOS window	Subrata Banik
2020-12-23	soc/intel/alderlake: Add SPI DMI Destination ID	Subrata Banik
2020-12-22	soc/intel/common: Fix XHCI elog driver	Tim Wawrzynczak
2020-12-22	soc/intel/common/block/acpi: Fix get_cores_per_package	Patrick Rudolph
2020-12-22	soc/intel/cannonlake: Add Iccmax and loadlines for CML-S	Gaggery Tsai
2020-12-22	soc/intel/apl/graphics: add missing left-shift	Michael Niewöhner
2020-12-22	sb,soc/intel: Drop unnecessary headers	Kyösti Mälkki
2020-12-22	soc/amd/common/psp: Remove files from bootblock	Marshall Dawson
2020-12-22	soc/amd/stoneyridge: Remove unused psp.h	Marshall Dawson
2020-12-22	soc/mediatek/mt8192: Do dramc software impedance calibration	Huayang Duan
2020-12-22	soc/mediatek/mt8192: Do EMI init before dram calibration	Huayang Duan
2020-12-22	soc/mediatek/mt8192: Do memory pll init before calibration	Huayang Duan
2020-12-22	soc/intel/xeon_sp: Use common block ACPI	Marc Jones
2020-12-21	soc/intel/xeon_sp/skx: Properly set up MTRR's	Arthur Heymans
2020-12-21	soc/intel/xeon_sp: Fix compiling with CONFIG_DEBUG_RESOURCES	Arthur Heymans