coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2017-08-22	soc/intel/cannonlake: Define soc_intel_cannonlake_config	Pratik Prajapati
2017-08-22	soc/intel/skylake: Lock sideband access in coreboot and not in FSP	Barnali Sarkar
2017-08-21	soc/intel/cannonlake: Enable common PMC code for CNL	Lijian Zhao
2017-08-21	soc/intel/skylake: Fix SGX init sequence	Pratik Prajapati
2017-08-21	intel/common/block/sgx: Refactor SGX common code	Pratik Prajapati
2017-08-21	intel/common/mp_init: Refactor MP Init code to get rid of microcode param	Pratik Prajapati
2017-08-21	intel/common/sgx: Use intel_mp_current_microcode() to get microcode pointer	Pratik Prajapati
2017-08-21	soc/intel/cannonlake: Add support for all UART port index	Subrata Banik
2017-08-21	soc/intel/skylake: Add support for all UART port index	Subrata Banik
2017-08-21	soc/intel/cannonlake: Add Kconfig option to select UART index	Subrata Banik
2017-08-21	soc/intel/skylake: Add Kconfig option to select UART index	Subrata Banik
2017-08-21	soc/intel/apollolake: remove duplicate gpio GPE defines	Aaron Durbin
2017-08-21	intel/common/cpu: Add function to get microcode patch pointer	Pratik Prajapati
2017-08-21	soc/intel/common/smbus: Don't clear random bits	Nico Huber
2017-08-19	arch/x86: Sanity checking on HAVE_SMI_HANDLER	Kyösti Mälkki
2017-08-19	soc/intel/skylake: Enable power button SMI when jumping to payload	Furquan Shaikh
2017-08-18	Reinvent I2C ops	Nico Huber
2017-08-18	include/device: Split i2c.h into three	Nico Huber
2017-08-17	soc/intel/common/block: Add functions to common CPU library code	Shaunak Saha
2017-08-17	soc/intel/cannonlake: Add SPI flash controller driver	Lijian Zhao
2017-08-17	intel/cannonlake/chip: Add initial PCI enum support	Pratik Prajapati
2017-08-17	intel/common/block/fast_spi: Add config option to disable write status	Duncan Laurie
2017-08-17	soc/intel/apollolake: Fix CONFIG_FSP_CAR build error	Marshall Dawson
2017-08-17	soc/intel/skylake: Configure FSP to skip ME MBP step	Duncan Laurie
2017-08-16	soc/intel/cannonlake: Add proper support to enable UART2 in 16550 mode	Subrata Banik
2017-08-16	soc/intel/skylake: Add proper support to enable UART2 in 16550 mode	Subrata Banik
2017-08-15	soc/intel/cannonlake: Rectify LPC Lock Enable (LE) bit definition	Subrata Banik
2017-08-15	soc/intel/common/block: Fix PMC common block dependency	Shaunak Saha
2017-08-15	soc/intel/apollolake: Rename SRAM BAR0 and BAR2 macros	V Sowmya
2017-08-15	soc/intel/apollolake: Provide option to use Common MP Init	Barnali Sarkar
2017-08-15	soc/intel/cannonlake: Call into FSP siliconinit	Lijian Zhao
2017-08-15	soc/intel/cannonlake: Add postcar stage support	Lijian Zhao
2017-08-15	soc/intel/common/block: Add LPC Common code and use it for APL	Ravi Sarawadi
2017-08-15	soc/intel/{cannonlake,skylake}: fix PCH_P2SB_EPMASK macro	Aaron Durbin
2017-08-14	stoneyridge: Fix CPU ASL \_PR table	Marc Jones
2017-08-14	i2c: Move to Linux like `struct i2c_msg`	Nico Huber
2017-08-14	soc/intel/cannonlake: Remove unused systemagent registers	Subrata Banik
2017-08-14	soc/intel/cannonlake: Initialize struct member to 0	Subrata Banik
2017-08-14	common/block/lpss: Add CLK read function into LPSS common	Subrata Banik
2017-08-14	stoneyridge: Rename hudson to southbridge	Marc Jones
2017-08-11	soc/cannonlake: Enable SMM code for Cannon Lake	Brandon Breitenstein
2017-08-11	soc/intel/cannonlake: Add missing _PCH_DEV definitions	Furquan Shaikh
2017-08-10	soc/intel/apollolake: Enable UART debug controller on S3 resume	Furquan Shaikh
2017-08-10	soc/intel/skylake: Enable UART debug controller on S3 resume	Furquan Shaikh
2017-08-10	soc/intel/common/uart: Add support for enabling UART debug controller on resume	Furquan Shaikh
2017-08-10	soc/intel/common/lpss: Add lpss_is_controller_in_reset	Furquan Shaikh
2017-08-10	soc/intel/common/uart: Refactor uart_common_init	Furquan Shaikh
2017-08-10	soc/intel/common/block: Add CNL, APL and GLK CPU device IDs	Barnali Sarkar
2017-08-10	soc/intel/apollolake: Add file path check	Hannah Williams
2017-08-09	intel/common/block/smm: Update smihandler to handle gpi	Brandon Breitenstein