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AgeCommit message (Expand)Author
2015-07-29BCRD2: Enable PMIC SVID configJenny TC
2015-07-29skylake: remove the redundant fspNotify in chip final.robbie zhang
2015-07-29skylake: Rework microcode include pathDuncan Laurie
2015-07-24skylake: Fix building without serial consoleDuncan Laurie
2015-07-24tegra210: Fix parameter order of write32()Stefan Reinauer
2015-07-24tegra lp0: fix checkpatch errorsStefan Reinauer
2015-07-23t210: audio: add CLK_V_EXTPERIPH1 clockYen Lin
2015-07-23t210: Enable WRAP to INCR burst type conversion in MSELECTYen Lin
2015-07-23t210: implement MBIST workaroundYen Lin
2015-07-23t210: lp0_resume: set CAR2PMC_CPU_ACK_WIDTH to 0Yen Lin
2015-07-23t210: change memlayout.ldYen Lin
2015-07-23intel: common: Let mainboard supplement FSP memory infoDuncan Laurie
2015-07-23intel/common: Add SMBIOS memory widthLee Leahy
2015-07-23skylake: sanitize pcr header for ACPI and assemblerAaron Durbin
2015-07-23skylake: provide more clarity for PCR accessAaron Durbin
2015-07-21intel/fsp_baytrail: Support Baytrail FSP Gold4 releaseYork Yang
2015-07-21t132: Correct dma_busy functionTom Warren
2015-07-21t210: Add tegra_lp0_resume codeYen Lin
2015-07-21t210: Correct device MMIO rangeJimmy Zhang
2015-07-21skylake: add global reset cause registers to power stateAaron Durbin
2015-07-21skylake: take into account deep s3 in power failure checkAaron Durbin
2015-07-21skylake: read out and report full width of gen_pmcon registersAaron Durbin
2015-07-21Glados: Update Serial IO modes in devicetreeNaveen Krishna Chatradhi
2015-07-21intel/skylake: support 32bit uart8250_mem driver in romstageNaveen Krishna Chatradhi
2015-07-21intel/common: remove printk in pre_console_init()rsatapat
2015-07-21Skylake: Initialize GPIOs for UART2rsatapat
2015-07-21Skylake: Only support UART2 as debug port, clean up the restNaveen Krishna Chatradhi
2015-07-21intel fsp: remove CHIPSET_RESERVED_MEM_BYTESAaron Durbin
2015-07-21Braswell: Remove GOP from normal boot mode.Abhay Kumar
2015-07-21skylake: re-enable PCIe L1 sub statesAaron Durbin
2015-07-21skylake: honor pcie root port settings already in chip.hAaron Durbin
2015-07-21skylake: Show SPI controller if enabled in devicetree.cbDuncan Laurie
2015-07-21braswell: clean up \_PR entriesJagadish Krishnamoorthy
2015-07-17soc/intel: Remove microcode terminatorsStefan Reinauer
2015-07-17skylake: remove whitespace from ASL filesStefan Reinauer
2015-07-16t210: new sdram_lp0_save_params() functionYen Lin
2015-07-16t210: correct odmdata location in bctYen Lin
2015-07-16t210: Reorganize memlayout.ldFurquan Shaikh
2015-07-16t210: SPI driver cleanupFurquan Shaikh
2015-07-16t210: Correct dma_busy functionFurquan Shaikh
2015-07-16t210: Add PINMUX macros for drive strengthFurquan Shaikh
2015-07-16soc/intel: Add Skylake SOC supportLee Leahy
2015-07-16soc/intel/skylake: Use Broadwell as comparision base for Skylake SOCLee Leahy
2015-07-14Braswell: Use CBFS image type nameLee Leahy
2015-07-14azalia: fix up and clean up shrinkage of boilerplate codeJonathan A. Kollasch
2015-07-13tegra124/tegra210: Include stages.h in bootblock.cStefan Reinauer
2015-07-13tegra210: Fix coding style in clock.cStefan Reinauer
2015-07-13t210: Apply A57 hardware issue workaround during cpu startupFurquan Shaikh
2015-07-13t210: Add TZDRAM_BASE param to BL31_MAKEARGSFurquan Shaikh
2015-07-12Change #ifdef and #if defined CONFIG_ bools to #if IS_ENABLED()Martin Roth
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