coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2018-11-05	src/soc/intel/braswell/romstage/romstage.c: Perform RTC init in romstage	Frans Hendriks
2018-11-05	soc/intel/cannonlake: Enable ISH from device	Lijian Zhao
2018-11-05	soc/intel/cannonlake: Remove depreciated UPD selection	Lijian Zhao
2018-11-05	riscv: add support smp_pause / smp_resume	Xiang Wang
2018-11-05	src: Remove unneeded include <arch/ioapic.h>	Elyes HAOUAS
2018-11-05	soc/intel/icelake: Add PID based on Icelake EDS	Aamir Bohra
2018-11-02	mediatek/mt8183: Add AUXADC driver	Po Xu
2018-11-02	soc/intel: Enable GPIO functions in verstage	Duncan Laurie
2018-11-02	soc/intel/icelake: Allow coreboot to reserve stack for fsp	Aamir Bohra
2018-11-01	src: Add missing include <stdint.h>	Elyes HAOUAS
2018-10-31	soc/amd/stoneyridge: Fix get_cpu_count()	Martin Roth
2018-10-31	soc/amd/stoneyridge: Get rid of domain_read_resources	Martin Roth
2018-10-31	soc/intel/apollolake: Revert the w/a nWR_24 setting	John Zhao
2018-10-31	soc/intel/icelake: Open ports 0x60,0x64 for keyboard controller	Shelley Chen
2018-10-30	src: Move shared amd64 and IA32 MSRs to <cpu/x86/msr.h>	Elyes HAOUAS
2018-10-30	soc/amd/stoneyridge: Set IOMMU support to follow device setting	Martin Roth
2018-10-30	soc/amd/stoneyridge: Remove dev_find_slot where possible	Richard Spiegel
2018-10-30	src: Add missing include <stdint.h>	Elyes HAOUAS
2018-10-30	sifive/fu540: correct cbmem support	Philipp Hug
2018-10-29	tegra210_lp0: make sure to build with compiler.h included	Nico Huber
2018-10-27	soc/intel/*: Make FSP header path user configurable	Patrick Georgi
2018-10-26	soc/intel/icelake: Do initial SoC commit	Aamir Bohra
2018-10-26	mediatek/mt8183: Correct MPU ctrl register address	Huayang Duan
2018-10-26	soc/intel/cannonlake: Add back PM TIMER EMULATION	Lijian Zhao
2018-10-25	soc/amd/common/def_callouts.c: Prefer using '"%s...", __func__'	Richard Spiegel
2018-10-25	soc/amd/stoneyridge: Remove "else" after a return	Richard Spiegel
2018-10-25	soc/intel: Consolidate FSP CAR setup and teardown code	Praveen hodagatta pranesh
2018-10-25	soc/intel/cannonlake: Enable S4 sleep state support	praveen hodagatta pranesh
2018-10-25	soc/amd/common/pi: Correct top of DRAM reporting by AGESA	Marshall Dawson
2018-10-24	mediatek/mt8183: Initialize DRAM with a sequence in constant array	Huayang Duan
2018-10-24	vboot: fix CONFIG_RESUME_PATH_SAME_AS_BOOT S3 resume logic	Joel Kitching
2018-10-23	src: Remove unneeded whitespace	Elyes HAOUAS
2018-10-23	soc/amd/stoneyridge: Remove smbus.asl	Richard Spiegel
2018-10-23	soc/intel/common/block/gpio: Allow GPI to be dual-routed	Furquan Shaikh
2018-10-23	soc/intel/common/block/gpio: Configure Tx Disable in IO standby for GPIs	Furquan Shaikh
2018-10-23	soc/intel/apollolake: Add reset code to postcar stage	Patrick Georgi
2018-10-22	intel: Use CF9 reset (part 2)	Patrick Rudolph
2018-10-22	intel: Use CF9 reset (part 1)	Patrick Rudolph
2018-10-22	soc/amd: Implement common reset API	Nico Huber
2018-10-22	soc/samsung/exynos5250: Convert to `board_reset()`	Nico Huber
2018-10-22	soc/mediatek: Convert to `board_reset()`	Nico Huber
2018-10-22	soc/imgtech/pistachio: Convert to `board_reset()`	Nico Huber
2018-10-22	soc/rockchip/rk3399: Convert to `board_reset()`	Nico Huber
2018-10-22	reset: Convert individual boards to `board_reset()`	Nico Huber
2018-10-19	soc/lowrisc: Remove the remains of a LowRISC soc	Peter Lemenkov
2018-10-19	soc/intel/cannonlake: Enable HDA driver support	praveen hodagatta pranesh
2018-10-18	mediatek/mt8183: Add EMI init for DDR driver init	Huayang Duan
2018-10-18	mediatek/mt8183: Add register definitions of DRAM controller	Tristan Shieh
2018-10-18	cpu/amd: Use common AMD's MSR	Elyes HAOUAS
2018-10-18	soc/amd/stoneyridge: Replace double defined MISC MMIO reg. 0x40	Richard Spiegel