coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2016-01-18	intel/skylake: Remove unused devicetree configuration variables	Duncan Laurie
2016-01-18	intel/skylake: provide default VR configuration	Aaron Durbin
2016-01-18	intel/skylake: Add devicetree setting for DDR frequency limit UPD	Duncan Laurie
2016-01-18	intel/skylake: Add elog event for THERMTRIP	Duncan Laurie
2016-01-18	header files: Fix guard name comments to match guard names	Martin Roth
2016-01-17	intel/skylake: disable heci1 if psf is unlocked	Archana Patni
2016-01-17	intel/skylake: During RO mode after FSP reset CB lose original state	Subrata Banik
2016-01-16	intel/skylake: Fix uninitialized variable warning	Martin Roth
2016-01-16	intel/skylake: Add kconfig option to skip Native SD Controller	Subrata Banik
2016-01-16	intel/skylake: Add VrConfig UPD parameters from coreboot	Rizwan Qureshi
2016-01-16	intel/skylake: Enable SkipMpInit token	Rizwan Qureshi
2016-01-15	intel/skylake: Init variable so GCC knows it's set	Martin Roth
2016-01-15	intel/skylake: More UPD params are added for PCH policy in FSP	Rizwan Qureshi
2016-01-15	intel/skylake: Update UPD parameters as per FSP 1.8.0	Barnali Sarkar
2016-01-15	intel/skylake: Add GPIO ACPI Apis.	Subrata Banik
2016-01-15	intel/skylake: add nhlt support	Aaron Durbin
2016-01-14	soc/braswell: Add CPUID for D0 stepping	Divya Sasidharan
2016-01-14	soc/braswell: Fix P-state table	Subrata Banik
2016-01-14	intel/skylake/pcr.c: error out on invalid size in pcr read/write	Martin Roth
2016-01-13	tree: drop last paragraph of GPL copyright header from new files	Martin Roth
2016-01-12	intel/skylake: Remove check for Microcode loaded by ME	Martin Roth
2016-01-08	fsp_baytrail: Add additional PCI space above 4GB	Martin Roth
2016-01-07	intel/braswell: Disable IFD & ME by default so abuild can build	Martin Roth
2016-01-07	Correct some common spelling mistakes	Martin Roth
2016-01-06	intel/braswell: Build in both C0 and 'other' vbios	Martin Roth
2015-12-31	imgtec/pistachio: disable default RPU gate register values	Ionela Voinescu
2015-12-31	imgtec/pistachio: memlayout: update GRAM size	Ionela Voinescu
2015-12-31	imgtec/pistachio: I2C: fix base address for I2C clock setup	Ionela Voinescu
2015-12-31	imgtec/pistachio: identity map SOC registers region	Ionela Voinescu
2015-12-31	imgtec/pistachio: Add SOC_REGISTERS memory region	Ionela Voinescu
2015-12-31	imgtec/pistachio: Use SYS PLL in integer mode	Ionela Voinescu
2015-12-29	mips: add coherency argument to identity mapping	Ionela Voinescu
2015-12-27	mainboard/google/urara: change SYS PLL to 700MHz	Ionela Voinescu
2015-12-27	soc/intel/broadwell: Add back support for EHCI debug setup	Duncan Laurie
2015-12-27	broadwell: Fix SATA Gen3 DTLE configuration registers	Duncan Laurie
2015-12-27	broadwell: Fix CONFIG_SPI_CONSOLE usage	Duncan Laurie
2015-12-26	ACPI: Add hack to avoid IASL warning when reading back registers	Martin Roth
2015-12-22	soc/intel/fsp_baytrail: Make sure i2c bus is < 7	Martin Roth
2015-12-21	imgtec/pistachio: DDR2, DDR3: DLL reset set	Ionela Voinescu
2015-12-21	imgtec/pistachio: DDR2, DDR3: DQS gate early	Ionela Voinescu
2015-12-21	imgtec/pistachio: increase CBFS cache	Ionela Voinescu
2015-12-20	soc/intel/broadwell: Init var before use, only use when needed	Martin Roth
2015-12-17	Drop src/cpu/ indirection for MIPS	Stefan Reinauer
2015-12-17	soc/imgtec/pistachio: add implementation for system reset	Ionela Voinescu
2015-12-17	soc/imgtec/pistachio: Implement hard_reset()	Stefan Reinauer
2015-12-17	soc/intel/fsp_baytrail: Adjust root port INT routing	Martin Roth
2015-12-16	intel/fsp_baytrail: change indent to use tabs	Ben Gardner
2015-12-16	intel/fsp_baytrail: rename include folder baytrail to include/soc	Ben Gardner
2015-12-16	intel/fsp_baytrail: Fix PCI_DEV_PIRQ_ROUTE macro ending	Ben Gardner
2015-12-16	soc/samsung/exynos5250: Implement hard_reset()	Stefan Reinauer