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2018-03-23soc/intel/apollolake: Bypass FSP's deassertion of PERST# signal.Shamile Khan
BUG=b:76058338 BRANCH=None TEST=Build coreboot for Octopus board. Change-Id: I1858c7843d16b6b63fc30762a889916bbb9b781a Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/25311 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-22amd/stoneyridge: Add PM1 wake status to boot logMarshall Dawson
Print the wake status bits to the console. The format is kept similar to Intel's to maintain compatilibity with inspection utilities. Add relevant wake events from the register to the ELOG. Clear the register before continuing. TEST=Inspect console and ELOG for Grunt BUG=b:75020968 Change-Id: Idc9d12326abb290e4f7a5c60677eb6e057d475b2 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/25300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2018-03-22soc/intel/skylake: Define IFD_CHIPSETFurquan Shaikh
This change defines IFD_CHIPSET as sklkbl to allow ifdtool to set the right access control bits for SKL/KBL platforms. BUG=b:76098647 BRANCH=poppy TEST=Verified that the access control bits on KBL platforms are set correctly. Change-Id: I7b2131caa06d6a975e703262931ec0ea519a86aa Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25307 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-20soc/intel/apollolake: Add support for GSPIRavi Sarawadi
BUG=b:73133848 BRANCH=None TEST=Build coreboot for Octopus board. Tested the GSPI interface with a SPI EEPROM and got correct response to a RDID command Change-Id: Iec96f926ba7162074090617b7cf1c84e36b0fb37 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/24906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-19soc/intel/apollolake: Add PCIe de-emphasis enable configuration.Shamile Khan
PCIe de-emphasis is enabled by default. Thunderpeak Wi-Fi requires it to be disabled. Therefore allow it to be configured via a device tree setting. TEST=On GLKRVP, verify Thunderpeak Wi-Fi card shows up in lspci when de-emphasis is disabled in device tree. Change-Id: Iae204768dfe00a638c764644c44c7cda269e73e0 Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/25185 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-19soc/amd/stoneyridge/southbridge.c: Remove configure_stoneyridge_uartRichard Spiegel
The GPIO programming of configure_stoneyridge_UART() can be done by the early GPIO table, AOAC enabling was already removed. So configure_stoneyridge_uart() became redundant. Remove procedure configure_stoneyridge_uart(). BUG=b:74258015 TEST=Build and boot kahlee, observing serial output does not changes from previous serial output. Change-Id: Ie67051d7b90fa294090f6bfc518c6c074d98cc98 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25192 Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-17soc/amd/stoneyridge: Call sb_spibase() earlyGarrett Kirkendall
Call sb_spibase() early so that it will set up the SPI base address. This is another step to moving AGESA calls out of the bootblock. BUG=b:74427893 BRANCH=master TEST=Build and boot Grunt. Change-Id: I665d32f3acb0046eb6abbd363735561f0372f2a0 Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-03-17soc/intel/apollolake: handle different memory profiles for apl and glkAaron Durbin
glk has different memory profile values than apl. Therefore, a translation is required to correctly set the proper profile value depending on what SoC (and therefore FSP) is being used. Based on SOC_INTEL_GLK Kconfig value use different profiles. BUG=b:74932341 Change-Id: I6ea84d3339caf666aea5034ab8f0287bd1915e06 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25249 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-16soc/amd/stoneyridge: Create a HALT_THIS_AP calloutRichard Spiegel
It was required for all cores use the same CAR teardown function (exit_car.S and gcccar.inc). AGESA has already been modified to do the AP to do the call out. Create assembly code to call chipset_teardown_car and then enter an endless loop with halt instruction. Then create the call out that will call this new assembly code. BUG=b:70338633 AGESA COMMIT=3313d277 TEST=Created a debug version of AGESA that would print the returned status of HALT_THIS_AP. Build code without the fix, see the return. Build code with the fix, see that there's no return. Change-Id: I05ee405812211d93dfdbdc5ee7d9978c2eb585e1 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/24999 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-03-16soc/amd/stoneyridge/southbridge.c: Create AOAC initialization codeRichard Spiegel
Devices that need to have their AOAC register enabled do have a delay before they become available. Currently each device has their own wait loop. Create a procedure that initializes all AOAC devices in a table and wait for all AOAC to become alive, then call this new procedure before the call to initialize the UART. Then change all procedures that initialize some AOAC by moving the devices to the table and removing AOAC initialization code. BUG=b:74416098 TEST=Build and boot kahlee checking that UART is sending debug messages out. Change-Id: I359791c2a332629aa991f2f17a67e94726a21eb5 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25142 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-03-16soc/intel/apollolake: Add config option for enabling hotplugFurquan Shaikh
PcieRpHotPlug in apollolake UPD is default enabled. This change adds a config option to enable hotplug only if explicitly requested by mainboard. This changes the default behavior on all apollolake boards to have hotplug disabled. BUG=b:74633273 BRANCH=reef,coral Change-Id: I572c054d31aaf5d43a79c4b1773ec9356da48d9d Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-16soc/intel/apollolake and mainboards: Use pcie_rp_clkreq_pin arrayFurquan Shaikh
This change uses an array pcie_rp_clkreq_pin for accepting CLKREQ# from mainboards instead of defining a separate property for each root port. This allows us to use memcpy to copy the entire array into FSP params as well as new properties for PCIe root ports can be added as arrays in future CLs. BUG=b:74633273 BRANCH=reef,coral Change-Id: Ifa05f1e38fcfd95063ec327712e472cdbd12dbb7 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-15soc/amd/stoneyridge: Call sb_acpi_mmio_decode()Garrett Kirkendall
Call function sb_acpi_mmio_decode() from bootblock_fch_early_init(). This enables decoding of the FCH ACPI MMIO regions 0xfed80000 - 0xfed81fff. This is another step to moving AGESA out of the bootblock for StoneyRidge BUG=b:74586747 BRANCH=master TEST=Build and boot on Grunt. Change-Id: I8cf329e5cd2002b225742fefa5c1ddd2598de674 Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25161 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-15soc/intel/broadwell: add support for Intel GMA OpRegionMatt DeVillier
Add global/ACPI nvs variables required for IGD OpRegion. Add functions necessary to generate ACPI OpRegion, save the table address in ASLB, and restore table address upon S3 resume. Implementation largely based on existing Haswell/Lynxpoint code. Test: boot Windows 10 on google/lulu with Tianocore payload and GOP display init, observe display driver loaded and functional, display not black screen when resuming from S3 suspend. Change-Id: I024f4f0784df3cbbb9977692e9ef0ff9c3552725 Signed-off-by: CoolStar <coolstarorganization@gmail.com> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/25094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-03-14soc/intel/cannonlake: Disable RTC write protectCaveh Jalali
The cannonlake FSP enables PchLockDownRtcMemoryLock by default, but we need this memory to be writable. We normally over-ride this in the SoC chip init code, so we'll do the same on cannonlake. BUG=b:71722386 BRANCH=none TEST=Filled /dev/nvram with 0xff and 0x00 bytes to verify we can flip all the bits. Change-Id: I7cdd4abc2b3795d7dd82236fbe3c112428ee882b Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/25069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
2018-03-14soc/intel/cannonlake: Add SaGv value definitionLijian Zhao
SaGv(Sytem Agent Dynamic Frequency) have four settings, disabled, disabled but running at fixed lower frequency, disabled but running at fixed middle frquency, disabled but running at fixed high frequency and totally enabled. BUG=None. Change-Id: Ib5fb648179e7889aaa64d91e6cf7a7a7503f4225 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/25116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-14soc/amd/stoneyridge: Configure FCH for TPMGarrett Kirkendall
In preparation for moving AGESA calls out of the bootblock: * Add sb_tpm_decode to enable FCH decoding of TPM 1.2 regions and Legacy TPM IO 0x7f-0x7e and 0xef-0xee * Modify sb_tpm_decode_spi to additionally call sb_tpm_decode. BUG=b:65442212 BRANCH=master TEST=abuild, build Gardenia, build and boot Grunt (with other changes to call code not committed at this time) Change-Id: I0e2399e113c765393209dd11fd835fc758cf3029 Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-03-14soc/intel/baytrail: add support for Intel GMA OpRegionMatt DeVillier
Add global/ACPI nvs variables required for IGD OpRegion. Add functions necessary to generate ACPI OpRegion, save the table address in ASLB, and restore table address upon S3 resume. Implementation largely based on existing Broadwell code. Test: boot Windows 10 on google/squawks with Tianocore payload and GOP display init, observe display driver loaded and functional, display not black screen when resuming from S3 suspend. Change-Id: Iab15e1de2bb7d8fbec2e8705a621cfca0f255d4b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/25102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-03-09soc/intel/skylake: Move PCR DMI programming into bootblockSubrata Banik
As per PCH BWG 2.5.16, set up LPC IO Enables PCR[DMI] + 2774h bit [15:0] to the same value program in LPC PCI offset 82h. Also this cycle decoding is only allowed to set when SRLOCK is not set. Hence move the required programming from lpc.c to pch.c. Also only enable COM port ranges if CONFIG_DRIVERS_UART_8250IO Kconfig is selected. Change-Id: Ie706735492a450baa653d8a8bb74c6e42f5150b8 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-09soc/intel/common: Enable decoding of the COMB range to LPC based on KconfigSubrata Banik
By default all Intel platform has enable IO decode range for COMA if CONFIG_DRIVERS_UART_8250IO is selected. With this patch, COMB will get enable based on CONFIG_SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE Kconfig selection. Also make lpc_enable_fixed_io_ranges() function returns Enabled I/O bits to avoid an additional pci configuration read to get the same data. Change-Id: I884dbcc8a37cf8551001d0ca61910c986b903ebc Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/25045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2018-03-09soc/amd/stoneyridge: Add function to enable I2C host controllersGarrett Kirkendall
In preparation for moving AGESA calls out of bootblock: Add function to enable the four stoneyridge I2C engines. BUG=b:65442212 BRANCH=master TEST=abuild, build Gardenia, build and boot Grunt (with other changes to call code not committed at this time) Change-Id: Icb55c49cf56c65a9c2e1838cff1ed5afc04e1826 Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25026 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-09soc/amd/stoneyridge: Add ACPI MMIO enable functionGarrett Kirkendall
In preparation for moving AGESA calls out of bootblock: * Add definitions for needed registers in southbridge.h * Add function to enable AMD FCH ACPI MMIO regions 0xfed80000 to 0xfed81ffff. Will be called by a later commit. BUG=b:65442212 BRANCH=master TEST=abuild, build Gardenia, build boot Grunt (with other changes to call code not committed at this time) Change-Id: If26efa6c6f5b562ba898e7d9da4827833310dc26 Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25025 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-09soc/intel/denverton_ns: Update UART legacy mode to keep FSP tracesJulien Viard de Galbert
The FSP can only output its traces when the HSUART PCI device is available. - Move the hiding to after last FSP call. - Adapt coreboot PCI enumeration to keep the legacy configuration. With UART configured as legacy Linux will not re-enumerate it but detects it as legacy (ttyS0 instead of ttyS4). Change-Id: Id8801e178ffd8eeee78ece07da7bd6b8dbd88538 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/23623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-03-08soc/intel/common/block/gspi: set cs polarity before usingNick Vaccaro
Move call to __gspi_cs_change() in gspi_ctrlr_setup() to after initialization of cs polarity since it requires polarity to be set to work properly. Failure to do so confuses cr50. BUG=b:70628116 BRANCH=chromeos-2016.05 TEST='emerge-meowth coreboot' and verify on scope that chip select polarity is correct for the first transaction. Change-Id: I20b4f584663477d751a07889bccc865efbf9c469 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/25013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-08soc/intel/braswell: add resource allocation for LPE BAR1Matt DeVillier
coreboot's PCI resource allocator doesn't assign BAR1 for Braswell's LPE device because it doesn't exist, but is required by Windows drivers for the device to function. Manually add the required resource via the existing lpe_read_resources function, and marked it as IORESOURCE_STORED so pci_dev_set_resources ignores it. TEST: boot Windows 10 on google/edgar, observe that memory resources are properly assigned to LPE driver for BAR1 and no error reported. Change-Id: Iaa68319da5fb999fe8d73792eaee692cce60c8a2 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-03-08soc/intel/braswell: add ACPI for eMMC/SD devices in PCI modeMatt DeVillier
Allows eMMC in PCI mode to be seen/used by Windows. Test: boot Windows installer on google/edgar, observe internal eMMC storage available for installation when eMMC in PCI (vs ACPI) mode. Change-Id: I4272c198e5e675f451a1f4de5d46e3cd96371446 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/24988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-07soc/amd/stoneyridge/Kconfig: Create a power restore optionRichard Spiegel
File soc/amd/stoneyridge/sm.c has a CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL that's not used at all and has no control. It's also not used in the build process. Remove the define from sm.c, create a true Kconfig definition and use it to define if power should be restored after a power failure/recovery. BUG=b:72873003 TEST=Build kahlee. Use serial output to check what is being programmed to RTC shadow. Build with and without selecting the Kconfig parameter. Then remove serial output and leave the parameter unselected (always S5 at power recovery). Change-Id: Iec82cb68cf1e2a820e610f12d8620488662232aa Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-03-07soc/intel/braswell: add LPEA resources to southcluster.aslMatt DeVillier
The LPEA device memory resources, required by Windows drivers, were not being set. Allocate required resources per Inte'sl CHT Tianocore reference code. Test: boot Windows on google/edgar, observe LPEA device working properly. Change-Id: Ic3ecfc2ddade7d76dbaa95ffdd82599c3bcf35da Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/24987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-03-07soc/amd/stoneyridge: clean up southbridge.cGarrett Kirkendall
* Limit dependency on vendorcode header files and use defines from iomap.h and southbridge.h * Factor out to functions, device power-on code for AMBA and UART. BUG=b:69220826 BRANCH=master TEST=abuild, build Gardenia, build and boot Grunt Change-Id: Ibcf4d617e2a0a520a6d7e8d0d758d7a9705a84ea Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-03-07soc/amd/stoneyridge: clean up OSCOUT1_ClkOutputEnbGarrett Kirkendall
Change OSCOUT1_ClkOutputEnb programming to use registers from iomap.h and southbridge.h BUG=b:69220826 BRANCH=master TEST=abuild, build Gardenia, build and boot Grunt Change-Id: Ib138dae6057394740c415e882e4dbd925882c2de Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-03-07soc/amd/stoneyridge: Add southbridge definitionsGarrett Kirkendall
* Add definitions to iomap.h for AMD ACPI MMIO base addresses. * Add FCH AOAC registers for enabling FCH devices. * From: BIOS and Kernel Developer's Guide (BKDG) for AMD Family 15h, Models 70h-7Fh Processors Rev 3.04 BUG=b:69220826 BRANCH=master TEST=abuild, build Gardenia, build and boot Grunt Change-Id: I45c1d1d7edc864000282c7ca4e2b8f2a14ea9eac Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/24998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-03-06soc/intel/braswell: increase LPEA fw allocation to 2MiBMatt DeVillier
Increase memory allocated for the LPEA firmware from 1MiB to 2MiB to match Intel CHT reference code and fix Windows functionality. Test: boot Windows on google/edgar, observe no error in Device Manager for LPEA audio device due to BAR2 resource allocation. Change-Id: I7cffcdd83a66a922c2454488c8650df03c9f5097 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/24986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-06soc/intel/braswell: fix PCI resource PMAX/PLEN valuesMatt DeVillier
Without PMAX correctly set, the calculation for PLEN is incorrect, leading to a Windows BSOD on boot. Correct PMAX using code from Baytrail SoC, setting PMAX to (CONFIG_MMCONF_BASE_ADDRESS - 1). Test: Boot Windows 10 on google/edgar without BSOD. Change-Id: I4f2f4a0ff3a285826709f9eaafa40b0bf0cafb83 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/24985 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-06soc/intel/skylake: Remove MCFG constantsDuncan Laurie
The MMCONF base address and length are set in Kconfig so it does not need to be redefined by the SOC as the code can just use the Kconfig variable directly. Tested on a fizz board to ensure MCFG is still created properly. Change-Id: I5fd472b1afc8264823a2b9db0f296fbfb6b1ecc0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/24975 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-06soc/intel: Fix MCFG end bus numberDuncan Laurie
The ACPI MCFG table is generated with a static end bus number of 255, which expects that the reserved range in E820 is 256MB. However the actual MCFG range is configurable with Kconfig, so these two values may not match when the OS tries to determine the range: PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000) PCI: MMCONFIG 0000 [bus 00-3f] at [mem 0xe0000000-0xe3ffffff] (base 0xe0000000) (size reduced!) acpi PNP0A08:00: [Firmware Info]: MMCONFIG for domain 0000 [bus 00-3f] only partially covers this bridge Instead of forcing the end bus number to be 255 use the Kconfig value to set it based on the current configuration. Tested on a fizz device to ensure that the kernel no longer complains: PCI: MMCONFIG for domain 0000 [bus 00-3f] at [mem 0xe0000000-0xe3ffffff] (base 0xe0000000) Change-Id: I999ea9b72b9deba5f27dd692faa0408427a0bf89 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/24974 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-06soc/amd/stoneyridge: Add ST/CZ SMBus device idMartin Roth
The SMBus PCI device ID for Stoney wasn't updated when the code was pulled over from hudson. This means that the IOAPIC wasn't being initialized in coreboot. BUG=b:74070580 TEST=Boot Grunt, see IOAPIC init messages in console. Change-Id: Ida5d3f3592488694681300d79444c1e26fff6a1a Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/24930 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-05soc/intel/common/block/smm: Add configurable delay before entering S5Furquan Shaikh
This change adds a configurable delay in milliseconds before SLP_EN is set in SLP_SMI for S5. Reason for doing this is to avoid race between SLP and power button SMIs. On some platforms (Nami, Nautilus), it was observed that power button SMI triggered by EC was competing with the SLP SMI triggered by keyboard driver. Keyboard driver indicated power button press which resulted in depthcharge triggering SLP_SMI, causing the AP to enter S5. However, the power button press also causes the EC to send a pulse on PWRBTN# line, which is debounced for 16ms before an interrupt is triggered. This interrupt was generated after SLP_SMI is processed which resulted in the device waking back up from S5. This change adds a config option SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS which is used to add a delay before SLP_EN is set for S5. This change should only affect CHROMEOS boards as the config option will be 0 in other cases. BUG=b:74083107 TEST=Verified that nami, nautilus do not wake back from S5 on power button press at dev mode screen. Change-Id: Iaee19b5aba0aad7eb34bd126fda5b0f6ef394ed7 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/24964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-01soc/intel/broadwell: Generate ACPI DMAR tableMatt DeVillier
If the SoC is VT-d capable, write an ACPI DMAR table. The entry for the GFXVTBAR is only generated if the IGD is enabled. Change-Id: Id7c899954f1bae9d2b48532ca5ee271944f0c5f6 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/23821 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Youness Alaoui <snifikino@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-03-01soc/intel/broadwell: Enable VT-d and X2APICMatt DeVillier
We use the usual static addresses 0xfed90000/0xfed91000 for the GFX IOMMU and the general IOMMU respectively. These addresses have to be configured in MCHBAR registers and reserved from the OS. Change-Id: I7afcce0da028a160174db2cf6b4b6735bcd59165 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/23820 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Youness Alaoui <snifikino@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-03-01soc/amd/stoneyridge: Remove printk for GPIOJustin TerAvest
The printk() calls in sb_program_gpios() aren't necessary, and incur a 13 second delay if the function is called from bootblock_mainboard_early_init(). This commit removes them so GPIOs can be set up earlier. TEST=call sb_program_gpios from bootblock_mainboard_early_init BUG=b:73898539 Change-Id: I064291decf47d86132e36469e029b3262ec20172 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/24915 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-28skylake: Fix unwanted disablement of ACPI UPWEKane Chen
In PORTSC, Port Enabled/Disabled(PED) is RW1CS. When there is a USB device attached on system, current UPWE method will set 1 to PED, this will cause port disabled as it's RW1CS. This change is inspired by xhci_port_state_to_neutral in linux driver. It will mask all RO and RWS bits and set WDE and WCE. BUG=b:70777816 TEST=System won't be awakend from s3 automatically when usb devices is attached. Also system can be awakend by hotplugging usb devices under S3. Change-Id: Ifd4c2d6640fea538e0ac71d7c5e73ab529e94f42 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/23848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-28soc/intel/skylake: Add support to print ME versionFurquan Shaikh
This change adds a boot state callback to print ME version after DEV_ENABLE is complete. Information is printed only if UART_DEBUG is enabled because talking to ME to get the firmware version adds ~1 second to boot time. TEST=Verified on Soraka that ME version printed is correct. Change-Id: I360d5d7420950d5aa255df08be6d7123621b87a8 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/23857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-26soc/amd/stoneyridge: Refactor northbridge resource allocatorMarc Jones
The resource allocator was overly complicated due to porting from a multi-node resource allocator. It had some assumptions about the UMA memory and where it would be located. The refactored allocations account for UMA being reserved above 4GiB. TEST=Check CBMEM table has correct RAM regions. Change-Id: I722ded9fb877ec756c3af11fcb5fea587ac0ba8e Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/23819 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-26soc/amd/common: Save the UMA settings from AGESAMarc Jones
Save the UMA base and size settings returned by AGESA in amdinitpost(); Change-Id: Id96cc65582118ad41d397b1a600cab1615676a55 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/23818 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-26soc/amd/common/block/pi/amd_late_init.c: Fix part numberRichard Spiegel
Kahlee DIMM have invalid string when it comes to part number (bytes 0x149-0x15c). We currently force a NA string, but grunt has the proper strings. Just let the string go through, and a second commit within smbios.c will be responsible for testing the string and taking proper action. BUG=b:73122207 TEST=Build, boot and record serial output for kahlee while injecting different strings to dmi17->PartNumber. Remove string injection before committing. Change-Id: I427262873f9ec80f459245e5f509e28a68de3074 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/23825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-22soc/amd/stoneyridge: Add readable macros for GPIOJustin TerAvest
This commit defines a set of macros for defining GPIO configuration that are easier to read than the raw iomux function values used today. TEST=None BUG=b:72875858 Change-Id: Ie100c8494c565afa28fa44d78ff73155fc8c7ea8 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23828 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-22soc/intel/cannonlake: Clear EMMC timeout registerLijian Zhao
Clear EMMC timeout register to avoid EMMC issue according to cannonlake bios writer guide. BUG=b.71586766 TEST=Install OS into EMMC successfully on meowth P1 platform. Change-Id: I39e927a2c312c94561213f9f7c3319dcafa426b9 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/23831 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-02-22soc/intel/cannonlake: Add emmc/sdc port idLijian Zhao
EMMC and SD Controller port id listed here, the port id definition came from Cannonlake BIOS Writer Guide 570374. BUG=None TEST=None Change-Id: I901e90c47b08bb013fcfee5def610e320a7ac19a Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/23789 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-02-22soc/intel/cannonlake: Add more HDA Audio Link settingsLijian Zhao
Since FSP version 7.x.11.43, more HDA Audio link options are exposed, so included that into coreboot. Users can modify that base on platform implementations. BUG=None TEST=Boot up with debug build version FSP and check the debug print result on meowth platform. Change-Id: Ib2a75f554ddf9919a62c78a162ec1b9e602f1f5d Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/23400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-02-22soc/intel/cannonlake: Add provision to make CSME function disable in SMM modeSubrata Banik
TEST=lspci from Chrome OS shows CSME device is not visible over PCI tree. Change-Id: I3e0a5b00758a4ce42f2f190748c293c5ce07390c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23824 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-02 03:50:53 +0000