summaryrefslogtreecommitdiff
path: root/src/soc
AgeCommit message (Collapse)Author
2019-11-11fsp{rangeley,baytrail,broadwell_de}: Fix dead assignmentElyes HAOUAS
Change-Id: I0f02a4508b78cdb0706df6f288138a9db54e229e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36703 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-11rockchip/rk3288: Bump verstage size a little moreJulius Werner
RK3288 is running out of space again. I believe reducing the CBFS cache size this much should be safe. I don't really care to test it either though. We should probably just deprecate that SoC at some point, it's just causing too much pain. Change-Id: Id8f971606a7a183d3e9af8bbb1b353e518ec24c8 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Joel Kitching <kitching@google.com>
2019-11-11soc/intel/icelake: add soc implementation for ETR address APIMichael Niewöhner
Add soc implementation for the new ETR address API. Change-Id: I8383a60c2c4988948ab8b3e9a54330269d217868 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36568 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-11soc/intel/cannonlake: add soc implementation for ETR address APIMichael Niewöhner
Add soc implementation for the new ETR address API. Change-Id: Ifc128099185a2c40ec3e7c5f84fcc42227c93f28 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36567 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-11soc/intel/apollolake: add soc implementation for ETR address APIMichael Niewöhner
Add soc implementation for the new ETR address API. Change-Id: I1832f5f14055fc3dbb502289035130ca7a5d6d33 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-11soc/intel/common: pmclib: add API to get ETR register addressMichael Niewöhner
Add a new API to get the ETR register address. Change-Id: I706f3e220d639a6133625e3cb7267f7009006af2 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36565 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-10soc/intel/broadwell: Use common sb code for SPI lockdown configurationArthur Heymans
Change-Id: I5a8239f4e9e1f9728074ff5452c95d3138965d82 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-10soc/intel/broadwell: Don't reinitialize SPI after lockdownArthur Heymans
With the common southbridge SPI code reinitialization after lockdown is not necessary, hence the SMM finalize call becomes a no-op. Change-Id: I4d7c6ba91dc9f0e0ce4e3228fdf859d5f3d5abf4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36004 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-10soc/intel/broadwell: Use common INTEL_SB SPI codeArthur Heymans
Change-Id: Id906733ac3719c8d6835aad52ca87beb81b5771d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-10soc/intel/broadwell: Use common SB RTC codeArthur Heymans
Change-Id: Iedb9a8962ac1b4107e9192b0be610fb92d2cfdc6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-10sb/intel/common: Remove the SOUTHBRIDGE_INTEL_COMMON Kconfig symbolArthur Heymans
All code in southbridge/intel/common is now properly guarded by a Kconfig symbol, making SOUTHBRIDGE_INTEL_COMMON obsolete. Change-Id: Ifeccfaa9534f903e3f3543e1f9f3d5f3345b461e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36438 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-10sb/intel/common: Make linking rtc.c conditionalArthur Heymans
Change-Id: I7321da453c0d9bb4a142c3c93103d8dc0ff416b7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-10soc/intel/common/ebda: Drop codeArthur Heymans
There is no need to use EBDA to pass cbmem_top from romstage to later stages. Change-Id: I46e2459ff3c785f530cabc5930004ef920ffc89a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-10soc/intel/common/sa: Remove EBDA dependencyArthur Heymans
Saving cbmem_top across stages is not needed anymore so EBDA should not be used. The guard to cbmem_top_chipset implementation was inappropriate. Change-Id: Ibbb3534b88de4f7b6fc39675a77461265605e56e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2019-11-09arch/x86: Replace some __SMM__ guardsKyösti Mälkki
We generally do not guard source in attempts to reduce the final object sizes, but rely on garbage collection. Most of the __unused attributes inserted here will be removed when remaining __SIMPLE_DEVICE__ guards can be removed. Change-Id: I2440931fab4f41d7e8249c082e6c9b5a9cd0ef13 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36641 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-09ELOG: Avoid some preprocessor useKyösti Mälkki
Change-Id: I8daf8868af2e8c2b07b0dda0eeaf863f2f550c59 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36648 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-09ELOG: Introduce elog_gsmi variantsKyösti Mälkki
This avoids a lot of if (CONFIG(ELOG_GSMI)) boilerplate. Change-Id: I87d25c820daedeb33b3b474a6632a89ea80b0867 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36647 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-09soc/intel/tigerlake/acpi: Copy acpi directory from icelakeSubrata Banik
Clone entirely from Icelake List of changes on top off initial icelake clone 1. Removed Descriptor Name for Memory mapped SPI flash and local APIC in northbridge.asl 2. Rearranged code in gpio.asl to move RBUF object under _CRS and made the file use ASL2.0 syntax. 3. Make use of absolute path for scs.asl 4. Remove unused smbus.asl 5. Rearranged code in nothbridge.asl to move MCRS object under _CRS, use absolute variable path and added TODO for further clean up. 6. Refer absolute variable path in scs.asl Change-Id: If967cb5904f543ce21eb6e89421df0e5673d2238 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-11-09soc/intel/tigerlake: Do initial SoC commit till ramstageSubrata Banik
Clone entirely from Icelake List of changes on top off initial icelake clone 1. Replace "Icelake" with "Tigerlake" 2. Replace "icl" with "tgl" 3. Replace "icp" with "tgp" 4. Rename structure based on Icelake with Tigerlake 5. Remove and clean below files 5.a Clean up upd override in fsp_params.c, will be added once FSP available. 5.b Remove __weak functions from fsp_params.c 5.c Remove dGPU over PCIE enable Kconfig option 6. Add CPU/PCH/SA EDS document number and chapter number 7. Remove unnecessary headers from .c files based on review Tiger Lake specific changes will follow in subsequent patches. 1. Include GPIO controller delta over ICL 2. FSP-S related UPD overrides as applicable Change-Id: Id95e2fa9b7a7c6b3b9233d2c438b25a6c4904bbb Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36087 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-09soc/intel/tigerlake/romstage: Do initial SoC commit till romstageSubrata Banik
Clone entirely from Icelake List of changes on top off initial icelake clone 1. Replace "Icelake" with "Tigerlake" 2. Replace "icl" with "tgl" 3. Replace "icp" with "tgp" 4. Rename structure based on Icelake with Tigerlake 5. Remove and clean below files 5.a Clean up upd override in fsp_params.c, will be added once FSP available. 5.b Remove __weak functions from fsp_params.c 6. Add CPU/PCH/SA EDS document number and chapter number 7. Add required headers into include/soc/ from ICL directory Change-Id: I24980c196efb2c5569996ca4fb315c256cf9de87 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36552 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-09soc/intel/tigerlake/bootblock: Do initial SoC commit till bootblockSubrata Banik
Clone entirely from Icelake List of changes on top off initial icelake clone 1. Replace "Icelake" with "Tigerlake" 2. Replace "icl" with "tgl" 3. Replace "icp" with "tgp" 4. Rename structure based on Icelake with Tigerlake 5. Add CPU/PCH/SA EDS document number and chapter number 6. Add required headers into include/soc/ from ICL directory Tiger Lake specific changes will follow in subsequent patches. 1. Add Tigerlake specific device IDs (CPU/PCH/SA) Change-Id: Id7a05f4b183028550d805f02a8078ab69862a62e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2019-11-08ELOG, soc/intel: Avoid some preprocessor useKyösti Mälkki
Change-Id: I5378573f37daa4f09db332023027deda677c7aeb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36646 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-08sb,soc/intel: Reduce preprocessor use with ME debuggingKyösti Mälkki
Change-Id: Iedd54730f140b6a7a40834f00d558ed99a345077 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-08arch/x86: Drop some __SMM__ guardsKyösti Mälkki
Change-Id: I64063bbae5b44f1f24566609a7f770c6d5f69fac Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36637 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-08intel/braswell: Remove duplicate set_max_freq() prototypesKyösti Mälkki
Change-Id: I13ec9f477c64831848fb0e80b97bfbc10896c195 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-11-07soc/intel/{apl,dnv,quark}: Use strip_quotes for FSP optionsMario Scheithauer
The commit 8fc523e3 (drivers/intel/fsp2_0: Use strip_quotes for cbfs filenames) breaks the Siemens APL mainboards as FSP-M never returns once it is called. The reason for this is that the -b option is missing when adding the FSP package to cbfs via cbfstool. This patch fixes this issue. TEST=tested on siemens/mc_apl5 Change-Id: I48e5fa36e1ad799d09714f53a3041f73b8ec3550 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36645 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: David Guckian Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-07soc/intel/icelake: Refactor pch_early_init() codeSubrata Banik
This patch keeps required pch_early_init() function like ABASE programming, GPE and RTC init into bootblock and moves remaining functions like TCO configuration and SMBUS init into romstage/pch.c in order to maintain only required chipset programming for bootblock and verstage. TEST=Able to build and boot ICL DE system. Change-Id: I4f0914242c3215f6bf76e41c468f544361a740d8 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36627 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-06soc/intel/common: Make native and FSP-T CAR init mutually exclusiveArthur Heymans
postcar stage does not consume cpulib.c, so don't include it there. Change-Id: Ie723412dcf09151cdbb41e357ad9c2e4f393cb47 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36168 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-06soc/intel/icelake: Set FSP_TEMP_RAM_STACK unconditionallySubrata Banik
Icelake default selects PLATFORM_USES_FSP2_1 which means stack will be shared between FSP and coreboot (CONFIG_FSP_USES_CB_STACK) hence no need to have any other guard to assign FSP_TEMP_RAM_SIZE. Change-Id: Idbe393f7a63ad10f1ad3c9e7248593cf8eb115d9 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36628 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-05soc/intel/common: Include Tigerlake device IDsRavi Sarawadi
Add Tigerlake specific CPU, System Agent, PCH, IGD device IDs. BUG=None BRANCH=None TEST=Build 'emerge-tglrvp coreboot' Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: I19047354718bdf510dffee4659d885f1313a751b Reviewed-on: https://review.coreboot.org/c/coreboot/+/36225 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-11-05drivers/intel/fsp2_0: Use strip_quotes for cbfs filenamesWim Vervoorn
The quotes were not stripped for the cbfs filenames of the FSP components. This is causing problems when the regions-for-file macro is executed (when VBOOT is enabled and the files should be filtered). BUG=N/A TEST=build Change-Id: I14267502cfab5308d3874a0c0fd18a71b08bb9f8 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36548 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-05soc/intel/fsp_broadwell_de: Add CONFIG_IED_SIZE, drop CONFIG_SMM_TSEG_SIZEAndrey Petrov
Fix regression introduced in recent SMM region handling overhaul. Previously IED region size was hardcoded in the code. However when chip code was modified to use smm_region() and friends, IED_SIZE define was not added and build system quetly substituted it with 0. Also, drop CONFIG_SMM_TSEG_SIZE which is now obsolete. TEST=tested on watson platform; without the patch tg3 NIC driver doesn't work properly and that gets solved with this patch Change-Id: Id6fb258e555bb507851886b0e75f1f53c3762276 Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36417 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-05soc/intel/common: Don't link CAR teardown in romstageArthur Heymans
This is done in postcar stage. This also assumes CAR tear down will always be done in postcar stage. Change-Id: I0ff1624c20b9649ca0a8fa31c342bf99530076d7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-04soc/intel/sgx: convert SGX and PRMRR devicetree options to KconfigMichael Niewöhner
The devicetree is not made for user-choosable options, thus introduce Kconfig options for both SGX and the corresponding PRMRR size. The PRMRR size Kconfig has been implemented as a maximum value. At runtime the final PRMRR size gets selected by checking the supported values in MSR_PRMRR_VALID_CONFIG and trying to select the value nearest to the chosen one. When "Maximum" is chosen, the highest possibly value from the MSR gets used. When a too strict limit is set, coreboot will die, printing an error message. Tested successfully on X11SSM-F Change-Id: I5f08e85898304bba6680075ca5d6bce26aef9a4d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-04soc/intel: skl,cnl,icl: consolidate ebda and memmapMichael Niewöhner
As of CB:36136 ebda and memmap are identical for skl, cnl and icl, thus move them to common code. Tested successfully on X11SSM-F Change-Id: I9a20c814d2a6874fcb4ff99ef1a7825d891f74e2 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36137 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-04soc/intel: skl,cnl,icl: rely on TOLUM as cbmem_top returned by FSPMichael Niewöhner
Instead of doing our own calculations, rely on TOLUM returned by FSP for cbmem_top. This (hopefully) saves us from making mistakes in weird calculations of offsets and alignments. Further this makes it easier to implement e.g. SGX PRMRR size selection via Kconfig as we do not have to make any assumptions about alignments but can simply pass (valid) values to FSP. Tested successfully on X11SSM-F Change-Id: If66a00d1320917bc68afb32c19db0e24c6732812 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36136 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-04sb/intel: Use defined CONFIG_HPET_ADDRESSElyes HAOUAS
Change-Id: I15ae5e70ba351e89d5ea9d04dbb1efdfbb372bba Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36458 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-04soc/intel: Remove unused codePatrick Rudolph
Delete acpi_create_intel_hpet() which has been replaced by acpi_write_hpet() in the corresponding soc folders some time ago. Change-Id: I788c9ef27cdc575eb8467cbef64ee52f4053e197 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Guckian Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-04soc/intel/broadwell: Use sb/intel/common/acpi/platform.aslArthur Heymans
Change-Id: I6d8d04289254317af8d7cc55c89431d408414384 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-04soc/intel/{braswell,baytrail}: Use sb/common/intel/platform.aslArthur Heymans
Change-Id: I64a27cb080838c986a12a40c80d0c91824b9d04c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36581 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-04arch/mips: Pass cbmem_top to ramstage via calling argumentArthur Heymans
This allows to use a common cbmem_top implementation. Change-Id: I85efe3899607854c36d0ec594868f690eb724a7f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36421 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-04soc/nvidia/tegra210: Populate _cbmem_top_ptrArthur Heymans
On this platform the ramstage is run on a different core so passing cbmem_top via calling arguments is not an option. To work around this populate _cbmem_top_ptr with cbmem_top_chipset which is also used in romstage. Change-Id: I8799c12705e944162c05fb7225ae21d32a2a882b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36557 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-04soc/intel/icelake: Make use of "all-y"Subrata Banik
This patch makes use of "all-y" in order to replace all common stage (bootblock, verstage, romstage, postcar, ramstage) files inclusion in Makefile.inc Change-Id: I11001d0d381ec9c1df41bc331da845f51e666a44 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36546 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-04soc/intel/icelake: Add alignment check for TSEG base and sizeSubrata Banik
This patch ensures to not set SMRR if TSEG base is not align with TSEG size Change-Id: I77d1cb2fd287f45859cde37a564ea7c147d5633f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36542 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-04soc/intel/icelake: Set DCACHE_BSP_STACK_SIZE default ~129KiB unconditionallySubrata Banik
Icelake default selects PLATFORM_USES_FSP2_1 which means stack will be shared between FSP and coreboot (CONFIG_FSP_USES_CB_STACK) hence no need to have any other default value than 129KiB (128KiB for FSP and 1KiB for coreboot) Change-Id: I856f7e48a4a1e86eb082b9e772e0776664edca51 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36538 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-04soc/intel/icelake: Remove unused headersSubrata Banik
This patch removes inclusion of unused headers from soc/intel/icelake Change-Id: Icb653dee7992538aadf98d84adadd081f816fd01 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36536 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-04soc/intel/icelake: Skip BIOS OpRom execution based on CONFIG_RUN_FSP_GOPSubrata Banik
This patch replaces BIOS OpRpm execution checks from CONFIG_INTEL_GMA_ADD_VBT to CONFIG_RUN_FSP_GOP as adding VBT files doesn't mean GFX PEIM is going to execute to initialize IGD. Change-Id: Ic76529ba11f621f644d4472be6cbbc34682f00bf Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36532 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-04soc/intel/icelake: Clean up report_cpu_info() functionSubrata Banik
This patch makes below clean up for report_cpu_info() function 1. Replace cpu_string with cpu_not_found 2. Assign default string "Platform info not available" to cpu_not_found string 3. Add array out of bound check while skiping leading white space in cpu brand string name Change-Id: I41c76eb93f0c5229c4a49aa041339b8ad51ad34a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36531 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-03arch/arm64: Pass cbmem_top to ramstage via calling argumentArthur Heymans
This solution is very generic and can in principle be implemented on all arch/soc. Currently the old infrastructure to pass on information from romstage to ramstage is left in place and will be removed in a follow-up commit. Nvidia Tegra will be handled in a separate patch because it has a custom ramstage entry. Instead trying to figure out which files can be removed from stages and which cbmem_top implementations need with preprocessor, rename all cbmem_top implementation to cbmem_top_romstage. Mechanisms set in place to pass on information from rom- to ram-stage will be replaced in a followup commit. Change-Id: I86cdc5c2fac76797732a3a3398f50c4d1ff6647a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-11-03arch/arm: Pass cbmem_top to ramstage via calling argumentArthur Heymans
This solution is very generic and can in principle be implemented on all arch/soc. Instead trying to figure out which files can be removed from stages and which cbmem_top implementations need with preprocessor, rename all cbmem_top implementation to cbmem_top_romstage. Mechanisms set in place to pass on information from rom- to ram-stage will be placed in a followup commit. Change-Id: If31f0f1de17ffc92c9397f32b26db25aff4b7cab Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36145 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-26 00:54:52 +0000