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2017-09-06soc/intel/skylake: Add config for enabling PCIe AERRizwan Qureshi
Add a config for enabling/disabling Advanced Error Reporting feature for PCIe root ports. BUG=b:64798078 TEST="lspci" shows that AER is enabled in the capabilities list. Change-Id: Ieb74c3566ded2276e549c98f78813c4f5d4d310a Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/21401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-06soc/amd/stoneyridge: Use __packedJonathan Neuschäfer
__packed has been introduced in commit 6a00113de8 ("Rename __attribute__((packed)) --> __packed"). Use it. Change-Id: Ie654567ebff884b911de10bd9fef605436e72af8 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21346 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-06soc/intel/{cannonlake,skylake}: Fix null pointer dereference in klocworkSubrata Banik
This patch fixes klocwork bug due to recent memmap.c implementation where “Pointer 'dev' returned from call to function 'dev_find_slot' at line 144 may be NULL.” Change-Id: I4c74ca410d1a0ba48634ec9928a0d9d1cc20e27a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-05intel/skylake: nhlt: Add capture configuration format for IV feedback from ↵Harsha Priya
max98927 This changelist adds the capture format to be set for max98927. The nhlt blob is the same but the format params for capture are different from the render. BUG=b:36724448 TEST=IV feedback data is of good quality Change-Id: I135cf4479e89cd2046ff46027f94c0f71aed650e Signed-off-by: Harsha Priya <harshapriya.n@intel.com> Reviewed-on: https://review.coreboot.org/21340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-05nvidia/tegra*: Use xcompile for compiler prefix unless specifiedPatrick Georgi
GCC_PREFIX is uncommon in the coreboot tree. If not provided, take data from .xcompile to fill in the blanks. Change-Id: I711a73be9d35d896198664f0ae213218653f275e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/21391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-05soc/intel/denverton_ns: Add support for Intel Atom C3000 SoCMariusz Szafranski
This change adds support for Intel Atom C3000 SoC ("Denverton" and "Denverton-NS"). Code is partially based on Apollo Lake/Skylake code. Change-Id: I53d69aede3b92f1fe06b74a96cc40187fb9825f1 Signed-off-by: Mariusz Szafranski <mariuszx.szafranski@intel.com> Reviewed-on: https://review.coreboot.org/20861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
2017-09-05soc/intel/cannonlake: Set IGD stolen memory size to 64MBSubrata Banik
This patch overrides default FSP IGD stolen memory size UPD value. TEST=Ensures FSP-M UPD “IgdDvmt50PreAlloc” value is 0x2 (64MB) Change-Id: I63d992e139810ad203137b34c98d1a463f88b92d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-05soc/intel/common/block/gpio: Fix PAD_DW1_MASKHannah Williams
for case CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL=y https://ticket.coreboot.org/issues/128 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Change-Id: I2b0b9c07ebc99f4b4d7e8c5a72483bedd33e2e07 Reviewed-on: https://review.coreboot.org/21282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Youness Alaoui <snifikino@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-04Kconfig: Move and rename ADD_VBT_DATA_FILEPatrick Rudolph
Move ADD_VBT_DATA_FILE to "Devices" menu and rename it to INTEL_GMA_ADD_VBT_DATA_FILE. Depend on Intel platforms to avoid confusing users of non-Intel platforms. The Intel GMA driver will use the vbt.bin, if present, to fill the ACPI OpRegion. Change-Id: I688bac339c32e9c856642a0f4bd5929beef06409 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-02soc/intel/cannonlake: Use common mca_configure() APIPratik Prajapati
Use mca_configure() API from cpulib to configure Intel Machine Check Architecture (MCA) Change-Id: Ib4943a7f7929775bd5e9945462e530ef68a398b8 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21241 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-02soc/intel/skylake: Use common mca_configure() APIPratik Prajapati
Use mca_configure() API from cpulib to configure Intel Machine Check Architecture (MCA) Change-Id: Ia96cb82fff3def46dbecb09dee94de86f179abe6 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-02intel/common/cpulib: Add API to configure MCAPratik Prajapati
Add mca_configure() API to configure Intel Machine Check Architecture (MCA). Change-Id: I5e88c7527ce350824e48892caa978b2b78f1de20 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21239 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-01soc/intel/cannonlake: Define Max PCIE Root PortsPratik Prajapati
This patch defines Max PCIE Root Ports and fixes bellow Coverity scan defect, *** CID 1380036: Control flow issues (NO_EFFECT) /src/soc/intel/cannonlake/romstage/romstage.c: 80 in soc_memory_init_params() 79 >>> CID 1380036: Control flow issues (NO_EFFECT) >>> "i" is converted to an unsigned type because it's compared to an unsigned constant. 80 for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { 81 if (config->PcieRpEnable[i]) 82 mask |= (1 << i); Change-Id: Id45ff6e96043ed71117018a4e73d08920ae9667e Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-01soc/intel/cannonlake: add *spi.c files to makeNick Vaccaro
Adds spi.c and gspi.c to verstage. Change-Id: I363d9aafa989c5a7a0b36ad9edf1c70a75604d28 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/21284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-01soc/intel/cannonlake: add gpio files to makeNick Vaccaro
Adds gpio.c to romstage and ramstage. Adds select GENERIC_GPIO_LIB to CPU_SPECIFIC_OPTIONS. Change-Id: I4931f6c6f089cc54ea168cf4a80d268d983a61de Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/21283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-01soc/intel/canonlake: Enable LPSS UART in 32bit PCI modeLijian Zhao
Cannonlake LPSS UART port can be working on both 32 bit and 8 bit mode. To maintian compatibilty with previous generation of SOC, select 32 bit mode as default. Change-Id: Iaef8bceabc1b12e054ab4a364f98b568a9efcd85 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-01soc/intel/cannonlake: Perform dram top calculation based on HW registersSubrata Banik
This patch ensures that entire system memory calculation is done based on host bridge registers. BRANCH=none BUG=b:63974384 TEST=Build and boot cannonlake RVP successfully with below configurations 1. Booting to OS with no UPD change 2. Enable ProbelessTrace UPD and boot to OS. 3. Enable PRMRR with size 1MB and boot to OS. 4. Enable PRMRR with size 32MB and boot to OS. 5. Enable PRMRR with size 2MB and unable to boot to OS due to unsupported PRMRR size. 6. Enable C6 DRAM with PRMRR size 0MB and boot to OS. Change-Id: I0a430a24f52cdf6e2517a49910b77ab08a199ca2 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-01soc/intel/apollolake: Use SMM library to get tseg region informationSubrata Banik
This patch uses smm common library function to get tseg base address and size. Hence removing definitions of smm_region() from soc directory. BRANCH=none BUG=b:63974384 TEST=Build and boot reef successfully. Change-Id: I091ca90cf576c0da35cf3fe010f8c22a18ef82d9 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-01soc/intel/skylake: Use SA library to get smm region informationSubrata Banik
This patch uses system agent common library to know tseg region start and size. Unable to remove smm_region() function from soc code as SMM common library is not yet available for skylake use. BRANCH=none BUG=b:63974384 TEST=Build and boot eve successfully. Change-Id: If98b65805753db2c30d6fea29e401a17cef39799 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21290 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-30soc/intel/{cannonlake,skylake}: Add active default value for UART_FOR_CONSOLESubrata Banik
This patch to avoid build bot hang issue due to no active default value for UART_FOR_CONSOLE kconfig option. Change-Id: I70ca5dc6c4bde6a119ad59d8c58955c96c042198 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21287 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-30soc/intel/common: Add functions into common SMM librarySubrata Banik
This patch to add helper function to get SMM region start and size based on systemagent common library. BRANCH=none BUG=b:63974384 TEST=Build and boot eve successfully. Change-Id: If10af4a3f6a5bd22db5a03bcd3033a01b1cce0b4 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-30soc/intel/common: Add functions into common system agent librarySubrata Banik
This patch to add helper function to get tseg memory base and size for HW based memory layout design. BRANCH=none BUG=b:63974384 TEST=Build and boot eve successfully. Change-Id: I4c8b79f047e3dc6b2deb17fdb745f004004526b6 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-30soc/intel/cannonlake: Add PrmrrSize and C6DRAM configSubrata Banik
This patch ensures coreboot can set PRMRR size and C6DRAM enable FSP-M UPDs. Change-Id: I61ec3b6a16e20526516f681ddc3c70755724ed8a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21266 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-29soc/intel/cannonlake: Fix Coverity scan errorLijian Zhao
Add return in case of null pointer to avoid coverity scan error, fixed 1.Coverity ID 1379849: Null pointer dereferences (FORWARD_NULL) 2.Coverity ID 1379848: Null pointer dereferences (FORWARD_NULL) Change-Id: Ica19735307736c8a55c29af88db8b1372f8779e4 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21155 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2017-08-29amd/stoneyridge: Change ACPI _PR.CPxx to _PR.PxxxMarc Jones
This is a bug introduced by this commit: stoneyridge: Fix CPU ASL \_PR table [commit I870f81] The following error is found in dmesg ACPI Error: [\_PR_.P000] Namespace lookup failure, AE_NOT_FOUND... ACPI Exception: AE_NOT_FOUND, During name lookup/catalog... ACPI Exception: AE_NOT_FOUND, (SSDT:AGESA ) while loading table... ACPI Error: 1 table load failures, 3 successful... ... acpi-cpufreq: overriding BIOS provided _PSD data And, "ls -la /sys/devices/system/cpu/cpufreq/" doesn't work The cause is that the Pstate SSDT table generated by AGESA expects CPU variables \_PR.Pxxx, not \_PR.CPxx as generated by coreboot. Use Kconfig to set the required string. BRANCH=none BUG=b:64885241 TEST= Check dmeg and ls -la /sys/devices/system/cpu/cpufreq/ Change-Id: I4929f9a1c39705c6df9d965c8d030f4d1f0b5e5f Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/21165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-28soc/amd: Standardize guards on header filesMartin Roth
The guards in the header files were inconsistent. Some had no leading or trailing underscores, some had one, some had both leading and trailing. Change all to double leading & trailing underscores. Change all comments to have a space before them instead of tabs BUG=b:62235990 Test=Build Kahlee Change-Id: I4466df529ab201c922096a31d7438381778b582f Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-08-28soc/amd/stoneyridge: Increase preram console sizeMarshall Dawson
Increase the default setting to add more CAR space for the early console. This avoids truncation of the log. BUG=b:64980233 Change-Id: Ia11d1c6c186a7025510c240206743ebe8d741461 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21186 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-28soc/intel/skylake: Fix FSP1.1 booting issue with HW based dram top calculationSubrata Banik
This patch ensures skylake device using FSP1.1 can use HW based DRAM top calculation which was broken due to skylake fsp1.1 not honoring any UPD to know PRMMR size and default reserving 1MB for PRMRR size. This WA is not needed for FSP2.0 implementation due to PrmrrSize UPD is available and considering into hw based dram top calculation. BRANCH=none BUG=b:63974384 TEST=Build and boot lars which is using skylake 1.1 fsp. Change-Id: Iade0d2cb2a290fc4c9f0e6b1eaadc8afff2fa581 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2017-08-26soc/intel/skylake: Move SPI lock down config after resource allocationBarnali Sarkar
This patch to ensures that coreboot is performing SPI registers lockdown after PCI enumeration is done. This requirements are intended to support platform security guideline where all required chipset registers are expected to be in lock down stage before launching any 3rd party code as in option rom etc. coreboot has to change its execution order to meet those requirements. Hence SPI lock down programming has been moved right after pci resource allocation is donei, so that SPI registers can be lock down before calling post pci enumeration FSP NotifyPhase() API which is targeted to be done in BS_DEV_ENABLE-BS_ON_ENTRY. TEST=Ensure SPIBAR+HSFSTS(0x04) register FLOCKDN bit and WRSDIS bit is set. Also, Bits 8-12 of SPIBAR+DLOCK(0x0C) register is set. Change-Id: I8f5a952656e51d3bf365917b90d3056b46f899c5 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/21064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-26soc/intel/cannonlake: use __packedAaron Durbin
Now that there is a handy macro utilize it. Change-Id: I560bc7a591075235229952cdea63d4e667f323ee Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-08-26soc/intel/skylake: Move DMI lock down config after resource allocationSubrata Banik
This patch to ensures that coreboot is performing DMI registers lockdown after PCI enumeration is done. This requirements are intended to support platform security guideline where all required chipset registers are expected to be in lock down stage before launching any 3rd party code as in option rom etc. coreboot has to change its execution order to meet those requirements. Hence BIOS Interface lock down through Sideband access has been moved right after pci resource allocation is done, so that BILD lock down is getting executed along with LPC and SPI BIOS interface lockdown settings before calling post pci enumeration FSP NotifyPhase() API which is targeted to be done in BS_DEV_ENABLE-BS_ON_ENTRY. TEST=Ensure DMI register offset 0x274c bit 0 is set. Change-Id: Ie66701d5bd8c8f389e23fb30c8595dd83cf6b1ae Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25soc/intel/braswell: Put SERIRQ in quiet modeHannah Williams
Cherry-pick from Chromium commit 1568761. Original-Change-Id: If459c3cab8fb7ca13d8bff3173a94855ec2e2810 Original-Signed-off-by: Hannah Williams <hannah.williams@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Kevin K Wong <kevin.k.wong@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@google.com> Original-Tested-by: Aseda Aboagye <aaboagye@chromium.org> Change-Id: Ibb2e6d316adcfcc0d56d242501aac9c4c0bbdf62 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25soc/intel/braswell: Populate NVS SCC BAR1Hannah Williams
Cherry-pick from Chromium commit f92d7be. This BAR is used in _PS0 and _PS3 methods and is used by kernel driver to put SD controller in D3 Original-Change-Id: Iae4722cb222f61e96948265f57d6b522065853d9 Original-Signed-off-by: Hannah Williams <hannah.williams@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@google.com> Original-Tested-by: Aseda Aboagye <aaboagye@chromium.org> Change-Id: I59973226d57fe1dc3da21b2cec1c7b9a713829ab Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25soc/intel/braswell: select GENERIC_GPIO_LIBMatt DeVillier
Needed for to-be-added Google Braswell boards which make use of common GPIO library function to determine installed RAM type. Change-Id: Ie9b0c6513f10b252bf0a5014bd038d24879421be Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25soc/intel/cannonlake: Init UPD params based on configPratik Prajapati
Initialize UPD params based upon config Change-Id: Ib2ee58f8432a957ef389b40f717533e4cfe774b9 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21175 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-25soc/intel/skylake: Remove TCO lock down programmingSubrata Banik
FSP is doing TCO lock inside Post PCI bus enumeration NotifyPhase(). Hence remove TCO Lock down programming from coreboot. TEST= Ensure TCO_LOCK offset 8 bit 12 is set. Change-Id: Iec9e3075df01862f8558b303a458126c68202bff Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25soc/intel/common: Add function to DLOCK PR registersBarnali Sarkar
Add a function in FAST_SPI library to discrete lock the PR registers 0 to 4. BUG=none BRANCH=none TEST=Build and boot poppy Change-Id: I46e1948315ea9489932efdf7d60d6d78ab3948a6 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/21063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25soc/intel/skylake: Move PMC lock down config after resource allocationSubrata Banik
This patch to ensures that coreboot is performing PMC registers lockdown after PCI enumeration is done. This requirements are intended to support platform security guideline where all required chipset registers are expected to be in lock down stage before launching any 3rd party code as in option rom etc. coreboot has to change its execution order to meet those requirements. Hence PMC register lock down has been moved right after pci resource allocation is done, so that PMC registers can be lock down before calling post pci enumeration FSP NotifyPhase() API which is targeted to be done in BS_DEV_ENABLE-BS_ON_ENTRY. TEST=Ensure PMC MMIO register 0xC4 bit 31 is set. Change-Id: Ibd86a38fa78752ce007da63a9ccdd991ca21ab92 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25soc/intel/skylake: Remove ABASE lock down programmingSubrata Banik
FSP is doing PMC ABASE lock inside Post PCI bus enumeration NotifyPhase(). Hence remove ABASE Lock down programming from coreboot. TEST= Ensure GEN_PMCON_B offset 0xA4 bit 17, 18 is set. Change-Id: I800e654c7d8dc55cc0e8299501c1f85c57882e9d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25soc/intel/skylake: Move LPC lock down config after resource allocationSubrata Banik
This patch to ensures that coreboot is performing LPC registers lockdown after PCI enumeration is done. This requirements are intended to support platform security guideline where all required chipset registers are expected to be in lock down stage before launching any 3rd party code as in option rom etc. coreboot has to change its execution order to meet those requirements. Hence lpc register lock down has been moved right after pci resource allocation is done, so that lpc registers can be lock down before calling post pci enumeration FSP NotifyPhase() API which is targeted to be done in BS_DEV_ENABLE-BS_ON_ENTRY. TEST=Ensure LPC register 0xDC bit 1 and 7 is set. Change-Id: I705a3a3c6ddc72ae7895419442d67b82f541edee Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25soc/intel/common: Move update_mrc_cache after BS_DEV_ENUMERATESubrata Banik
This patch ensures that MRC cache data is already written into SPI chip before SPI protected regions are getting locked during BS_DEV_RESOURCES-BS_ON_EXIT. This requirements are intended to support platform security guideline where all required chipset registers are expected to be in lock down stage before launching any 3rd party code as in option rom etc. coreboot has to change its execution order to meet those requirements. Hence storing mrc cache data into SPI has been moved right after pci enumeration is done, so that SPI registers can be lock down before calling post pci enumeration FSP NotifyPhase() API which is targeted to be done in BS_DEV_ENABLE-BS_ON_ENTRY. TEST=Ensure MRC training data is stored into SPI chip and power_ Resume autotest is passing. Change-Id: I8ee26b5cc70433438cf4e45e707b8a54f89cf9b0 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21028 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25soc/intel/skylake: Add LPC and SPI lock down config optionSubrata Banik
This patch to provide new config options to perform LPC and SPI lock down either by FSP or coreboot. Remove EISS bit programming as well. TEST=Build and boot Eve and Poppy. Change-Id: If174915b4d0c581f36b54b2b8cd970a93c6454bc Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25amd/pi/hudson: Fix FCH ECMartin Roth
Move the fchec.h files, which do not seem mainboard specific, out of the mainboard directories into the southbridge/soc directories. Change-Id: Idd271c6ab618aa4badf81c702212e7de35317021 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-08-25soc/amd/stoneyridge: Move IMC ASL sourceKyösti Mälkki
This is not specific to a board but the binary IMC firmware used on the platform. Also remove unused IMSP and IMWK methods. Change-Id: I80026bca55f5ba236c080bcd882fc374559942e6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-08-25soc/amd/stoneyridge: Move oem_fan_control()Kyösti Mälkki
While at it, replace LibAmdMemFill() with memset(). Change-Id: I770cab446add8f305f02e365e7c9763df88cd958 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21192 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-24soc/intel/cannonlake: Add cpu.c and MP init supportPratik Prajapati
Add initial MP init support. This boots up all CPUs. Change-Id: Ia33691c17c663d704abf65320d4bf1262239524d Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21081 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-23soc/intel/skylake: Usable dram top calculation based on HW registersSubrata Banik
This patch ensures that entire system memory calculation is done based on host bridge registers. BRANCH=none BUG=b:63974384 TEST=Build and boot eve and poppy successfully with below configurations 1. Booting to OS with no UPD change 2. Enable ProbelessTrace UPD and boot to OS. 3. Enable PRMRR with size 1MB and boot to OS. 4. Enable PRMRR with size 32MB and boot to OS. 5. Enable PRMRR with size 2MB and unable to boot to OS due to unsupported PRMRR size. Change-Id: I9966cc4f2caa70b9880056193d5a5631493c3f3d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-23soc/intel/common: Early system agent library access in postcar stageSubrata Banik
BRANCH=none BUG=b:63974384 TEST=Build and boot eve successfully. Change-Id: Ie5558cdb7acacc34451e1cf63a3e4239e7901c67 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-23soc/intel/common: Add functions into common system agent librarySubrata Banik
This patch to add helper functions for memory layout design based on PCI Host Bridge/DRAM registers. BRANCH=none BUG=b:63974384 TEST=Build and boot eve successfully. Change-Id: I95250ef493c9844b8c46528f1f7de8a42cba88a2 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21133 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-23soc/intel/apollolake: Allow overriding dev tree settings by boardKane Chen
This change provides interface to override dev tree settings per board due to many projects share same devicetree.cb. BUG=b:64880573 TEST=Verify that dev tree settings can be overridden in mainboard on coral Change-Id: I349b1678d9e66022b586b6c7f344b831ed631c74 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/21142 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 20:30:53 +0000