coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2017-11-30	soc/intel/{APL,GLK}: Use Intel SRAM common code	V Sowmya
2017-11-30	soc/intel/common: Add Intel SRAM common code support	V Sowmya
2017-11-29	soc/amd/stoneyridge: Add mainboard call for SPD values	Marc Jones
2017-11-28	soc/intel/skylake: Make use of Intel common DSP block	Subrata Banik
2017-11-28	google/scarlet: support kd097d04 panel	Lin Huang
2017-11-28	rockchip/rk3399: support dual mipi dsi	Lin Huang
2017-11-28	rockchip/rk3399: mipi: properly configure PHY timing	Lin Huang
2017-11-28	rockchip/rk3399: improve mipi transfer flow	Lin Huang
2017-11-28	rockchip/rk3399: mipi: correct Feedback divider setting	Lin Huang
2017-11-28	rockchip/rk3399: mipi: correct phy parameter setting	Lin Huang
2017-11-28	rockchip/rk3399: mipi: Fix LOOP_DIV_HIGH_SEL to be 4 bits wide	Lin Huang
2017-11-28	intel/common/block: Add SKL CSME device ID	Subrata Banik
2017-11-28	AMD platforms: Fix ASL comment that implies "\_SB" is southbridge	Martin Roth
2017-11-23	soc/intel/cannonlake: Add PM methods to power gate SD card controller	Vaibhav Shankar
2017-11-23	soc/intel/cannonlake: Invoke pmc and hard reset only if CSE fails to reset	John Zhao
2017-11-23	Constify struct cpu_device_id instances	Jonathan Neuschäfer
2017-11-23	soc/amd/common: Include appropriate headers in dimm_spd.h	Marc Jones
2017-11-23	soc/amd/stoneyridge: Get entire DDR4 SPD	Marc Jones
2017-11-22	Create SOC description file soc.asl	Richard Spiegel
2017-11-21	src/soc/intel/apollolake: move TCO1 disable into bootblock	Vadim Bendebury
2017-11-21	soc/amd/stoneyridge: Add ELOG to SMM	John E. Kabat Jr
2017-11-21	amd/stoneyridge/spi: Fix reads greater than 5 bytes	Marshall Dawson
2017-11-21	soc/amd/common: Remove duplicated #include amd_pci_int_defs.h	Richard Spiegel
2017-11-20	soc/intel/cannonlake: Add ACPI workaround for EMMC	Lijian Zhao
2017-11-20	amd/stoneyridge: Fix SPD files and functions camel case	Marc Jones
2017-11-17	Move amd/stoneyridge/include/amd_pci_int_defs.h to include/soc/	Richard Spiegel
2017-11-17	soc/intel/cannonlake: fix gpio pin numbers	Bora Guvendik
2017-11-17	soc/intel/cannonlake: Add cpu.asl file	Shaunak Saha
2017-11-17	amd/stoneyridge: Enable SMI trap on SlpTyp	Marshall Dawson
2017-11-17	amd/stoneyridge: Add SlpTyp SMI handler	Marshall Dawson
2017-11-17	amd/stoneyridge: Add SPI controller driver	Marshall Dawson
2017-11-16	vendorcode/amd/pi/00670F00: Get rid of filecodes, replace filecode.h	Martin Roth
2017-11-15	mb/{amd/gardenia,google/kahlee}: move carrizo_fch.asl code to soc	Richard Spiegel
2017-11-15	soc/intel/skylake: Make use of common CSE code for skylake	Subrata Banik
2017-11-15	soc/intel/common: Use HOST_CSR to get circular Buffer Depth	Subrata Banik
2017-11-15	soc/intel/common: Add HECI message retry count	Subrata Banik
2017-11-15	soc/intel: Enable ACPI DBG2 table generation	Duncan Laurie
2017-11-15	soc/intel/cannonlake: Fix and clean up xhci ACPI code	Vaibhav Shankar
2017-11-14	soc/amd/stoneyridge: Remove direct AGESA header includes	Martin Roth
2017-11-14	soc/amd/common: Remove direct AGESA header includes	Martin Roth
2017-11-14	AMD Stoney Ridge: Add agesa_headers.h	Martin Roth
2017-11-14	amd/common/spi: Update flash driver usage	Marshall Dawson
2017-11-14	soc/amd/stoneyridge: Load SMU fimware using PSP	Marshall Dawson
2017-11-14	amd/stoneyridge: Add generic IMC sleep and wakeup	Marshall Dawson
2017-11-14	amd/stoneyridge: Replace BIT(n) in southbridge	Marshall Dawson
2017-11-14	amd/stoneyridge: Define bits for AcpiConfig	Marshall Dawson
2017-11-13	soc/intel/common: Add error print in common i2c	Lijian Zhao
2017-11-13	soc/intel/cannonlake: Define default LPSS clock	Lijian Zhao
2017-11-13	soc/amd/stoneyridge: Add CPU PPKG ASL	Marc Jones
2017-11-13	soc/amd/stoneyridge: Add GNVS variables for thermal control	Marc Jones