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2015-03-28tegra132: use generic GIC driverAaron Durbin
As the arm64 boot flow handles initializing the GIC by way of the driver provide the SoC support for that driver and use it. BUG=chrome-os-partner:31945 BRANCH=None TEST=Built and booted kernel on ryu. Change-Id: I6ba20339be8fc823e241b4299ad6c3deb82799fa Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 582cd9cef58e27aef2ce9c9b4fba4a78365bec6e Original-Change-Id: I34efaf28369377f353b4c51d20d19c9433befda4 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/217514 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9077 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-03-28arm64: Replace CONFIG_* variables with {read/write}_currentFurquan Shaikh
Instead of relying on config variables to determine the current el, use {read/write}_current macros for accessing registers. BUG=chrome-os-partner:30785 BRANCH=None TEST=Compiles successfully and boots to kernel login prompt Change-Id: I6c27571fa65e06e28b71fee3e21d6ca93542e66b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 96aed53b2879310f6f979d5aa78b8d1df7f04564 Original-Change-Id: If4a5d1e9aa50ab180c8012862e2a6c37384f7f91 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/217148 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9065 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28tegra132: update MTS version formattingAaron Durbin
Nvidia tracks their MTS versions using decimals. Update the format so there isn't an extra step in communicating versions while debugging things. BUG=chrome-os-partner:31864 BRANCH=None TEST=Booted and confirmed decimal print out. Change-Id: I8d8b8a6e9b80548509dd8a30abb17c9970afdead Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b7deb04a1deed41e1a54713320a29f6731401b35 Original-Change-Id: Ia7d0bc49318a4b4c969ee37e762e084ec65de543 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/217260 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9061 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28tegra132: remove bring_up_secondary_cpu chip optionAaron Durbin
Now that there is cpu devicetree support retire the bring_up_secondary_cpu option as the devicetree is the way going forward to do other CPU bring up. BUG=chrome-os-partner:31761 BRANCH=None TEST=Built and booted with 2nd core. Change-Id: I3e8812cd2183f2126c11c36ff4844c15b3cbfc1b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7eab33b763d33d6be210ddb69e3c67411bad0fd0 Original-Change-Id: Ic213fbf56a1846e73462886f876a0a70e48b3158 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216929 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9060 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27broadwell: add support for smbios type17 in broadwellKane Chen
This change also depends on mrc due to changes in pei_data.h Report smbios type 17 for each memory CQ-DEPEND=CL:210005 BUG=None BRANCH=None TEST=Compiles successfully See smbios type17 in OS by dmidecode Original-Change-Id: If83c99364726cd17c719a59ed8ac993736c63b9a Original-Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/210399 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> (cherry picked from commit 6da6b4ffb3a45fdd766b88220c2adb168b3c5e10) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I39ea9ef9b342239fe26846ab0a928f6a680c21e8 Reviewed-on: http://review.coreboot.org/8956 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-27rk3288: Add GPIO() macroJulius Werner
The static gpio_t initializers are stylish, but they are still a little too annoying to write and read in day-to-day use. Let's wrap that in a macro to make it a little easier to handle. BUG=None TEST=None Change-Id: If41b2b3fd3c3f94797d314ba5f3ffcb2a250a005 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 102a5c0a800f43d688d11d1d7bbc51e360341517 Original-Change-Id: I385ae5182776c8cbb20bbf3c79b986628040f1cf Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220250 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9052 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27rk3288: Add missing #include and use uniform typesDavid Hendricks
This updates timer.h to #include the header necessary for u32, and to change the one instance of uint32_t to u32 to be uniform. BUG=none BRANCH=none TEST=compiled Change-Id: I4d67045206fd94985774b8d46a307bbb2e337f30 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4ff2629fdf3c69c203fa61ec894bb4895990cb5e Original-Change-Id: Ie406fb1f518af5d1fd1e623630b2bcbbef35622c Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220612 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9051 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27soc/imgtec/pistachio: Add IMGTEC SPI controller driverIonela Voinescu
The Serial Peripheral Flash Interface (SPFI) block allows communication with various devices over the SPI bus. It uses a configurable transaction interface and it clocks the bus according to the configured command, address, gap (aka dummy) and data lengths. This controller requires the SPI_ATOMIC_SEQUENCING flag set (write and read done in the same transaction) as it cannot directly control CS and will assert/de-assert CS at the beginning/end of a transaction itself. Note that the size of any transfer cannot be greater than 64KB - 1, as this is configured in a 16-bit field. The SOC has 2 SPFI interfaces each of them providing 5 slave select lines. SPFI 0 supports single and dual modes, SPFI 1 supports single, dual and quad modes. For SPFI interface 0: - The block needs the system PLL and the following top level SPI clock registers to be set: - CR_cr_top_spi0clkinternal_CTRL[2:0] with division value - CR_MIPS_CLOCK_GATE[19]: bit cr_top_SPI0CLKOUT_MIPS set - CR_cr_top_SPI0CLKOUT_CTRL[6:0] with division value - The following MFIO configuration parameters are also required: Signal name Pad name MFIO mode spim0_d0_txd MFIO_MIPS_10 0 spim0_d1_rxd MFIO_MIPS_9 0 spim0_mclk MFIO_MIPS_8 0 spim0_cs0 MFIO_MIPS_2 1 spim0_cs1 MFIO_MIPS_1 1 spim0_cs2 MFIO_MIPS_55 1 MFIO_MIPS_28 1 spim0_cs3 MFIO_MIPS_56 1 MFIO_MIPS_29 1 spim0_cs4 MFIO_MIPS_57 1 MFIO_MIMPS_30 1 For SPFI interface 1: - The block needs the system PLL and the following top level SPI clock registers to be set: - CR_cr_top_spi1clkinternal_CTRL[2:0] with division value - CR_MIPS_CLOCK_GATE[20]: bit cr_top_SPI1CLKOUT_MIPS set - CR_cr_top_SPI1CLKOUT_CTRL[6:0] with division value - The following MFIO configuration parameters are also required: Signal name Pad name MFIO mode spim1_d0_txd MFIO_MIPS_5 0 spim1_d1_rxd MFIO_MIPS_4 0 spim1_mclk MFIO_MIPS_3 0 spim1_d2 MFIO_MIPS_6 0 spim1_d3 MFIO_MIPS_7 0 spim1_cs0 MFIO_MIPS_0 0 spim1_cs1 MFIO_MIPS_1 0 MFIO_MIPS_58 1 spim1_cs2 MFIO_MIPS_2 0 MFIO_MIPS_55 2 MFIO_MIPS_31 1 spim1_cs3 MFIO_MIPS_56 2 spim1_cs4 MFIO_MIPS_57 2 BUG=chrome-os-partner:31438, chrome-os-partner:32441 TEST=Tested as bare-metal driver on Pistachio FPGA Change-Id: I3b3e4475976e6fba58cef93b12d997ec5cb26341 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 621849942e27f7d6cf2c8ade7f2c4d18d2318b91 Original-Change-Id: Ib257eb6236bd2895281175871b4ab979660f1239 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/217320 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9049 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27urara: use proper SOC nameVadim Bendebury
Danube has become Pistachio, let's rename all instances where this SOC is mentioned. BUG=none TEST=board urara still builds Change-Id: Iea91419121eb6ab5665c2f9f95e82f461905268e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 58696cc7c77a70dca2bfd512d695d143e1097a78 Original-Change-Id: Ie5ede401c4f69ed5d832a9eabac008eeac6db62d Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220401 Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org> Reviewed-on: http://review.coreboot.org/9048 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: support arm64 SMP bringupAaron Durbin
Use the formal devicetree way for bringing up each of the cpus. This includes providing a cpu_driver as well as calling arch_initialize_cpus() with the proper operations to start the cores. BUG=chrome-os-partner:31761 BRANCH=None TEST=Booted SMP on ryu. Change-Id: I276fe08916bc0c46c8f4dd30e47c7d9b135e2bbd Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 038daec1b74f4c414ab7ad153d34e48d4644183a Original-Change-Id: I13d8bfd645abf66f270d56d48eff4331c4ea1200 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216926 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9043 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: remove printk() before console_init()Aaron Durbin
printk() shouldn't be called until the consoles have been initialized. This just so happened to work by luck. Once CONFIG_SMP is enabled that breaks because of spinlock usage in uncached memory. BUG=chrome-os-partner:31761 BRANCH=None TEST=Built with CONFIG_SMP and ramstage doesn't hang early. Change-Id: I4bf5d98e409840cf07a7759e9273d770f3bbf8bb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6ec672e52eda69f2b5abb747807a496bb973088f Original-Change-Id: I247caac410894fb896dfb25a27c3a3213ef7f020 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216429 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9036 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: Fix clock apisFurquan Shaikh
Instead of directly using the clk_src_id based on enum for clock source, every device needs to have its own set of clk source ids defined. This prevents accidentally selecting a wrong clk source if the ids are different from host1x's. Also, clk_src_id is separated from clk_src_freq_id. clk_src_id is the clk src id represented in CLK_SOURCE_<dev> registers, whereas clk_src_freq_id is used for handling the common clock sources based on id to get the proper frequency in software. [pg: integrated a later commit to fix the build] BUG=chrome-os-partner:31821 BRANCH=None TEST=Compiles successfully and boots to kernel prompt Change-Id: I5d40fb49b81e8838b2be071d32c466213215e0d6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 27d5d6a34d1c826c6095c18368efb78c228d4ca8 Original-Change-Id: I5c88bed62841ebd81665cf8ffd82b0d88255f927 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/216761 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Commit-Id: 13c30c50a9e8a7f3c48673a2f6c144ba546129b6 Original-Change-Id: I6659858c24e925aec9495bf64344c0000ad19b4c Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/217342 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9033 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: Add LPDDR3 SDRAM init in coreboot.Tom Warren
Expanded sdram.c to add support for LPDDR3 init. This code can be used with matching BCT .inc files to have LPDDR3 SDRAM initialized by coreboot instead of the T132 BootROM. BUG=chrome-os-partner:29921 BUG=chrome-os-partner:31031 BRANCH=None TEST=Built for rush and rush_ryu. Change-Id: I53801d9399dbf67fd86d0a2521174f0668567620 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 60e130c47c1894925a12f251af5b83a1fa144d57 Original-Change-Id: I6bcffcd22d2e4f8da6d729b6757714657f3f6735 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214753 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9029 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: return actual plld frequencyAaron Durbin
Depending on the requested frequency the plld cannot necessarily obtain the exact clock. Therefore provide the closest configured frequency as a return value. This is equivalent to the t124 patch. BUG=chrome-os-partner:31640 BRANCH=None TEST=Built and noted plld actual value close to requested. Change-Id: I9aaba81222fb97d9fbbb4156af3a7476ba654c10 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fc928db8197b465220e53b4d0ba5896b3c06a863 Original-Change-Id: I94b94a1bf01087ff0d0e4b1ef3fb59eec2a8ba15 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214843 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Reviewed-on: http://review.coreboot.org/9025 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: No need for Kconfig variables for stacksFurquan Shaikh
With the latest changes to include stack storage within ramstage, we no longer need to define Kconfig options for ramstage/exception stacks in arm64. BUG=None BRANCH=None TEST=Compiles successfully and boots to kernel on ryu Change-Id: I7361d8f567453e775240151fd1180c49025141b3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9aaa89115a67606fcb66eb354741043f7f2094bf Original-Change-Id: I93c23ac3fa9adab4eac3c739023cbae3e5135497 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214607 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9023 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: add spin table supportAaron Durbin
Until PSCI is functional the other core still needs to be brought up in the kernel. The kernel boots these cpus with the spin table which is just an address in memory to monitor a jump location. BUG=chrome-os-partner:31545 BRANCH=None TEST=Built and brought up secondary core in linux. Change-Id: Iaa69110f6a647d8fd4149119d97db4fc45d7da00 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 01ca36685852bc5dd85fd4015c8a1e600e23e7ca Original-Change-Id: Ieaf19cd70aff3e6c8de932e04b1b5aba71822a97 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214777 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9021 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: add option to bring up and init secondary cpuAaron Durbin
Optionally bring up secondary cpu according to devicetree. BUG=chrome-os-partner:31545 BRANCH=None TEST=Built and enabled bringing up second core on ryu. Change-Id: I5ede8b2f1b30a6170520cc11c18e263793cea301 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d7da2dcce9be653a3c551c33bbefb3810a6949e9 Original-Change-Id: Ia3f2c10dab2bbfd65ba883451bf4eafc26f2e7cf Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214776 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9020 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: support GIC secondary cpu supportAaron Durbin
For the secondary CPUs the set of banked registers needs to be initialized. In the boot CPU path all both the CPU's banked registers and the global register set is initialized. BUG=chrome-os-partner:31545 BRANCH=None TEST=Built and brought up 2nd cpu in kernel. Change-Id: I3a7bc708f726c4435afca817a251790f536844d9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 813b0a8b3faacf2342164d385e5837ebede29b18 Original-Change-Id: Ie5db56ca052eebac4ed1a34eaeeb6bbd8a26ca30 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214774 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9018 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27arm64: make mmu_enable() use previous ttb from mmu_init()Aaron Durbin
No need to pass in the same value for the ttb after just calling mmu_init(). All current users are setting this once and forgetting it. BUG=chrome-os-partner:31545 BRANCH=None TEST=Built and booted on ryu. Change-Id: Ie446d16eaf4ea65a34a9c76dd7c6c2f9b19c5d57 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bd77461d483b513a569365673c83badc752f4aa8 Original-Change-Id: I54c7e4892d44ea6129429d8a46461d089dd8e2a9 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214772 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9016 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: select EL3 cpu start up stateAaron Durbin
The armv8 cores in tegra132 start in EL3. Indicate as such. BUG=chrome-os-partner:31545 BRANCH=None TEST=Built and noted Kconfig selection. Change-Id: I80f323a7d14c5376c8233c42dcc28f64ef07c9a2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8af81929a82e3b686026b2ea648145e5fee98970 Original-Change-Id: I83370a03cfc0f04058ae2b6d87b09b96642df97d Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214667 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9011 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: implement smp_processor_id()Aaron Durbin
Implement smp_processor_id() for the arm64 cores. BUG=chrome-os-partner:31545 BRANCH=None TEST=Built. Change-Id: Id2fca068f92cdc816b02b5e7ce1229517787684a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d5c5c68329631ce0fc3cebef1c2422aa44ac192d Original-Change-Id: I7a1cd2f94ba4ae1854450cc60ef8a62f2457aabb Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214664 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9008 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: increase MAX_CPUS to 2Aaron Durbin
There are 2 cores visible to the OS and both need to be brought up. Therefore, provide the proper number of cores. BUG=chrome-os-partner:31545 BRANCH=None TEST=Built and noted CONFIG_MAX_CPUS=2. Change-Id: I8a99891506af0fb3aa0284475c3c4be8bb69268b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: efa6c0343521dd98b86eacc94737f3497b721f95 Original-Change-Id: Id31b0a3046e40e1aec09bf2ee66b1e2f0b27fd21 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214661 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9006 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: Increase TrustZone Carveout Region sizeFurquan Shaikh
Increase TZ carveout region size to 4MiB. TTB lives in the first 1MiB of the trust zone. Rest of the TZ memory can be used by el3 monitor. BUG=chrome-os-partner:31615 BRANCH=None TEST=Compiles successfully and boots to kernel Change-Id: I448574860186815992c15a358a1481faecf224bd Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: de0f3f8016a4e566a2bacb967ef92213648d8257 Original-Change-Id: I1f25b7b119037cba7055a1bd61997f020a0b1010 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214370 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9003 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: refactor cpu startup codeAaron Durbin
In order to more easily bring up the 2nd core refactor the cpu startup logic. A common 32bit_entry.S is compiled both for romstage and ramstage to provide the common 32-bit entry point. BUG=chrome-os-partner:31545 BRANCH=None TEST=Built and booted ryu to the kernel. Also, can get the 2nd core up out of reset. Change-Id: I0c2c9f637189009767e8d5510732678c64e62a2a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7394b271bf67dfad8a601f41faaac8f07ae6d4a5 Original-Change-Id: Id810df95c53d3dc8b36d8bd21851d3b0006a8bc2 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/213850 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9001 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: Add exception stack top addressFurquan Shaikh
BUG=chrome-os-partner:31515 BRANCH=None TEST=Exception handling for ryu works fine Change-Id: Ibeac161428c77718a640aa11361fb8d822b4a343 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 131f9fca0995a8d07972a5bc5ec76bfea0f1cb42 Original-Change-Id: I5b109d9eb692b9e4ef4bc1f6cf267420f50764da Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/213674 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8998 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: add enums for bus namesAaron Durbin
Instead of requiring the mainboards to know the magic literals for the bus numbers provide an easier name to number to handle all the weird ordering. BUG=chrome-os-partner:31106 BRANCH=None TEST=Built and booted on ryu. Change-Id: I4a90f5f5f3ed1d936e2eee23f4726069adc49cc7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b028e90650384c947a3d0ee84c6d1346a22b22b9 Original-Change-Id: Id4d773d3049a43b186711900c61935ba7f3562ce Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/213491 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8996 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: initialize GICAaron Durbin
This provides are barebones initialization for tegra132 GIC on CPU0. It routes all interrupts to CPU0, moves them all into group 1, and attempts to allow non-secure access for all registers (doesn't appear to be implemented, though). BUG=chrome-os-partner:31449 BRANCH=None TEST=Built and booted past smp init in the kernel. Timers appear to be flowing now since jiffies are updated. Change-Id: Id45c13cc23e50feed3d88da13420c9eb694498a0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 81bad0a53083baa7af0f1fd5f82fef0538ee62df Original-Change-Id: I69dd9ae53f259e876a9bc4b9d7f65330150d2990 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/212795 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8995 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: move page tables to trustzone regionAaron Durbin
In order to access secure device register space the cpu needs to have the page tables marked as secure memory. In addition the page tables need to live within secure memory otherwise the accesses default to non-secure. Therefore move the page tables to the trustzone region. Remove the TTB_* config options as well as removing the TTB reservations from coreboot's resource list. BUG=chrome-os-partner:31355 BUG=chrome-os-partner:31356 BRANCH=None CQ-DEPEND=CL:213140 TEST=Built and booted into kernel. Change-Id: I1fc8dda932c36935f8523792bc1147f6b0743d11 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1522a83bb57e33749843d5b3ea5545ded97a3953 Original-Change-Id: Ia4b9d07ef35500726ec5b289e059208b9f46d025 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/213141 Reviewed-on: http://review.coreboot.org/8994 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: Add special I2C6 initTom Warren
I2C6 has a special mux in the SOR/DC domain, so there's a ton of devices that need to be clocked, SOR unpowergated, and then the I2C6 muxing done in the DPAUX_HYBRID_PADCTL register. BUG=none BRANCH=none TEST=none, built rush/ryu AOK Change-Id: Ibeeda763b7fb30fabaee85d03fbf7d5efb42a30a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0b4da98e20a89b045f2d5b5033a27cd7ab855f35 Original-Change-Id: I4aaa74ef1b3009da621d1a2ef6f79de8ebf545e2 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/212887 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8992 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: separate/refactor clock enable/reset codeTom Warren
Added distinct functions for clock_enable and clock_clear_reset, and rewrote clock_enable_clear_reset() to use them. Useful when unpowergating SOR partition, for instance, where we need to enable a bunch of periph clocks, unclamp SOR, then take all of those periphs out of reset. BUG=none BRANCH=none TEST=none, built rush/ryu OK. Change-Id: I92edf3104adc8eb7637c47a5e000788fd55f1452 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4fd76a6d0d0fb7922c6beacbc1cfcb365b6537b2 Original-Change-Id: I6fef5a72421cb4e3d7edb33a66f62b6e14865a32 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/212916 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8991 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27tegra132: never recover cbmem from romstageAaron Durbin
Tegra132 has 2 different paths for booting and resuming from sleep. The boot path uses the typical bootblock, romstage, and ramstage. However, the resume path is completely orthogonal. cbmem_initialize() attempts to recover the cbmem area, but that functionality should not be used from romstage because tegra132 is by definition in a fresh boot if it is executing romstage. Therefore, use cbmem_initialize_empty() so that cbmem is always initialized from scratch on each boot. BUG=chrome-os-partner:31239 BRANCH=None TEST=Built and ran on ryu. Was able to enter recovery and stay in recovery without entering a reboot loop. Change-Id: I0453c15e57a873a7ce7a63190dceafb75e4c9342 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 28ebc092e6721552c18db03e7578424c23a64b64 Original-Change-Id: I2016146fdc3aea493a78bab31ea8c8cbd78935c5 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211424 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8990 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27broadwell: Fix some errors in selftestKane Chen
1. Fixed some errors in selftest compare to reference. 2. Some WA steps for xhci in sleep trap is only for lpt. BUG=chrome-os-partner:28234 TEST=compile ok, run selftest on auron to verify boot to OS BRANCH=None Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Change-Id: Iaccb087581d5f51453614246bf80132fcb414131 Original-Reviewed-on: https://chromium-review.googlesource.com/215646 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Commit-Queue: Kane Chen <kane.chen@intel.com> Original-Tested-by: Kane Chen <kane.chen@intel.com> (cherry picked from commit 97761b4ad3073fff89aabce3ef4f763383ca5cad) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I2b1d5be4f8a13eb00009a36a199520cd35a67abf Reviewed-on: http://review.coreboot.org/8971 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27broadwell: Apply pcie updates from 2.1.0 ref codeKane Chen
some clock gating and pcie settings are missed in original code BUG=chrome-os-partner:28234 BRANCH=None TEST=build and boot on samus verify registers between samus and crb Original-Change-Id: I931276adb2f2667c4f9e7611acfd709b7232d492 Original-Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214568 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> (cherry picked from commit 57e42c781d435092a08238461f0605dbf092e576) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ia62a50f28a411bbd2ba51b94de17ca70051ea093 Reviewed-on: http://review.coreboot.org/8967 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27broadwell: Read and save HSIO version from ME in romstageDuncan Laurie
This can be used to know if HSIO registers need updating in ramstage but it is not possible to query the ME for HSIO version after sending the DRAM-init-done message. BUG=chrome-os-partner:28234 BRANCH=samus TEST=build and boot on samus, check for HSIO version messages in log Original-Change-Id: Id6beeaf57287e8826b9f142f768636a9c055d7eb Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214259 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 637cbf5c1a1d922dab3f8a5cd4b3cd05617d1b92) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I29ce907804e892afde5f91e0b21688a50217cf13 Reviewed-on: http://review.coreboot.org/8966 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27broadwell: Fix GPE register addressesDuncan Laurie
This macro is incorrect and should be counting by dword instead of byte. The effects of this were subtle: incorrect events in ELOG and hanging when waking from USB input because PME_B0 was not disabled properly. BUG=chrome-os-partner:31611 BRANCH=none TEST=test wake from suspend with USB keyboard Original-Change-Id: I7caf1d46283071787550a9765703897181774957 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214258 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 3cfc4a1812466cb1c1317b8f21321aafee623857) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I3e2f8190d824692ecb961615becf65319a6ffd8b Reviewed-on: http://review.coreboot.org/8965 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27broadwell: Changes from 2.2.0 ref codeDuncan Laurie
- The SATA CAP register setup was moved outside the refcode blob we run so it needs to be set up by coreboot again... - Slight tweak to fast ramp voltage for broadwell CPU BUG=chrome-os-partner:25491 BRANCH=None TEST=Build and boot on samus Original-Change-Id: I7bdc0811ad8f28ab0912972036dca59d229b0173 Original-CSigned-off-by: Duncan Laurie <dlaurie@chromium.org> Original-CReviewed-on: https://chromium-review.googlesource.com/214024 Original-CReviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 5d166a0c4d206eaa885ecebaa0c3cefefdc59280) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Id58d3bee5e713139edf6e8fda8cdf4c48ba95bd1 Reviewed-on: http://review.coreboot.org/8964 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27broadwell: Add broadwell specific platform ASLDuncan Laurie
This can be shared between mainboards, they are still free to override if needed. BUG=chrome-os-partner:28234 BRANCH=none TEST=build and boot on samus Change-Id: I85fae6e254adcbda1c52410d5ba046f3f05b54c0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/213792 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 3e40cb804e7a95ce2183ebb3ef5d86820aef61b5) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/8961 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27broadwell: fixed power gating enable for disabled sata portKane Chen
The original code won't set power gating for disabled port correctly, due to it must be set before Lock BUG=chrome-os-partner:28234 BRANCH=None TEST=build and boot on samus verify bit 24, 26 is set in RCBA(0x3a84) for samus Original-Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Change-Id: Id78d391ac657665a972cb4fd1810df6304a5a6ab Original-Reviewed-on: https://chromium-review.googlesource.com/213561 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Tested-by: Kane Chen <kane.chen@intel.com> Original-Commit-Queue: Kane Chen <kane.chen@intel.com> (cherry picked from commit 066c8c81df8be9ae9ab7b33342a93b0b3ea7b240) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ic7c87b04863f93de5665d72e0f95b4105b1d4d3b Reviewed-on: http://review.coreboot.org/8960 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27broadwell: sata updates from 2.1.0 ref codeKane Chen
fixed a coding error and sync sata configuration with ref code BUG=chrome-os-partner:28234 BRANCH=None TEST=build and boot on samus verify registers between samus and crb Original-Change-Id: I09dd80a9772ac82b841363a540c9b7a8689e04a9 Original-Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/213137 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> (cherry picked from commit 0fbb59e3c5117a513ef19117560bb41dfe8c0d71) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I99a389b06f4ec077c298100ca878c68ef69debfa Reviewed-on: http://review.coreboot.org/8959 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27broadwell: Fix devslp enable to use correct registerDuncan Laurie
This was a merge error when I was pulling in some of the code into this file I put it after the read of CAP2 but before it is modified and written back. In the end the DEVSLP bits are getting set/cleared that need to but the other bits in the register may be wrong. Also when enabling devslp set the devslp-present bit in each enabled port. Also remove much of the 0:1f.2@0x98 setup and the attempt to write (the write once) CAP register that is already being written in the reference code. BUG=chrome-os-partner:28234 BRANCH=None TEST=build and boot on samus Original-Change-Id: I467f3c15b9f4d4c814ba0ef8baf95739b4bc6662 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/212308 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 9110a42982183b2954c865abbf18e008a39c997c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I7db5c7ccf619aa28856388dd40f59495ef6d7e77 Reviewed-on: http://review.coreboot.org/8958 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27broadwell: Add small delay before Flex Ratio rebootDuncan Laurie
In order to prevent possible TPM lockout due to PLTRST assertion shortly after powering up add a small delay before the reset. This will affect cold power up only, reboot/resume/warmboot will all have the flex ratio locked already so this reset is unneeded. BUG=chrome-os-partner:29859 BRANCH=None TEST=build and boot on samus. I tried unsuccessfully to trigger the TPM lockout, but I was not able to do that consistently without this patch so it is unknown yet whether this is 100% effective. Original-Change-Id: Ief8c9261c0268b0f90a3022213ebd2b06633b481 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211893 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 20413f2eafa144f5f381eb6f92d8b959415ca049) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I665e9ed1faa65e88d988660a24bdad40a4c5ab7e Reviewed-on: http://review.coreboot.org/8957 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27broadwell: Fix TCO register size and event reportingDuncan Laurie
TCO registers are 16bit not 32bit. Also do not log the TCO reset event in S3 resume path to avoid it being logged when TCO is not actually tripping. BUG=chrome-os-partner:28234 BRANCH=None TEST=manual: 1) build and boot on samus 2) modify kernel command line with nmi_watchdog=0 3) while sleep 1 ; do echo -n V ; done > /dev/watchdog & 4) fg 1 5) ctrl-Z 6) wait for reboot 7) check event log for TCO event 8) check suspend/resume path to ensure no TCO event logged Original-Change-Id: I9cd8627de8498b280deb088f3a8e1e20546e2f96 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211840 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 5952fe4672d07bd39e345f2048c2bfc510bf9f2a) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I6cdeffb8b50c5001d714edd3a1264cf117cd1ad6 Reviewed-on: http://review.coreboot.org/8954 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27broadwell: Misc updates from 2.1.0 ref codeDuncan Laurie
- ADSP IRQ should be exclusive - HDA should write reg 0x43 even if disabled - A few clock gating tweaks based on ref code changes - Move SATA clock gating to sata.c where SIR changes are done - Add support for enabling Deep SX in AC/DC modes - CLKREQ VR Idle for enabled PCIE ports BUG=chrome-os-partner:28234 BRANCH=None TEST=build and boot on samus Original-Change-Id: Icece58e32b7a5d2b359debd5516a230cae3fd48c Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211611 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit c0e22ba043ed96bdddca4989b2f29d0e989f6fef) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: If5f5e1666aa9660e31305ee6369f2febf6757b99 Reviewed-on: http://review.coreboot.org/8952 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27samus: Disable CMDPWR on broadwellKane Chen
Workaround for auto shutdown issue on broadwell SKU. Now we can see C7 transition, and MRC fastboot BUG=chrome-os-partner:29787,chrome-os-partner:29117 BRANCH=None TEST=build ok and boot on samus Original-Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Commit-Id: 932152b16c3943b00bd317e7370402dda451529f Original-Change-Id: Id1f174b67fa3e6f248dd8b21aee25e6e01abf33e Original-Reviewed-on: https://chromium-review.googlesource.com/210870 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Tested-by: Kane Chen <kane.chen@intel.com> Original-Commit-Queue: Kane Chen <kane.chen@intel.com> (cherry picked from commit 932152b16c3943b00bd317e7370402dda451529f) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ie9fb792635b39d33136cef576ae5559013d5947a Reviewed-on: http://review.coreboot.org/8950 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27broadwell: Tweak GFXPAUSE settings based on revisionDuncan Laurie
Changes from 2.1.0 reference code release. BUG=chrome-os-partner:28234 BRANCH=None TEST=build and boot on samus Original-Change-Id: I6110a9bdb2973f1a134d8105c37659bf43f61d34 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210607 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit ef660ddc6c17a003f06b8995e821c7642c49a56e) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ibb41cd7369cfc7b9b86b61460650a56415b3d8fb Reviewed-on: http://review.coreboot.org/8949 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27broadwell: Add config option to disable DSP power gating in D3Duncan Laurie
This is useful for debug and testing. BUG=chrome-os-partner:29649 BRANCH=None TEST=build and boot on samus Original-Change-Id: I9050e75fd7c308ebd97d196298c687f8b0f8f97d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210599 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 2831154af4f33717489cb0b62aef228fb8f7c2e2) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ie622df02d9ab219cefce5f11332e010b47e3ec6e Reviewed-on: http://review.coreboot.org/8947 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-26rk3288: switch to stopwatch APIAaron Durbin
Instead of using rela_time use the stopwatch API as the semantics fit perfectly with the expiration usage. BUG=None BRANCH=None TEST=None, but similar usage tested on tegra132. Change-Id: I91ef59212a2dd1b48640b1aaaab6acacf4e9b3e6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b1dd8380f04641f4f73caa3441f349d9eca6be05 Original-Change-Id: Iff3293debc2f85553c9e9b765084e5c00720012c Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219713 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8895 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26tegra132: allow mainboards to insert memory regions in address mapAaron Durbin
Depending on the needs of the mainboard certain regions of the address map may need to be adjusted. Allow for that. BUG=chrome-os-partner:31293 BRANCH=None TEST=With ryu patches able to insert a non-cacheable memory region. Change-Id: I68ead4a0f29da9a48d6d975cd41e2969db43ca55 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 88342562885b09c4350ba1c846b725b5f12c63d9 Original-Change-Id: Iaa657bba98d36a60f2c1a5dfbb8ded4e3a53476f Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/212161 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8925 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26tegra132: Initialize CNTFRQFurquan Shaikh
BUG=chrome-os-partner:31356 BRANCH=None TEST=Kernel boots with the changes required in depthcharge Change-Id: I061305e0ab8f6145c0dc74b2ff958a667ff7276a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0ff2fc86c1c6e6b592fa3faffd360a3a8c6351a9 Original-Change-Id: If1c5850607174ab0f485ef41d47016056d9832cd Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/212730 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8941 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26tegra132: add I2C6 controller to funit libraryTom Warren
BUG=None BRANCH=None TEST=Built rush and ryu, ran on rush into recovery mode. I2C6 is in the SOR domain, so a lot of further init is needed before it can be used. A follow-on patch will do this. Change-Id: I5701bfcf1d0bb8c6edd3d885b1b7dd14e67ba73a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 69908f2489d1a918bb109d43e713932214741b46 Original-Change-Id: I1160a182ee6e2b2b56479384efc6a9063590448f Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/212671 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8940 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-07 09:52:06 +0000