Age | Commit message (Expand) | Author |
2020-03-18 | soc/intel/tigerlake: Update FSP UPDs to turn on USB4/TBT | Brandon Breitenstein |
2020-03-18 | soc/mediatek/mt8183: Fix wrong setting of DRS config | Huayang Duan |
2020-03-18 | soc/mediatek/mt8183: Improve the AC timing of DRAMC | Huayang Duan |
2020-03-18 | soc/intel/apollolake: Allow toggling of GMM in devicetree in Gemini Lake | Franklin He |
2020-03-18 | soc: Remove copyright notices | Patrick Georgi |
2020-03-18 | soc/intel/skylake: Control fixed IO decode from devicetree | Wim Vervoorn |
2020-03-17 | soc/amd/picasso: Set I2C clock reference to 150MHz | Martin Roth |
2020-03-17 | soc/amd/picasso: Remove unused defines from cpu.h | Marshall Dawson |
2020-03-17 | soc/amd/picasso: Move get_soc_config to common location | Marshall Dawson |
2020-03-17 | src/soc/intel/tigerlake: Fix incorrect use of Field objects in ASL | Rizwan Qureshi |
2020-03-17 | soc/intel/cannonlake: Set correct serirq mode | Jeremy Soller |
2020-03-17 | soc/broadwell: remove unused function init_one_gpio() | Matt DeVillier |
2020-03-16 | soc/intel/tigerlake: Support ISH | li feng |
2020-03-16 | src/soc/tigerlake_dev: Update PMC IPC Hardware ID | John Zhao |
2020-03-15 | soc/intel/Kconfig: Avoid specifying dedicated chipset name | Subrata Banik |
2020-03-15 | soc/intel/common: Check prerequisites for GLOBAL_RESET command | Sridhar Siricilla |
2020-03-15 | soc/intel/common/block/cse: Modify handling of HMRFPO_ENABLE command | Sridhar Siricilla |
2020-03-15 | soc/intel/icelake: Re-flow comment for 96 characters | Paul Menzel |
2020-03-15 | soc/intel/icelake: Correct past participle in comment | Paul Menzel |
2020-03-15 | soc/intel/tigerlake: Match RP number with TGL EDS | Wonkyu Kim |
2020-03-15 | soc/intel/tigerlake: Enable CNVi through dev_enabled | Srinidhi N Kaushik |
2020-03-15 | soc/intel/tigerlake: Update Cpu Ratio settings | Srinidhi N Kaushik |
2020-03-15 | soc/intel/tigerlake: Configure Vmx support using Kconfig | John Zhao |
2020-03-12 | soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table | John Zhao |
2020-03-12 | soc/intel/*/smihandler: Only compile in TCO SMI handler if needed | Patrick Georgi |
2020-03-12 | soc/intel/tigerlake: Configure L1Substates for PCH Root ports | Wonkyu Kim |
2020-03-12 | vboot: remove extraneous vboot_recovery_mode_memory_retrain | Joel Kitching |
2020-03-12 | soc/intel/tigerlake: Enable HDA through dev_enabled | Srinidhi N Kaushik |
2020-03-11 | soc/intel/common/block/smm: add case intrusion to SMI handler | Michael Niewöhner |
2020-03-11 | soc/intel/tigerlake: Save DIMM info by available nodes | Jamie Ryu |
2020-03-11 | soc/intel/tigerlake: Correct FSP log interface | Ronak Kanabar |
2020-03-11 | soc/intel/tigerlake: Fix stale device pointer usage | Karthikeyan Ramasubramanian |
2020-03-11 | soc/intel/common/block: tco: enable intruder SMI if selected | Michael Niewöhner |
2020-03-10 | soc/intel/common: Add more GPIO definition macros | Nico Huber |
2020-03-10 | soc/intel/dnv: Set INT_LINE accouting for PIRQ routing & swizzling | Stephen Douthit |
2020-03-10 | soc/intel/dnv: Add ACPI _PRT methods for virtual root ports | Stephen Douthit |
2020-03-10 | soc/intel/dnv: Fix ACPI reporting of root port interrupt routing | Stephen Douthit |
2020-03-10 | src: Remove unneeded 'include <arch/cache.h>' | Elyes HAOUAS |
2020-03-10 | soc/intel/dnv: Don't clobber SATA_MAP while trying to set mode | Stephen Douthit |
2020-03-10 | soc/intel: fix eist enabling | Matt Delco |
2020-03-10 | soc/intel/xeon-sp,mb/ocp/tiogapass: Don't fake binaries | Nico Huber |
2020-03-10 | soc/intel/tigerlake: Enable Hybrid storage mode | Wonkyu Kim |
2020-03-09 | soc/intel/braswell/chip.h: Include smbios.h for Type9 Entries | Michał Żygowski |
2020-03-07 | soc/intel/tigerlake: Avoid NULL pointer dereference | John Zhao |
2020-03-07 | intel/soc: skl,apl,cnl,icl,tgl: add INTRUDER relevant registers | Michael Niewöhner |
2020-03-07 | intel/soc: skl,apl,cnl,icl,tgl,common: enable TCO SMIs if selected | Michael Niewöhner |
2020-03-07 | soc/intel/common/block/smm: add Kconfig for TCO SMI | Michael Niewöhner |
2020-03-07 | soc/intel/braswell: Generate microcode binaries from tree | Michał Żygowski |
2020-03-06 | soc/intel/tigerlake: Enable CNVi Mode | Srinidhi N Kaushik |
2020-03-06 | soc/intel: Add Intel Xeon Scalable Processor support | Jonathan Zhang |