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The HOB does not move, place its location in .bss.
Change-Id: I2c6dbe4d64138e45fa1dfe7580ffa70d0441bd88
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47294
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The cpu/car code only applies to pre-family-17h CPUs that still use
cache as RAM (CAR) and the PI code only applies to the pre-FSP vendor
code blob binaryPI interface.
Change-Id: I5a13d7e202bb745255fabb46110850c36b07de7a
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47274
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In gpio.c file, we have community group array for each comm,
representing gpio groups within that community. Like there might be
group H,D, VGPIO and C within community 1. Community also may have
some reserved gpio and we also define those in an array which indicates
OS can't use those GPIO (through PAD_BASE_NONE)
Now when we define reserved pads in the middle of actual community
pads, it creates an issue while calculating an offset for GPIO
host own pad register. This is because function actually checks
current gpio index (lets say vgpio_39 in our case) and tries to get
group index from an array which we have defined. If we have defined
reserved gpios in between 2 communities, index calculated will also
account for reserved GPIO and register offset calculation will move
to next set of register (offset 0xC instead of offset 0x8).
Because of this coreboot won't configure HOST_OWN_PAD register correctly
and driver will not be able to get non-SMI interrupts for related gpio.
Align pad group as per EDS and pin-ctrl driver in linux kernel.
Reference: DOC#618876 (EDS volume 2)
BUG=None
BRANCH=None
TEST=VGPIO community index is correctly calculated. Drawlat board
boots fine with this change and warm reset also works.
Change-Id: Id6013914c88c50f4b8c60ca9a9285a8e1b214d11
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Multiple GPIOs were defined as a reserved GPIO in JasperLake. Correcting
this GPIOs with proper name to align with EDS volume 2
Also removing unused GPIOs at the end of community 4 (group E).
Since those reserved GPIOs are at the end of the community, it won't
affect the offset calculations within community. This change will also
help us aligning pad numbering with kernel pin-ctrl drivers too.
Reference: DOC#618876 (EDS volume 2)
BUG=None
BRANCH=None
TEST=Platform boots fine and basic functionality such as SD, Wifi works.
Change-Id: I8326b7181d47a177261656f51602638d8ce80fbb
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47232
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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All wakes by a PCH PCIe root port were lumped under one event source;
this commit splits them up so each root port gets its own ID in the
event log.
BUG=b:172279061
BRANCH=volteer
Change-Id: Icdb10043700c20ddb6ae93747a731005fd233a70
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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All wakes by a PCH PCIe root port were lumped under one event source;
this commit splits them up so each root port gets its own ID in the
event log.
BUG=b:172279061
BRANCH=volteer
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Icebcac3b69c605ecf6df37733b641397ea3c3ad0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Copy lpit.asl to pep.asl to have a clean patch series without moving
files and to be able to keep the replace-patch CB:46471 as small as
possible to avoid confusion.
Change-Id: Ib1c019039ef0c518cf678af6109ba914b7f47bb6
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This change adds two functions that provide an IPC mailbox method via
ACPI for runtime clock configuration.
pmc_acpi_fill_ssdt_ipc_write_method() will provide a method in the SSDT
that can be called by other ACPI devices to send an IPC mailbox command.
This function is exported because some SOCs override the default PMC
device and need to call this function to write the method into the SSDT.
pmc_acpi_set_pci_clock() will call the method defined by the previous
function to enable or disable the PCIe SRCCLK for a specified root port
and clock pin. It can be called by the PCIe root port after turning off
power to the attached device.
BUG=b:160996445
TEST=boot on volteer device and disassemble the SSDT to ensure that this
method exists.
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I95f5a1ba2bc6905e0f8ce0e8b2342ad1287a23a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46259
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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From Tigerlake FSP v3373 onwards vbt binary size changed from 8KiB
to 9KiB. Commit cf5d58328fe004d967466be42de62d6bab4c3133 had changed
the size from 8 to 9 Kib in drivers/gma. This change makes use of
Kconfig option to pick the size for tigerlake.
BUG=b:171401992
BRANCH=none
TEST=build and boot delbin and verify fw screen is loaded
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I21a0bba9ae01bac326f0f931641c98e8d308310f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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InternalGfx isn't used so drop it.
Change-Id: I12f424d8d883e065ef8d007e56a8bff41a7fae53
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Individual drivers check whether the concerned device is enabled before
filling in the SSDT. Move the check before calling acpi_fill_ssdt() and
remove the check in the individual drivers.
BUG=None
TEST=util/abuild/abuild
Change-Id: Ib042bec7e8c68b38fafa60a8e965d781bddcd1f0
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
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Reorder soc_util.c and remove the un-needed #if ENV_RAMSTAGE to match
cpx version in preparation for more de-duplication.
Change-Id: Iab343e903e2478709fe91739c9ca77f587286df7
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Currently, there's no check for the table being programmed. This skips
programming a table if the table size is zero, or the pointer to the
table has been set to NULL.
BUG=None
TEST=Set table pointer to NULL, table doesn't run.
BRANCH=Zork
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I7d09b47e7d619428b64cc0695f220fb64c71ef4c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Expand fam17h to family 17h to make the help text slightly easier to
understand and add family 19h to the description of
SOC_AMD_COMMON_BLOCK_PSP_GEN2.
Change-Id: I9284c9c638e1d217d4605523dde004781f4343f9
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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The patch enables ALC711 Audio codec.
Test=Verified on ADL RVP.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I73f480dad1047cebd7ffc66e0104ff10cacc300b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
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NOC errors detected at runtime in AOP SRAM region
strongly suggested speculative memory accesses were occurring
in memory regions that either don't exist or are device memory
rather than SRAM.
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Change-Id: I6611dc614c80063c7df057b59337417c8f56fd9c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Change-Id: Id4460eb596b080dec1a63a20869182170c3388af
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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The RV1 CPUID is already in the cpu.h file, but was still missing from
the CPU table in cpu.c.
Change-Id: Iad78cbe933b40e946d421e4c93e523f9e31f1089
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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On picasso's psp_verstage, the vboot hash is being calculated by
hardware using relatively expensive system calls. By increasing the
block size, we can save roughly 150ms of boot and S3 resume time.
TEST=Build & boot see that boot time has decreased.
BRANCH=Zork
BUG=b:169217270 - Zork: SHA calculation in vboot takes too long
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I6642073357327811b415dcbcad6930ac6d2598f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46903
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Increasing the vboot hash buffer size greatly speeds up the SHA
calculations. Going from a standard 4k buffer to a 36k buffer
takes ~150ms of the boot and resume time.
TEST=Build & boot see that boot time has decreased.
BRANCH=Zork
BUG=b:169217270 - Zork: SHA calculation in vboot takes too long
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ibca868ad7be639c2a0ca1c4ba6d71123d8b83c92
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46902
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The CPU index wasn't getting updated. Confirm MADT sets IOAPIC and CPU
ID numbers.
Change-Id: I72430cc48f4609ac408e723172ba1ed263cca8e3
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Continue Xeon-SP de-duplication.
Move CPU helper functions from skx/ and cpx soc_util.c to common util.c.
Functions only used by util.c are updated to be static.
The following functions are moved:
int get_threads_per_package(void);
int get_platform_thread_count(void);
const IIO_UDS *get_iio_uds(void);
unsigned int soc_get_num_cpus(void);
void get_core_thread_bits(uint32_t *core_bits, uint32_t *thread_bits);
void get_cpu_info_from_apicid(uint32_t apicid, uint32_t core_bits,
uint32_t thread_bits, uint8_t *package, uint8_t *core, uint8_t *thread);
void xeonsp_init_cpu_config(void);
Change-Id: I118a451b9468459cf2c2194f31da1055e1435ebe
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47170
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Clean up the header includes.
Change-Id: I9f61d1a82b37bc0ed803967dc64decf18f44adc9
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
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The amdfwtool is not available at the beginning of the
building. So it may have error if it is missing.
Change-Id: Id4db70986755cef8e98877c4e92841b25ced5452
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Use command below to change the variable globally.
sed -i "s/\<variable\>/variable_u/g" `grep variable -rl ./ \
--exclude-dir=build --exclude-dir=crossgcc`
BUG=b:171334623
TEST=Build
Change-Id: I056a76663e84ebc940343d64178c18cb20df01a3
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Disable C1 C-state auto demotion to decrease SoC power usage.
When set, processor will conditionally demote C3/C6/C7 requests
to C1 based on uncore auto-demote information.
BUG=b:161215906
TEST=Measure and confirm SoC power usage reduction for key use cases
eg 'Google Meets video call'
Measured on instrumented boards for Volteer EVT and Delbin.
Below measurements for Volteer:
Google meets with 720p w/ auto-demotion w/o auto-demotion
System Power 13.14W 9.4W
SOC Power 7.9W 5.4W
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Signed-off-by: Shweta Malik <shweta.malik@intel.com>
Change-Id: I649cafbaf03917d76521aa5f76ec58d218e1a1b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Since the mainboard Kconfig is sourced before the SoC one, it would
still be possible to override this setting at mainboard level, even
though that shouldn't be needed. The maximum CPU count for Picasso is 8,
since the chips have only up to 4 cores with up to two threads each.
Change-Id: I53449b8fa73c5d13e6ea77bee6eed8896b7d3ec3
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47205
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This removes some boilerplate like starting the console and also adds
a "start of romstage" timestamp.
Change-Id: Ie85df5d244fa37c41f0b3177ca325c607fa54593
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 does not change.
Change-Id: If5f1feb0cd43fe1e0514b4e3fa766da60e2b7603
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46773
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Other southbridges such as Lynx Point do it. This eases merging later.
Change-Id: I10196bbc44ce859c2747755845378351f45944ae
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46766
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 does not change.
Change-Id: I1f41ce943e25dceab79c7d7ee2ed797c392dcd52
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46763
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These are present in common southbridge ACPI code, and also exist on
Broadwell. Thus, add the definitions to align with common ACPI code.
Change-Id: Ib0ad9da80920fe7c70986e541c50f6adccb49d0c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46761
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ifd1fb02497e1d326b6b9c5752f471f52b145a8ef
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46732
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.
Change-Id: I9179c1b449925cc66628fc3266652b8237ab49e5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46759
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Commit 2e1f764 (sb/intel/common/acpi/irqlinks.asl: Add missing IRQs)
added these IRQs for Lynx Point and earlier southbridges. Follow suit
for Broadwell, since it also supports them. Vendor firmware of the Asus
X555LAB laptop also contains these IRQs, as per the disassembled DSDT.
Change-Id: If857352dd25ba61c1f09c1ff4358efafdc3a5c73
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46758
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Drop unnecessary smbus.asl in favor of southbridge common code.
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 does not change.
Change-Id: I13b35d2155a2cede0a56846b8bf8a79d4ebfc7b3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46757
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Two of the PSP mailbox commands are only applicable to the first
generation of PSP mailbox interface.
Change-Id: Ice940ee780c3d96ae1d9ec7ba49ea4add00e8723
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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This reports where TSEG is located and will be used when setting up
SMM.
Change-Id: I9a89cc79b08e2dcf1ffb91aa27d92c387cc93bfd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I43e36f2e736192603be61519d3e185605e81f0e8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: I3a3d187fc24ab752dfe61893c15561a92d009fe2
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46062
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move the global CPPC package \GCPC to the first logical core CP00 and
adapt the reference in the other cores. This is cleaner and avoids
confusion.
Test: dumped SSDT on Supermicro X11SSM-F and verified decompiled version
Change-Id: I40b9fd644622196da434128895eb6fb96fdf254d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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IIO_RESOURCE_INSTANCE is a large struct, so it should be passed as a
constant pointer rather than making a copy.
Found-by: Coverity CID 1432759
Change-Id: Iebbb4d292f4d956e767bda28cbf20b0318586510
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46729
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The CAR set up by FSP-T is at base 0xfe800000 and has a 0x200000 size.
FSP-M seems to have a very large stack usage so it would overflow
other car symbols located below the coreboot stack such as timestamps
and the pre-ram console, which are now fixed.
TEST: boot with ocp/deltalake.
Change-Id: I886f9391ad79fcfa0724109393e3781a08d954b4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46895
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change adds elog.c to smm-y for Tiger lake and Jasper Lake
platforms to enable the logging of wake sources in eventlog for S0ix.
BUG=b:172272078,b:169731044
BRANCH=volteer
TEST=Verified on volteer that wake sources are correctly logged for
S0ix:
8 | 2020-11-02 13:54:27 | S0ix Enter
9 | 2020-11-02 13:54:33 | S0ix Exit
10 | 2020-11-02 13:54:33 | Wake Source | RTC Alarm | 0
11 | 2020-11-02 13:54:49 | S0ix Enter
12 | 2020-11-02 13:54:54 | S0ix Exit
13 | 2020-11-02 13:54:54 | Wake Source | Power Button | 0
14 | 2020-11-02 13:55:04 | S0ix Enter
15 | 2020-11-02 13:55:10 | S0ix Exit
16 | 2020-11-02 13:55:10 | Wake Source | GPE # | 112
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ie1c40dfba6c82ca45a21d35c5a2725e4d30855d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47141
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.
Change-Id: I7f87085c70149d02c544e2d43e1bdb58c7502d6d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46754
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reverts commit 81a4c85acf664156bb68807f681cd40928bf8267.
Reason for revert: Blocks merging Haswell and Broadwell together.
Tested on out-of-tree Acer Aspire E5-573, still boots.
Change-Id: I29c4ad9174ab84c7e9111daa0491ede9e1d639b4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46734
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Fix the asl to use CONFIG_MAX_CPUS to create entries for
multiple cpu uncores. Don't add the RTxx resource entries multiple
times. The function is called for each CPUs.
Change-Id: Ia4eb9716ae4bd72fb4eb98649105be629623cbef
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47060
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Separate the get_stack_for_port into soc specific functions. This
removes a #if in common code.
Change-Id: Ib38a7d66947ded9b56193a9163e5128b2523e99c
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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When asked to place cbmem_top(), FSP does not seem to care about
alignment. It can return an address that is MTRR poison, which will
exhaust all variable MTRRs when trying to set up caching for CBMEM.
This will make memory-mapped flash and TSEG caching fail as well.
Safeguard against this by aligning the region to cache to half of its
size, and move it upwards to compensate. It is assumed that caching
memory above the provided bootloader TOLUM address is inconsequential.
TEST=Boot Purism Librem Mini WHL, observe no MTRR exhaustion error
messages in console. The boot process also feels more fluid.
Change-Id: Ic64fd6d3d9e8ab4c78d68b910a476f9c4eb2d353
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I7adf430e6ce5f78f68a0c73af841fbdc62bb5dc9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47057
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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