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2016-07-08soc/intel/quark: Remove use of PDAT.bin fileLee Leahy
Remove the unused Kconfig values which specify the PDAT file, its location and inclusion into the coreboot file system. Remove the code in romstage which locates the pdat.bin file. TEST=Build and run on Galileo Gen2 Change-Id: I397aa22ada6c073c60485a735d6e2cb42bfd40ab Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15205 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-08soc/intel/apollolake: Include gpio_defs headerHarsha Priya
Add the gpio_defs.h reference in chip.h to enable reef and amenia devicetree.cb to use the definitions from gpio_defs.h. Change-Id: I333d4e810e42309ac76dd90c19f05cf3e3a517b1 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/15550 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-08acpi: Change device properties to work as a treeDuncan Laurie
There is a second ACPI _DSD document from the UEFI Forum that details how _DSD style tables can be nested, creating a tree of similarly formatted tables. This document is linked from acpi_device.h. In order to support this the device property interface needs to be more flexible and build up a tree of properties to write all entries at once instead of writing each entry as it is generated. In the end this is a more flexible solution that can support drivers that need child tables like the DA7219 codec, while only requiring minor changes to the existing drivers that use the device property interface. This was tested on reef (apollolake) and chell (skylake) boards to ensure that there was no change in the generated SSDT AML. Change-Id: Ia22e3a5fd3982ffa7c324bee1a8d190d49f853dd Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15537 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-07soc/intel/apollolake: add LPDDR4 sku selection supportAaron Durbin
Instead of having all the mainboards put similar logic into their own code provide common mechanism for memory SKU selection. A function, meminit_lpddr4_by_sku(), is added that selects the proper configuration based on the SKU id and configuration passed in. LPDDR4 speed as well as DRAM device density configuration is associated for each logical channel per SKU id. BUG=chrome-os-partner:54949 BRANCH=None TEST=Built and used on reef for memory config. Change-Id: Ifc6a734040bb61a58bc3d4c128a6420a71245c6c Signed-off-by: Aaron Durbin <adurbin@chromuim.org> Reviewed-on: https://review.coreboot.org/15559 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-07soc/intel/apollolake: make internal pulls weak for gpio inputsAaron Durbin
The internal pulls for gpio_input_pullup() and gpio_input_pulldown() were using fairly strong pulls. Weaken them so that external pulls can override the internal ones. This matches the current assumptions of lib/gpio.c. BUG=chrome-os-partner:54949 BRANCH=None TEST=Built and used on reef for memory config. Change-Id: Ifda1d04d40141325f78db277eb0bd55574994abf Signed-off-by: Aaron Durbin <adurbin@chromuim.org> Reviewed-on: https://review.coreboot.org/15558 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-07soc: Remove newline from `CHIP_NAME`Paul Menzel
The name must not terminated with a newline character `\n` as it would make it hard to use it strings. So, remove the newline from the two SoCs with it. Change-Id: I7570442b38a455e7c497d7f461c208fb0a88296d Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/15540 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-07tegra124: Build verstage when CHROMEOS is selectedPaul Kocialkowski
This includes the proper Kconfig options (based on the chromium os coreboot configuration) for setting up verstage on tegra124 devices. Change-Id: I4a1976ff684a417cae6fa718ef53cad763cee47d Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/15451 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-07-07intel/fsp_broadwell_de: Do not use hard coded SCI IRQ for ACPIWerner Zeh
The SCI interrupt can be routed to different IRQs using ACPI control register. Instead of using hard coded IRQ9 for ACPI table generation read back the register and return the used IRQ number. This way SCI IRQ can be modified (e.g. for a given mainboard) and ACPI tables will remain consistent. Change-Id: I534fc69eb1df28cd8d733d1ac6b2081d2dcf7511 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15548 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: York Yang <york.yang@intel.com>
2016-07-06PCI: Use PCI_DEVFN macro instead of DEV_FUNCWerner Zeh
There are several different macros available to convert a PCI device and function to a single 8 bit value. One is PCI_DEVFN and is defined in device/pci_def.h. The other is DEV_FUNC and is defined in several intel fsp based chipset implementations. In fsp_broadwell_de DEV_FUNC is even used without being defined at all. This patch unifies the situation so that only PCI_DEVFN is used. Change-Id: Ia1c6d7f3683badc66d15053846936d88aa836632 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15546 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-07-02soc/apollolake: Allow enable/disable of LPSS S0ix from devicetreeSaurabh Satija
Change-Id: Ib7aa1d1b32adcb541a155b8ba2ee011cb5bcf784 Signed-off-by: Saurabh Satija <saurabh.satija@intel.com> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/15055 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-07-02soc/intel/apollolake: Add GPE routing codeShaunak Saha
This patch adds the basic framework for SCI to GPE routing code. BUG = chrome-os-partner:53438 TEST = Toogle pch_sci_l from ec console using gpioset command and see that the sci counter increases in /sys/firmware/acpi/interrupt and also 9 in /proc/interrupts. Change-Id: I3b3198276530bf6513d94e9bea02ab9751212adf Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/15324 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-07-02soc/intel/apollolake: Let CSE know Ring Buffer Protocol is not neededAndrey Petrov
On Apollolake CSE can be used to fetch firmware from boot media. However, when this feature is not used, CSE needs to be explicitly notified of it before memory training is complete. This way it can transition to next state. BUG=chrome-os-partner:53876 TEST=CSE can be power-gated during S0iX. Confirmed with LTB. Change-Id: I5141bff350b6c0bb662424b7b709f0787ec5fd28 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15494 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-02soc/intel/apollolake: Add Audio DSP deviceHarsha Priya
Add the Audio DSP device for apollolake as a PCI driver with a static scan_bus handler so generic devices can be declared under it. This is for devices like the Maxim 98357A which is connected on the I2S bus for data but has no control channel bus and instead just has a GPIO for channel selection and power down control and needs to describe that GPIO connection to the OS via ACPI. Change-Id: Icb97ccf7d6a9034877614d49166bc9e4fe659b12 Signed-off-by: Harsha Priya <harshapriya.n@intel.com> Reviewed-on: https://review.coreboot.org/15528 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-02soc/intel/apollolake: handle p2sb quirksAaron Durbin
The P2SB device is device 0xd and function 0. If hidden that causes the latter pci devices on function >= 1 to not be probed in the kernel. This is also a problem for coreboot if the P2SB device is hidden by FSP. That means the coreboot driver won't be ran. Therefore, provide hide and unhide functions for the P2SB device. The other quirk is to allow the GPIO devices to work correctly. Those devices are ACPI devices. However, their resources are sub-regions within the P2SB BAR. Sadly, linux doesn't handle ACPI devices being children of PCI devices. This leads to resource conflict errors when the P2SB device is visible. For the time being keep the P2SB device hidden, but also ensure the resources it is using are accounted for and reserved. The fallout of that is the PMC and SPI device are no longer probed by the kernel. BUG=chrome-os-partner:53017 TEST=Ensured P2SB device is visible and pci resources are allocated correctly for the devices. Change-Id: I24e59bbde74310e1ce8425b344a3ad0b88702153 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15530 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-02soc/intel/skylake: Add function for gpio_t to ACPI pin translationDuncan Laurie
Add the function defined in gpio.h to translate a gpio_t into a value for use in an ACPI GPIO pin table. For skylake this just returns the gpio_t value as the pins are translated directly and they are all in the same ACPI device. Change-Id: I00fad1cafec2f2d63dce9f7779063be0532649c7 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15520 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-02soc/intel/apollolake: Add function to translate gpio_t into ACPI pinDuncan Laurie
There are four GPIO communities in this SOC and they are implemented as separate ACPI devices. This means the pin number that is used in an ACPI GPIO declaration needs to be relative to the community that the pin resides in. Also select GENERIC_GPIO_LIB in the SOC Kconfig so this function actually gets used. This was tested on the reef mainboard by verifying the output of the SSDT for the Maxim 98357A codec that the assigned GPIO_76 is listed as pin 0x24 which is the value relative to the Northwest community. Change-Id: Iad2ab8eccf4c91185a075ffce8d41c81f06c1113 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15513 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-07-02soc/intel/apollolake: Add support for LPSS I2C driverDuncan Laurie
Support the I2C interfaces on this SOC using the Intel common lpss_i2c driver. The controllers are supported in pre-ram environments by setting a temporary base address in bootblock and in ramstage using the naturally enumerated base address. The base speed of this controller is 133MHz and the SCL/SDA timing values that are reported to the OS are calculated using that clock. This was tested on a google/reef board doing I2C transactions to the trackpad both in verstage and in ramstage. Change-Id: I0a9d62cd1007caa95cdf4754f30c30aaff9f78f9 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15480 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-02soc/intel/apollolake: Add function to translate device into ACPI nameDuncan Laurie
Add support for the soc_acpi_name() handler in the device operations structure to translate a device path into ACPI name. In order to make this more complete add some missing devices in include/soc/pci_devs.h. Change-Id: I517bc86d8d9fe70bfa0fc4eb3828681887239587 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15479 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-01skylake: Generate ACPI timing values for I2C devicesDuncan Laurie
Have the Skylake SOC generate ACPI timing values for the enabled I2C controllers instead of passing it in the DSDT with static timings. The timing values are generated from the controller clock speed and are more accurate than the hardcoded values that were in the ASL which were originally copied from Broadwell where the controller is running at a different clock speed... Additionally it is now possible for a board to override the values using devicetree.cb. If zero is passed in for SCL HCNT or LCNT then the kernel will generate its own timing using the same forumla, but if the SDA hold time value is zero the kernel will NOT generate a correct value and the SDA hold time may be incorrect. This was tested on the Chell platform to ensure all the I2C devices on the board are still operational with these new timing values. Change-Id: I4feb3df9e083592792f8fadd7105e081a984a906 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15291 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-01soc/intel/apollolake: add initial NHLT supportSaurabh Satija
Provide the initial NHLT support for the following hardware: 1. 2 channel digital microphone array 2. Dialog 7219 headset 3. Maxim 98357 speaker amplifiers. The code utilizes the Intel SoC common NHLT support. Change-Id: Ic31e834a08f29c66512a7a63ad7bb35e0374e86a Signed-off-by: Saurabh Satija <saurabh.satija@intel.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15504 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-07-01soc/intel/common: use nvs.h include for nhlt codeAaron Durbin
The nvs.h header is the one which defines global_nvs_t proper. Don't rely on an indirect inclusion. Change-Id: I89d6a73f65e408c73f068b4a35b5efd361a6e5d3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15503 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-07-01soc/intel/apollolake: typedef global_nvs_t for consistencyAaron Durbin
Every other platform has global_nvs_t as a typedef. For some reason apollolake didn't bother following current conventions. Fix this omission to allow for better code sharing and consistency. Change-Id: Id596eed517737759a64ce803c89ea2a05cbe2cce Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15502 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-06-30soc/apollolake: Expose a function to read pmc barShaunak Saha
This patch exposes a function to read pmc bar. PMC bar is read in function read_pmc_mmio_bar which is defined static in file pmutil.c. This patch exposes that functionality to call it from other files. BUG=chrome-os-partner:53438 TEST= Read the PMC bar value properly from outside pmutil file. Change-Id: I26ee13e6ab95d3a8991c7f8ea4b3856ceb015d10 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/15460 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-30fsp_broadwell_de: Enable Super I/O address range decodeWerner Zeh
If there is an external 16550 like UART, one needs to enable the appropriate address ranges before console_init() is called so that the init sequence can reach the external UART. Otherwise the UART will only start working in ramstage and will produce unreadable characters in romstage due to the lack of initialization. Tested-on: Siemens MC_BDX1 Change-Id: Iafc5b5b6df14916c5ed778928521d4a8f539cf46 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15495 Tested-by: build bot (Jenkins) Reviewed-by: York Yang <york.yang@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-30soc/intel/apollolake: fix space indention in pm.hAaron Durbin
More spaces missed in review. Change-Id: I842da05ca6ad4f2c13d2d42433e41da57ccf7f96 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15500 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-06-29soc/intel/{common,skylake}: provide common NHLT SoC supportAaron Durbin
The nhlt_soc_serialize() and nhlt_soc_serialize_oem_overrides() functions should be able to be leveraged on all Intel SoCs which support NHLT. Therefore provide that functionality and make skylake use it. Change-Id: Ib5535cc874f2680ec22554cecaf97b09753cacd0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15490 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-06-29soc/intel/skylake: refactor nhlt supportAaron Durbin
Utilize the new NHLT helper functions by driving the NHLT endpoints through data descriptors. Change-Id: I80838214d3615b83d4939ec2d96a4fd7050d5920 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15488 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-29soc/intel/skylake: fix nhlt/ssm4567.c indentionAaron Durbin
Whitespace fix for improper space usage for indention. Change-Id: Ia6470bf152c57786d2d7f3d35bbf0609a2ee3ba2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15487 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-06-29soc/intel/apollolake: Change PCI macros to match SkylakeAndrey Petrov
Change PCI macros in such a way they can be transparently used across romstage and ramstage. Change-Id: Idc708c1990f2fc1d941bb82efcb0a697524f2eca Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15483 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-29soc/intel/apollolake: Update Upd header files for FSP Label 143_10Brandon Breitenstein
New UPDs added to header files as well as many comment fixes. Memory infor is now defined in FspmUpd.h and added ability to skip CSE RBP for coreboot. Removes some UPDs that are no longer available from source. BUG=chrome-os-partner:54677 BRANCH=none TEST=built and tested with FSP 143_10 version Change-Id: I7e1f531ebbe343b45151a265ac715ae74aeffcad Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/15459 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-29intel romstage: Use run_ramstage()Kyösti Mälkki
Change-Id: I22a33e6027a4e807f7157a0dfafbd6377bc1285d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15461 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-28soc/intel/apollolake: Add NHLT table region to ACPI global nvsSaurabh Satija
Add address and length of NHLT table in ACPI. Change-Id: Ic0959a8aae18d54e10e3fcd95bfc98a6b6e0385a Signed-off-by: Saurabh Satija <saurabh.satija@intel.com> Reviewed-on: https://review.coreboot.org/15025 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-28apollolake: Add ACPI device for audio controllerSaurabh Satija
Add the audio controller device to ACPI and define the _DSM handler to return the address of the NHLT table, if set in NVS. Change-Id: I619dbfb562b94255e42a3e5d5a3926c28b14db3e Signed-off-by: Saurabh Satija <saurabh.satija@intel.com> Reviewed-on: https://review.coreboot.org/15026 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins)
2016-06-28tegra124: Actually align the framebuffer's bytes-per-line to 32Paul Kocialkowski
The previous change with that intent aligned the framebuffer's bytes-per-line to 64 instead of 32: commit 8957dd6b52919ed634aa502dfd5b6316a6e6e055 Author: Paul Kocialkowski <contact@paulk.fr> Date: Sun May 1 18:38:04 2016 +0200 tegra124: Align the framebuffer's bytes-per-line to 32 Change-Id: I88bba2ff355a51d42cab6a869ec1e9c534160b9c Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/14816 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-06-28soc/apollolake: Populate fields in FADT to enable\disable SCIHannah Williams
This will allow kernel to trigger a APM SMI to enable\disable SCI Change-Id: I1be79b7a3082c23fbaf204eff55360c46458e325 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/15347 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-27soc/intel/apollolake: add code to disable unused deviceJagadish Krishnamoorthy
Parse the devicetree and pass the unused device to fsp for disabling the device function. BRANCH=none BUG=chrome-os-partner:54325 TEST=device off in devicetree should disable the device. Change-Id: I784b72a43fda13aa17634bf680205ab2d36e8d09 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://review.coreboot.org/15337 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-27intel/apollolake: Set sleep type to S5 on vboot reboot requestFurquan Shaikh
Add support for vboot_platform_prepare_reboot which is called whenever vboot requests reboot of the platform. SLP_TYPE needs to be set to S5 in such conditions since the platform would no longer be in a resuming state after reset. Change-Id: I01392bfda90c9274cd52c1004555d250b1d539b7 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15340 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-24rk3399: clean up sdram controller initialization codeVadim Bendebury
This is a purely cosmetic change replacing some of the more prominent copy and paste sections of the code with compressed versions of the same. BRANCH=none BUG=none TEST=with the rest of the patches applied stressapptest still runs for an hour on both Kevin and Gru. Change-Id: I492e1898e312473d07d9e5eceb3e3e10b48ee35f Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: eb8043f96457d090dbbee57097bc1d685e7d32d2 Original-Change-Id: I362e0e261209ae4d4890ecb0e08bb1956c172ffd Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/353774 Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org> Reviewed-on: https://review.coreboot.org/15308 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-24region: Add writeat and eraseat supportAntonello Dettori
Implement writeat and eraseat support into the region_device_ops struct. Change-Id: Iac2cf32e523d2f19ee9e5feefe1fba8c68982f3d Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/15318 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-24soc/apollolake: Clear SLP_TYP in PM1_CNTHannah Williams
Change-Id: Id49319ec6b52648b03eaeddfdd1580dd82110fb9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/15336 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-24soc/intel/apollolake: Add handling of global reset in FspNotify stageAndrey Petrov
Call basic FSP reset handling in FspNotify stage. Handling of reset requests for other stages need to be implemented as well. BUG=chrome-os-partner:54149 BRANCH=none TEST=with FSP that returns reset codes, do cold boot, check that reboot sequence occurs properly. Change-Id: I55542aa37e60edb17ca24ac358b61df72679b83e Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15280 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-24soc/intel/apollolake: Implement global reset handlingAndrey Petrov
Global reset enable bit is not cleared on reset. Therefore, clear the bit early. Lock down 0xcf9 so that payload/OS can't issue global reset. BUG=chrome-os-partner:54149 BRANCH=none TEST=none Change-Id: I3ddf6dd82429b725c818bcd96e163d2ca0acd308 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15199 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-24soc/intel/apollolake: Move PMC BAR setup to bootblockAndrey Petrov
Some features of PMC needs to be accessed before romstage. Hence, move PMC BARs setup into bootblock. BUG=chrome-os-partner:54149 BRANCH=none TEST=none Change-Id: I14493498314ef1a4ce383e192edccf65fed2d2cb Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15332 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-24soc/intel/apollolake: Add utility functions for global resetAndrey Petrov
Apollolake defines Global Reset where Host, TXE and PMC are reset. During boot we may need to trigger a global reset as part of platform initialization (or for error handling). Add functions to trigger global reset, enable/disable it and lock global reset bit. BUG=chrome-os-partner:54149 BRANCH=none TEST=none Change-Id: I84296cd1560a0740f33ef6b488f15f99d397998d Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15198 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-24Revert "intel/apollolake: Use custom reset calls"Andrey Petrov
Looks like we need to do real cold reset in some FSP flows, so reverting this. This reverts commit 6f762171de4b8514fddd430052cbf24524e09e5d. Change-Id: Ie948d264c4e2572dab26fdb9462905247a168177 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15331 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-24soc/intel/apollolake: Include _PTS, _WAK and _SWSHannah Williams
Change-Id: I3400611095978421c7b35a7ea9c68b8571942ae9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/15138 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-06-23intel/apollolake: Enable prefetching and caching for BIOS readsFurquan Shaikh
Change-Id: I6afcc17ec8511d3fd4c1ac3b15d523d9b6752120 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15321 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-23rockchip/rk3399: fix sdram training issueLin Huang
After write leveling for all ranks, check the PHY_CLK_WRDQS_SLAVE_DELAY result, if the two ranks in one slice both meet (0x200-PHY_CLK_WRDQS_SLAVE_DELAY < 0x20) or (0x200-PHY_CLK_WRDQS_SLAVE > 0x1E0), enable PHY_WRLVL_EARLY_FORCE_ZERO for this slice, and trigger write leveling again. BRANCH=none BUG=chrome-os-partner:54144 TEST=run "stressapptest -M 1024 -s 1000" and pass Change-Id: I1a0e4e888eb62b5fae5b5e5437a385e8660a246d Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 717cbac97b2045f2934e99859ce405aa3637b1c4 Original-Change-Id: Ic0d7c59404e870a7108ed64bbf3215fcc2d0973e Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/351825 Reviewed-on: https://review.coreboot.org/15300 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-23rockchip/rk3399: Clean up voltage rail settingsLin Huang
The CENTER LOGIC should always be 0.9V and can not be adjusted, so use duty_ns = 2860 to correct CENTER LOGIC to 0.9V. And now DDR seems to run stable at 800MHz on the gru board. BRANCH=none BUG=chrome-os-partner:54144, chrome-os-partner:53208 TEST=run "stressapptest -M 1024 -s 1000" and pass Change-Id: Ia900e248c10ddd0ab630446a324cc0446c0fa49b Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: f4fb1cefb59ac4099cef8b32a68ed9222e708478 Original-Change-Id: I2238da6c17908d09bc284b321d796901317ed9ef Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/352772 Reviewed-on: https://review.coreboot.org/15297 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-23rk3399: add definition for SP0 iomuxVadim Bendebury
This register is described in the TRM in section called GRF_GPIO3D_IOMUX. Added definitions allow to configure the SPI0 interface. BRANCH=none BUG=chrome-os-partner:50645, chrome-os-partner:51537 TEST=with the rest of the patches applied it is possible to communicate over SPI0 Change-Id: Ieee3fcae6095020042b02673c7d863f398ed2eb4 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 8f155e3b47c9f44ad4e5a2513916572e7d5ec0ab Original-Change-Id: Iea92971b0520dc4549cd0fd263dcb2098f80f6d6 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/349851 Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/15295 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
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