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2020-06-02soc/intel/xeon_sp/skx/soc_util.c: Remove unused <cpu/cpu.h>Elyes HAOUAS
Change-Id: I6dd004b417c27ff0b9f7e55557a9670f927d425c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-02soc/intel/*/bootblock/cpu.c: Drop unused includesElyes HAOUAS
Change-Id: Ide01a922d7d8e500f9a0b507544010706661d7de Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40690 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02{icelake,jasperlake,skylake,tigerlake}/bootblock.c: Clean up includesElyes HAOUAS
Drop unused includes and add missing <intelblocks/systemagent.h>. Change-Id: I06c8b2bf65283c3c1fcd25fdaae298b82fc0e09c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-06-02src: Remove unused '#include <timer.h>'Elyes HAOUAS
Change-Id: I57e064d26b215743a1cb06bb6605fc4fe1160876 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41491 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02src: Remove unused '#include <cpu/x86/lapic.h>'Elyes HAOUAS
Also, replace 'lapic.h' by 'lapic_def.h' in 'soc/intel/braswell/northcluster.c'. Change-Id: I71cff43d53660dc1e5a760ac3034bcf75f93c6e7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41489 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02soc/intel/xeon_sp: Early programming of ACPI barRocky Phagura
ACPI bar was not programmed previously for which is needed to enable SMI's and to check SMI status registers. The architecture of Lewisburg PCH is very similar to SunrisePoint PCH thus we can use code from soc/intel/skylake. TEST=build for Tiogapass and check ACPI base. Log message will now show pmbase=501 (bit 0 is enable) instead of 0. Check by reading and writing to io port 0x500. Change-Id: If5a0c4daabf5c35dc2852434fe46712ac9b06379 Signed-off-by: Rocky Phagura <rphagura@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41680 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-06-02soc/intel/xeon_sp/skx: Let iasl automatically resolve _PRT package sizeArthur Heymans
BUILD_TIMELESS=1 with ocp/tiogapass results in identical binaries. Change-Id: Iff97f3cc0ce800036be32b2758c60e4b7ac39fe9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41529 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-06-02soc/intel/denverton_ns: Fix 16-bit read/write PCI_COMMAND registerElyes HAOUAS
Change-Id: I23ca0c50b0b3c71710173b84d98c2e170ed3e45b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40842 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: David Guckian Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-01soc/intel/common: Trigger recovery mode for CSE Lite SKU run time errorsSridhar Siricilla
Implement triggering recovery mode for CSE Lite SKU runtime errors. Also, define recovery subcodes for various possible Lite SKU runtime errors. BUG=b:153520354 TEST=Verified on hatch Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Ib7744fc4fd0e41804d9b45079bf706b300220c62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-01soc/intel/common/block: Remove unused headersAngel Pons
Change-Id: I8877a70661cacc57ea893da172d9a4b6d19ba06a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-31soc/intel/tigerlake/acpi: Update pch_hda.asl to ASL2.0 syntaxVenkata Krishna Nimmagadda
This change updates pch_hda.asl to use ASL2.0 syntax. This increases the readability of the ASL code. BUG=none BRANCH=none TEST="BUILD for Volteer" Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com> Change-Id: Ia2bab6dcbac9eae76ac4258c44bb19425c8b5c80 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-05-31soc/intel/tigerlake/acpi: Update camera_clock_ctl.asl to ASL2.0Venkata Krishna Nimmagadda
This change updates camera_clock_ctl.asl to use ASL2.0 syntax. This increases the readability of the ASL code. BUG=none BRANCH=none TEST="BUILD for volteer" Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com> Change-Id: I6370e4b268331bfba5bc0392f27c560836b6ea72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41798 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-05-30soc/intel/tigerlake: Configure TcssDma0En and TcssDma1EnJohn Zhao
Determine the TcssDma0 and TcssDma1 enabling based on TBT DMA controllers setting. BUG=:b:146624360 TEST=Booted on Volteer and verified TcssDma0 and TcssDma1 enabling. lspci shows TcssDma0(0d.2) and TcssDma1(0d.3). Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I61ac4131481374e9a2a34d1a30f822046c3897fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/41812 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-29soc/amd/picasso: Enable FSP compressionFurquan Shaikh
This change enables LZMA compression for both FSP-M and FSP-S. This results in significant savings in the FSP size in each CBFS: cbfstool firmware/image-trembyle.bin print -r COREBOOT | grep fsp fspm.bin 0x9cdc0 fsp 132404 LZMA (720896 decompressed) fsps.bin 0xbdfc0 fsp 86146 LZMA (327680 decompressed) LZ4 works too, but the savings are smaller as compared to LZMA: cbfstool firmware/image-trembyle.bin print -r COREBOOT | grep fsp fspm.bin 0x9cdc0 fsp 189530 LZ4 (720896 decompressed) fsps.bin 0xcbfc0 fsp 118952 LZ4 (327680 decompressed) BUG=b:155322763,b:150746858,b:152909132 TEST=Verified that Trembyle boots to OS. No FSP-M or FSP-S errors in boot logs. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ie5e4d58e671e936aa525d3000f890e9e5ae45ec3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-05-29soc/amd/picasso: Relocate FSP-M to address in DRAMFurquan Shaikh
On Picasso, DRAM is up by the time FSP-M runs. This change relocates FSP-M binary to a specific address (0x90000000) in DRAM. Currently, this address is randomly chosen to ensure it does not overlap any of the other stages. Once we have a unified memory map set up for Picasso, this address can be updated along with it. BUG=b:155322763,b:150746858,b:152909132 Change-Id: I1a49765f00de9f97fa3dbd5bc288a3ed0d7087f6 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41828 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28soc/intel/tigerlake: Implement soc_get_pmc_mux_device()Tim Wawrzynczak
The ChromeOS EC is adding new entries to its USBC.CONx devices (see later patch), and it needs to get access to the PMC.MUX device so that its ACPI path can be retrieved. This provides a weak function to return NULL for all Intel SoCs except for Tiger Lake, which locates the device if it is found in the devicetree. Change-Id: I3fe3ef25e9fac8748142f5b1bd870c9bc70b97ff Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40948 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28soc/amd/picasso/soc_util: add comment on socket detection problemsFelix Held
At least some Pollock engineering samples return FP5 socket type while they are in fact FT5 socket type. Change-Id: I06a19c19374532bfb367fc15c734707d8c7f65a3 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41796 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28soc/amd/picasso/soc_util: remove unused functionsFelix Held
soc_is_pollock() and soc_is_picasso() aren't used by any mainboard or soc code. The same fuctionality is still provided by get_soc_type(). Change-Id: I046b4925bfeb4b31d11e2548ac87b7bbca0f6475 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41795 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28soc/intel/tigerlake: Generate PMC ACPI device at runtimeTim Wawrzynczak
In an attempt to help reduce the amount of static ASL files that are littered throughout the codebase, pmc.asl was converted to runtime SSDT generation instead. If future SoCs reuse the same PMC, then this function can be moved to soc/intel/common/block/pmc for example. TEST=Verified the following was in the decompiled SSDT: Scope (\_SB.PCI0) { Device (PMC) { Name (_HID, "INTC1026") // _HID: Hardware ID Name (_DDN, "Intel(R) Tiger Lake IPC Controller") Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xFE000000, // Address Base 0x00010000, // Address Length ) }) } } Also the following found in linux's /var/log/messages: "acpi INTC1026:00: GPIO: looking up 0 in _CRS", indicating the PMC ACPI device was found and its _CRS was locatable. Change-Id: I665c873d8a80bd503acc4a9f0241c7a6ea425e16 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/41408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-05-28soc/intel/jasperlake: Disable PAVP UPDRonak Kanabar
This patch will disable PAVP UPD, which is by default enabled in FSP. BUG=b:155595624 BRANCH=None TEST=Build, boot JSLRVP, Verified UPD values from FSP log Change-Id: I8e103ad11ae6ffa6b9efe4bf249bbe344bc10a30 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41763 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28soc/intel/jasperlake: Correct GPIO community PID configurationAamir Bohra
Current implementation returns the incorrect GPIO community PID. The GPIO community index 3 should return PID for COMM_4 and index 4 should return PID for COMM_5. TEST=Verify GPIO PM bits are correctly set through MS0x ACPI method. Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Change-Id: I3da4945e93605a297baff076295433164fdf613d Reviewed-on: https://review.coreboot.org/c/coreboot/+/41721 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28soc/intel/tigerlake: Configure THCWonkyu Kim
Enable/Disable THCx though devicetree BUG=None BRANCH=None TEST=Boot and check FSP log for THC setting Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: If7683969161be67f68f441c28c80503de39079b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41571 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28soc/intel/tigerlake: Correct GPIO community PID configurationEric Lai
Current implementation returns the incorrect GPIO community PID. The GPIO community index 3 should return PID for COMM_4 and index 4 should return PID for COMM_5. TEST=Verify PCR port id is correct for each community. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I5dc48e5b31f43853b3a613c17f13f7df71f1fbfa Reviewed-on: https://review.coreboot.org/c/coreboot/+/41725 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28Remove new additions of "this file is part of" linesElyes HAOUAS
Change-Id: I6c69dcad82ee217ed4760dea1792dd1a6612cd8b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-05-28soc/sifive/fu540: Add chip_operations stubKyösti Mälkki
Change-Id: If06695745bb72f883314e5514c616223b0210a2f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Philipp Hug <philipp@hug.cx>
2020-05-28soc/ucb/riscv: Add chip_operations stubKyösti Mälkki
Change-Id: Ie4f70429c516fff613d372fec7c1c955645f1c6d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Philipp Hug <philipp@hug.cx>
2020-05-28soc/intel/xeon_sp/skx: Remove invalid declarationKyösti Mälkki
The declaration is autogenerated inside static.c file from the pathname. The declaration here also lacked _skx_ part from the name. Change-Id: I3adce9147e9376f6d73e410fdd4c0ee800178b58 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41710 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-28soc/intel/xeon_sp/cpx: Remove redundant declarationKyösti Mälkki
The declaration is autogenerated inside static.c file from the pathname. Change-Id: I6eda101a69522d6d526da7c174aa3085ca0fb221 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-28soc/intel/common: Improve Type16 SMBIOS tablesPatrick Rudolph
Use CAPID0_A to provide information closer to reality. * Correctly advertise ECC support, max DIMM count and max capacity * CAPID0_A hasn't changed since SNB, but most EDS mark the bits as reserved even though they are still used by FSP. * Assume the same bits for Tiger Lake as for Ice Lake * Assume the same bits for Skylake as for Coffee Lake * Add CAPID0_A to Icelake headers The lastest complete documentation can be found in Document: 341078-002. Change-Id: I0d8fbb512fccbd99a6cfdacadc496d8266ae4cc7 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-05-28soc/intel/jasperlake: Use coreboot lock down configAamir Bohra
Allow lockdown configuration from using CHIPSET_LOCKDOWN_COREBOOT config. TEST=Build and boot waddledoo board Change-Id: I3abaa737580ef45b98cabfa23edd84162037dd70 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41534 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-27soc/amd/picasso/smu: only print time for actual command executionFelix Held
When waiting for the SMU to be ready to accept a new command, the time spent waiting shouldn't be printed as command execution time. Also fix the time unit in the print statement. Change-Id: I6b97b11cd9efae7029779ee2096d4f2224cecd72 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-05-27soc/intel/gma: Implement fsp_soc_get_igd_bar() in common codeNico Huber
`fsp/util.h` draws incompatible UDK headers in. Hence, we have to declare it locally again. Change-Id: Iaa5981088eeb5c36f765d6332ae47a38a6a4c875 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40729 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-27soc/intel/gma: Move DDI-A 4-lane config to common codeNico Huber
Change-Id: I0572dbbfb61e5e0129fe6a3a1b5894145d74fd0d Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40728 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-27intel/gma: Only enable bus mastering if we are going to use itNico Huber
Also fix wrong 32-bit writes. Change-Id: Ib038f0cd558223536da08ba2264774db11cd8357 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40727 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-27intel/gma: Don't bluntly enable I/ONico Huber
The allocator should take care of this. Change-Id: I4ec88ebe23b4dcab069f764decc8b9b0c6e6a142 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40726 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-27soc/intel/gma: Move display and opregion init to common codeNico Huber
Change-Id: I359b529df44db7d63c5a7922cb1ebd8e130d0c43 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40725 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-27drivers/intel/gma: Move IGD OpRegion to CBMEMNico Huber
It never was in GNVS, it never belonged among the ACPI tables. Having it in CBMEM, makes it easy to look the location up on resume, and saves us additional boilerplate. TEST=Booted Linux on Lenovo/X201s, confirmed ASLS is set and intel_backlight + acpi_video synchronize, both before and after suspend. Change-Id: I5fdd6634e4a671a85b1df8bc9815296ff42edf29 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40724 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-27soc/amd/picasso: Use SMU to put system into S3Marshall Dawson
Send a message to the SMU to turn off the system power. SMU will take the proper final steps based on PmControl[SlpTyp]. BUG=b:153264473 TEST=verify system can enter S3 Change-Id: I3c0d98110c12963aa6fef5d176fd9acaa7ed9f26 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://chromium-review.googlesource.com/2140471 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41626 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-27soc/amd/picasso: Add generic SMU service requestMarshall Dawson
Add a new feature that allows messages to be sent to the SMU. The offsets of the PCI config index/data indirect registers have been documented for prior generation devices. The index/data pair is used to access a command register, a response, and six argument values. BUG=b:153264473 TEST=Verify service can be used to take the system into S3 Change-Id: Ide431aa976cb2f8bdc248cb08aa0724a9596ac5a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://chromium-review.googlesource.com/2161796 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-05-27soc/amd/picasso/Makefile: Change APCB_magic.bin locationRaul E Rangel
The APCB_magic.bin lives in amd_blobs, not blobs. BUG=b:157140753 TEST=Boot trembyle to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib082a8e7fc631ca7145b0b77e49ea0cbf99dff41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41734 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-27soc/amd/picasso: add and use CPUIDs for older steppingsFelix Held
Change-Id: Ibe768ef7cd714c17fd5a296d9a3e5f963ae0ef01 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41641 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-27soc/amd/picasso: rewrite soc_utilFelix Held
This adds proper RV2 silicon and Dali SKU detection using both CPUID information and some bits from silicon_id in the Picasso misc data HOB that FSP-M stores in memory. BUG=b:153779573 Change-Id: I589be3bdac4b94785e6ecacf55235be4ad5673d9 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41630 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-05-26soc/amd/picasso: Use C00n for CPU ACPI stringMarshall Dawson
Match the path generated by AGESA. Add more PPKG packages. TEST=Verify that "\_PR.C00n" AE_NOT_FOUND errors go away BUG=b:145013057 Change-Id: I82587648d37c0be885991f2e5741d9f874d6a2eb Signed-off-by: Marshall Dawson <marshall.dawson@amd.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/1937788 Reviewed-by: Martin Roth <martinroth@chromium.org> Commit-Queue: Martin Roth <martinroth@chromium.org> Tested-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-05-26soc/intel/xeon_sp: select UDK_2017_bindingJonathan Zhang
Select UDK_2017_BINDING instead of UDK_2015_BIDING. Otherwise there is build error when turning on FSP debugging. Remove duplicate configs from SKX-SP and CPX-SP directories, to keep the configs at SoC family level. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I6b25bf25dcb57937e2d9fec54eeb7951b0ee4b2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/41573 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-05-26soc/intel/tigerlake: Remove MIPI clock setting from devicetreeSrinidhi N Kaushik
In Tiger Lake we have support for enabling MIPI clocks at runtime in ACPI. Hence remove setting pch_islclk from devcietree and chip.h. Also update functions which reference pch_isclk. BUG=b:148884060 Branch=None Test=build and boot volteer and verify camera functionality Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I6b3399172c43b4afa4267873ddd8ccf8d417ca16 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41570 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-26soc/intel/tigerlake: Delete unused configurationWonkyu Kim
Delete below configuration - Heci3Enabled: deprecated, see https://review.coreboot.org/cgit/coreboot.git/tree/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h#n442 - PchIshEnable: don't need as it's handled by devicetree dev on/off, see https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/tigerlake/romstage/fsp_params.c#n87 BUG:b:151166877 BRANCH=none TEST=Build and boot to OS Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: If96cc7db7118dd6c2ac02aab3bb0c96763ffc722 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-05-26soc/intel/tigerlake: Disable VMDWonkyu Kim
It's already disabled by FSP default but disable VMD by devicetree to remove dependency with FSP default setting. BUG=None Branch=None Test=Build TGLRVP and boot up and check FSP log for checking VMD is disabled. Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ief81fe481b94abed9754881cf1f454999fafa52e Reviewed-on: https://review.coreboot.org/c/coreboot/+/41061 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-26apollolake: update processor power limits configurationSumeet R Pawnikar
Update processor power limit configuration parameters based on common code base support for Intel Apollo Lake SoC based platforms. BRANCH=None BUG=None TEST=Built and tested on octopus system Change-Id: I609744d165a53c8f91e42a67da1b972de00076a5 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41233 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-26soc/intel/tigerlake: Add FSP UPD D3HotEnable and D3ColdEnableJohn Zhao
This adds FSP UPD D3HotEnable and D3ColdEnable for configuration. D3Hot low power mode support is for TCSS xhci, xdci, TBT PCIe root ports and DMA controllers. D3Cold is lower mode for TBT PCIe root ports and DMA controllers with D3Hot->D3Cold transition. BUG=:b:146624360 TEST=Built and booted on Volteer. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I6782cde6a1bfe13f46e75db8c85537c6d62f5d41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-05-26soc/intel/skylake/acpi/smbus.asl: Fix typo in commentElyes HAOUAS
Change-Id: I2d0c90afe8acf8405da2cb6444e47dc98ad8cc9b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40691 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-08 15:41:44 +0000