coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2020-08-08	soc/intel/skylake: Enable CIO depending on devicetree configuration	Felix Singer
2020-08-08	soc/intel/skylake: Enable SA IMGU depending on devicetree configuration	Felix Singer
2020-08-08	soc/intel/skylake: Add IMGU definitions to pci_devs.h	Felix Singer
2020-08-08	soc/intel/skylake: Enable SDXC depending on devicetree configuration	Felix Singer
2020-08-08	soc/mediatek/mt8192: Add initial config for new ARMv8 device MT8192	CK Hu
2020-08-07	soc/intel/skylake: Enable thermal subsystem depending on devicetree	Felix Singer
2020-08-07	soc/intel/skylake: Add SA thermal subsystem definitions to pci_devs.h	Felix Singer
2020-08-07	soc/intel/cnl: Set Heci1Disable depending on devicetree config	Felix Singer
2020-08-07	soc/amd/picasso/acpi: remove AOAC device enables from global NVS	Felix Held
2020-08-07	xeon_sp/cpx: Enable HWP Intel Speed Shift	Johnny Lin
2020-08-07	soc/intel/broadwell/iobp: Log success in `pch_iobp_write()`	Angel Pons
2020-08-07	soc/intel/common: Log CSE FW Status Registers before triggering recovery	Sridhar Siricilla
2020-08-07	soc/intel/{cnl,icl,jsl,tgl}: Use Bus Master for setting up PWRMBASE	Subrata Banik
2020-08-07	src/soc/intel/icelake: Allow option to use USE_INTEL_FSP_MP_INIT	Subrata Banik
2020-08-06	soc/intel/tigerlake: add common routine for DDR init	Nick Vaccaro
2020-08-06	soc/intel/common/block/cpu: Refactor init_cpus function	Subrata Banik
2020-08-06	soc/mediatek/mt8183: Set MMU default map length to 8GB befor mem init	Huayang Duan
2020-08-06	soc/mediatek/mt8183: Add ddr geometry to support 6GB, 8GB DDR bootup	Huayang Duan
2020-08-06	soc/mediatek/mt8183: Adjust tRFCab and tRFCpb by the density value	Huayang Duan
2020-08-06	soc/mediatek/mt8183: Add missing register settings for channels	Huayang Duan
2020-08-05	{sb,soc}/intel/*/acpi/lpc.asl: Drop commented-out code	Angel Pons
2020-08-05	{nb,soc}/intel: Use get_current_microcode_rev() for ucode version	Subrata Banik
2020-08-05	mb/google/zork: keep the c-state IO base address alignment	Chris Wang
2020-08-05	src: Use space after 'if', 'for'	Elyes HAOUAS
2020-08-05	src/soc/intel/common: Make top_of_ram till TOLUD region mmio_resource	Subrata Banik
2020-08-05	soc/intel/common: Include Alder Lake device IDs	Subrata Banik
2020-08-04	soc/intel/skylake: Add RMRRs after all DRHDs	Angel Pons
2020-08-04	soc/intel/broadwell: Add RMRRs after all DRHDs	Angel Pons
2020-08-04	soc/intel/apollolake/acpi.c: Add RMRRs after all DRHDs	Angel Pons
2020-08-04	soc/amd/picasso/acpi: clean up global NVS	Felix Held
2020-08-04	soc/intel/baytrail: Factor out `acpi_fill_madt()`	Angel Pons
2020-08-03	soc/amd/picasso: set is_rv to 1 for RV family	Akshu Agrawal
2020-08-03	soc/intel/baytrail: Add MRC SMBus workaround	Mate Kukri
2020-08-03	soc/intel/xeon_sp/cpx: configure STACK_SIZE	Jonathan Zhang
2020-08-03	soc/intel/xeon_sp/cpx: enable PLATFORM_USES_FSP2_2	Jonathan Zhang
2020-08-03	src/soc/intel/jasperlake: Update SD card ACPI device	Aamir Bohra
2020-08-03	Change all assert(0) to BUG()	Julius Werner
2020-08-03	qualcomm/sc7180: Fix TLMM assignments for GPIOs 29, 31 and 32	Julius Werner
2020-08-03	soc/intel/tigerlake: Invoke PCIe root port swapping	Caveh Jalali
2020-08-02	soc/intel/baytrail/northcluster.c: Clean up comments	Angel Pons
2020-08-02	soc/intel/baytrail/sata.c: Fix SATA init sequence	Angel Pons
2020-08-02	soc/intel/baytrail: Add native refcode replacement	Mate Kukri
2020-08-02	soc/intel/baytrail/northcluster.c: Rename variable	Angel Pons
2020-08-02	soc/intel/baytrail/northcluster.c: Tidy up long lines	Angel Pons
2020-08-02	soc/intel/braswell/northcluster.c: Tidy up long lines	Angel Pons
2020-08-02	soc/intel/braswell/northcluster.c: Rename macro	Angel Pons
2020-08-01	soc/intel/{icl,jsl,tgl}: Remove SkipMpInit UPD as deprecated	Subrata Banik
2020-07-31	soc/intel/cannonlake: Fix DMAR when no iGPU is present	Patrick Rudolph
2020-07-31	soc/intel/xeon_sp/cpx: configure DIMM_MAX and DIMM_SPD_SIZE	Jonathan Zhang
2020-07-30	smbios: Fix type 17 for Windows 10	Patrick Rudolph