coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2017-11-14	soc/amd/stoneyridge: Remove direct AGESA header includes	Martin Roth
2017-11-14	soc/amd/common: Remove direct AGESA header includes	Martin Roth
2017-11-14	AMD Stoney Ridge: Add agesa_headers.h	Martin Roth
2017-11-14	amd/common/spi: Update flash driver usage	Marshall Dawson
2017-11-14	soc/amd/stoneyridge: Load SMU fimware using PSP	Marshall Dawson
2017-11-14	amd/stoneyridge: Add generic IMC sleep and wakeup	Marshall Dawson
2017-11-14	amd/stoneyridge: Replace BIT(n) in southbridge	Marshall Dawson
2017-11-14	amd/stoneyridge: Define bits for AcpiConfig	Marshall Dawson
2017-11-13	soc/intel/common: Add error print in common i2c	Lijian Zhao
2017-11-13	soc/intel/cannonlake: Define default LPSS clock	Lijian Zhao
2017-11-13	soc/amd/stoneyridge: Add CPU PPKG ASL	Marc Jones
2017-11-13	soc/amd/stoneyridge: Add GNVS variables for thermal control	Marc Jones
2017-11-13	soc/amd/stoneyridge: Fix DRAM clear check	Marshall Dawson
2017-11-11	soc/intel/apollolake: Make use of Intel SPI common block	Subrata Banik
2017-11-11	soc/intel/apollolake: Add support for SPI device	Subrata Banik
2017-11-11	soc/intel/cannonlake: Make use of Intel SPI common block	Subrata Banik
2017-11-11	soc/intel/skylake: Make use of Intel SPI common block	Subrata Banik
2017-11-11	soc/intel/{cannonlake,skylake}: Add _soc_ prefix in spi soc routine	Subrata Banik
2017-11-11	soc/intel/common/block: Add Intel common SPI support	Subrata Banik
2017-11-10	soc/amd/stoneyridge: Add UMA settings to devicetree	Aaron Durbin
2017-11-10	amd/stoneyridge: Implement vboot_platform_is_resuming	Marshall Dawson
2017-11-10	amd/stoneyridge: Add function to find Pm1EvtBlk base	Marshall Dawson
2017-11-10	amd/stoneyridge: Remove dead southbridge definitions	Marshall Dawson
2017-11-10	amd/stoneyridge: Add more ACPI register definitions	Marshall Dawson
2017-11-10	amd/stoneyridge: Use the new generic acpi_sleep_from_pm1	Marshall Dawson
2017-11-10	amd/stoneyridge: Select AMD common sleep states	Marshall Dawson
2017-11-10	soc/amd/stoneyridge: Use uint8_t as type for SPD address	Richard Spiegel
2017-11-10	soc/amd/stoneyridge: Simplify and fix SMBUS code	Richard Spiegel
2017-11-10	soc/amd/common: Add DRAM clear option to northbridge.c	Richard Spiegel
2017-11-10	soc/intel/cannonlake: Remove structure variable initialization with 0	Subrata Banik
2017-11-10	soc/intel/common: Fix CSE common code to accomodate Skylake/Kabylake	Subrata Banik
2017-11-10	soc/intel/apollolake: Include HECI BAR0 address inside iomap.h	Subrata Banik
2017-11-10	src/soc/amd/stoneyridge/southbridge.h: Fix prototypes	Richard Spiegel
2017-11-09	soc/amd/stoneyridge: Fix and clean lpc.c	Richard Spiegel
2017-11-09	src/soc/amd/stoneyridge/southbridge.h: Remove unused prototypes	Richard Spiegel
2017-11-08	amd/stoneyridge: Add PSP definitions southbridge and iomap	Marshall Dawson
2017-11-08	amd/stoneyridge: Add SMU firmware blobs to cbfs	Marshall Dawson
2017-11-08	soc/amd/common/psp: Add command to load fw blobs	Marshall Dawson
2017-11-08	amd/stoneyridge: Remove fixme.c	Marshall Dawson
2017-11-08	amd/stoneyridge: Remove amdlib functions from fixme.c	Marshall Dawson
2017-11-08	amd/stoneyridge: Add northbridge register macros	Marshall Dawson
2017-11-07	soc/intel/kabylake: Add Dialog da7219 NHLT blob support	Naveen Manohar
2017-11-07	src: Fix all Siemens copyrights	Mario Scheithauer
2017-11-07	soc/intel/denverton_ns: re-factor HSIO configuration	Julien Viard de Galbert
2017-11-07	RISC-V boards: Stop using the config string	Jonathan Neuschäfer
2017-11-06	soc/amd/common/psp: Require PSP PCI definition in SOC	Marshall Dawson
2017-11-06	soc/amd/stoneyridge: consolidate addresses in iomap.h	Aaron Durbin
2017-11-06	soc/amd/stoneyridge: start header file for iomap	Aaron Durbin
2017-11-04	soc/amd/stoneyridge: don't open code known literals	Aaron Durbin
2017-11-04	soc/amd/stoneyridge: fix incorrect constants in macros	Aaron Durbin