coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2018-12-18	soc: Remove unneeded include <pc80/mc146818rtc.h>	Elyes HAOUAS
2018-12-18	soc/braswell: ensure ACPI opregion restored on S3 with GOP init	Matt DeVillier
2018-12-18	soc/baytrail: add vmx support via CPU_INTEL_COMMON	Matt DeVillier
2018-12-18	soc/amd/stoneyridge: Improve grammar through punctuation	Jonathan Neuschäfer
2018-12-18	Fix typos involving "the the"	Jonathan Neuschäfer
2018-12-17	soc/intel/fsp_broadwell_de: Drop unused files	Nico Huber
2018-12-14	soc/intel/cannonlake: Fix CNL-H GPIO pin map	Duncan Laurie
2018-12-14	soc/intel/cannonlake: Add GPIO group pad base for ACPI	Duncan Laurie
2018-12-14	soc/intel/common: Add support for GPIO group pad base	Duncan Laurie
2018-12-13	cpuid: Add helper function for cpuid(1) functions	Subrata Banik
2018-12-11	soc/intel/braswell/northcluster.c: Fix typo	Frans Hendriks
2018-12-11	mediatek/mt8183: Add DDR driver of tx rx window perbit cal part	Huayang Duan
2018-12-10	mb/intel/icelake_rvp: Fill Icelake U and Y RVP devicetree parameters	Aamir Bohra
2018-12-10	soc/intel/cannonlake: Fix GPIO reporting	Duncan Laurie
2018-12-07	soc/intel/apollolake: Print ME version on exit of BS_DEV_INIT stage	Karthikeyan Ramasubramanian
2018-12-07	riscv: fix non-SMP support	Philipp Hug
2018-12-07	soc/intel/cannonlake: Fix I2C clock input	Duncan Laurie
2018-12-06	soc/intel/apl: Warn if CBFS is outside the memory mapped area	Nico Huber
2018-12-06	src/soc/intel/braswell/southcluster.c: Config i8254 timer	Frans Hendriks
2018-12-05	sdm845: Add SPI-NOR flash driver	Mukesh Savaliya
2018-12-05	soc/amd/stoneyridge: Run romstage mainboard code before AGESA	Martin Roth
2018-12-05	soc/amd/stoneyridge: Name IO061 in ASL appropriately	Marshall Dawson
2018-12-05	src/(device/lib/soc): Remove unused variables	Richard Spiegel
2018-12-05	soc/sifive/fu540: Add helper function to get tlclk frequency	Jonathan Neuschäfer
2018-12-05	mb/emulation/spike-riscv: Implement mtime_init	Jonathan Neuschäfer
2018-12-05	mediatek: Share GPIO external interrupts (EINT) code among similar SoCs	Chuanjia Liu
2018-12-05	soc/intel/baytrail: Implement POSTCAR stage	Arthur Heymans
2018-12-05	soc/intel/baytrail: Use postcar_frame functions to set up frame	Arthur Heymans
2018-12-05	soc/intel/baytrail: Improve CAR setup	Arthur Heymans
2018-12-05	soc/intel/broadwell: Implement postcar stage	Arthur Heymans
2018-12-05	smmstore: make smmstore's SMM handler code follow everything else	Patrick Georgi
2018-12-05	elog: make elog's SMM handler code follow everything else	Patrick Georgi
2018-12-05	soc/intel/common/lpc_lib: Add function to disable LPC Clock Run	Nico Huber
2018-12-04	soc/intel/common: Limit BIOS region cache to 16MB	Lijian Zhao
2018-12-04	soc/intel/cannonlake: Add USB device names	Duncan Laurie
2018-12-04	soc/intel/cannonlake: Increase bootblock size	Duncan Laurie
2018-12-04	soc/intel/cannonlake: Add DPTF ACPI code	Duncan Laurie
2018-12-04	soc/intel/common/dptf: Add method for temp conversion	Duncan Laurie
2018-12-04	soc/intel/common/dptf: Make CPU address a define	Duncan Laurie
2018-12-04	soc/sifive/fu540: Load PLL settings from a struct	Jonathan Neuschäfer
2018-12-03	soc/intel/apl: Enable graphics with libgfxinit	Nico Huber
2018-12-03	soc/intel/apollolake: Add support to print ME version	Furquan Shaikh
2018-12-03	soc/amd/stoneyridge: Use new ACPI MMIO functions	Richard Spiegel
2018-12-03	soc/amd/stoneyridge: Create MMIO offsets for ACPI	Richard Spiegel
2018-12-03	soc/sifive/fu540: Simplify UART refclk calculation	Jonathan Neuschäfer
2018-12-03	soc/intel/cannonlake: Load FSP teardown optionally	Lijian Zhao
2018-12-03	soc/amd/stoneyridge: Create MMIO ACPI access functions	Richard Spiegel
2018-12-03	soc/intel/apl: Configure LPC serial IRQ mode	Nico Huber
2018-11-30	cpu/intel/common: Use a common acpi/cpu.asl file	Arthur Heymans
2018-11-30	soc/intel/fsp_baytrail: Rework acpi/cpu.asl	Arthur Heymans