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2016-04-15intel/apollolake: Fix logic errorPatrick Georgi
Testing dev->chip == NULL when dev == NULL doesn't make sense (and gcc thinks that's undefined behavior which should be rewarded with a trap). Change-Id: I801ce3d6b791fdf96b23333432dee394aa2e2ddf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14360 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-04-15intel/fsp_baytrail: fix whitespace issue in romstage.cBen Gardner
Change-Id: Ibb36292bb2fd40aa453dba1d9ce821f3e1e7a823 Reviewed-on: https://review.coreboot.org/14354 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-04-15soc/apollolake: Add helper functions to access Power Management RegistersHannah Williams
Change-Id: I928efea33030e03cbbaead6812c617d20446f7c9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14289 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-04-15soc/intel/apollolake: Fix northbridge _CRSZhao, Lijian
Fix build break on current _CRS method with correct scope. Change-Id: I75ba8abc547ec69be0a0950e23a7c31b447af31e Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/14288 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-14soc/apollolake: Add ACPI platform sleep capabilityHannah Williams
Change-Id: I6854f410b4d3847238f0253b7fbb9bbe8f9da395 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/14282 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-14soc/intel: Add Broadwell-DE SoC supportYork Yang
Initial files to support Broadwell-DE SoC. This is FSP 1.0 based project and is based on Broadwell-DE Gold release. Change has been verified on Intel Camelback Mountain CRB. Change-Id: I20ce8ee8dd1113a7a20a96910292697421f1ca57 Signed-off-by: York Yang <york.yang@intel.com> Reviewed-on: https://review.coreboot.org/14014 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-14src/soc/rockchip: Update license headersMartin Roth
Update all of the license headers to make sure they are compliant with coreboot's license header policy. Change-Id: Iea1a4b8f7df08d2ae694401211b0b664f5980b02 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14327 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-14soc/intel: Update license headersMartin Roth
Update all of the license headers to make sure they are compliant with coreboot's license header policy. Change-Id: I151d058615290e528d9d1738c17804f6b9cc8dce Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14321 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-13rockchip/common: do not retrieve register pointer twiceVadim Bendebury
The driver interface function derives the driver specific pointer from the API provided handle, no need to use the handle in the local functions. BRANCH=none BUG=none TEST=SPI interface with the flash ROM is still working properly. Change-Id: I7725b658365473c733698ca050e780d1dd5072d9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a2b42779785623bd1234ab2dfb0b4db76c890fc7 Original-Change-Id: I9d657dc23540e9eac52d2dbfc551ed32b7fa98f0 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/338090 Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14318 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-13rockchip/rk3288: refactor pwm driverLin Huang
3288 and 3399 use the same pwm controller. With this patch in place it is easy to add support for 3399. BRANCH=none BUG=none TEST=booted veyron_jerry to kernel login prompt Change-Id: If8f5697b4003d078b46de3fa3cebad6c8310a688 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: acf6132619167743c0c991b75f0f49c8d0e51ca7 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Change-Id: I79428f9ec71017ad8f3ad67dac1468178ccc3a1e Original-Reviewed-on: https://chromium-review.googlesource.com/338019 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14336 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-13rockchip/rk3288: refactor i2c interface to allow support of rk3399huang lin
Both SOCs use the same base i2c controller, the difference mostly being the number of interfaces and distribution of the interfaces' registers between register files. Upload check was complaining about misspelled labels, fixed them to pacify the check. With this patch in place it is easy to add support for 3399. BUG=none BRANCH=none TEST=brought up veyron_mickey all the way to booting the kernel. It properly recognized the TPM and the edid of the panel, proving that i2c interface is operational. Change-Id: I656640feabd0fc01d2c3b98bc5bd1e5f76f063f6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 82832dfd4948ce9a5034ea8ec0463ab82f0f5754 Original-Change-Id: I4829ea53e5f4cb055793d9a7c9957d6438138956 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/337971 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14335 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-13rockchip/rk3399: Add a stub implementation of the rk3399 SOChuang lin
Most things still need to be filled in, but this will allow us to build boards which use this SOC. BRANCH=none BUG=chrome-os-partner:51537 TEST=with the rest of the patches applied Kevin board can be booted to Linux login propmt. Change-Id: I6f2407ff578dcd3d0daed86dd03d8f5f4edcac53 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 27dfc39efe95025be2271e2e00e9df93b7907840 Original-Change-Id: I6f2407ff578dcd3d0daed86dd03d8f5f4edcac53 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/332385 Reviewed-on: https://review.coreboot.org/13915 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-13src/soc/marvell: Update license headersMartin Roth
Update all of the license headers to make sure they are compliant with coreboot's license header policy. Change-Id: I4572eec52bf834e4fac7bc5b54ceb591a0173a69 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14326 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-04-13soc/intel/apollolake: Add tsc_freq.c to all the stagesAndrey Petrov
Change-Id: I3120a52e21cf4ad03bb1d16b5b2b8a5e68aabf3f Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14339 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-04-13soc/intel/apollolake: Update platform-specific FSP headersAndrey Petrov
This updates FSP UPD headers that adds new fields. Importantly there are new FSPS UPD fields that allow to specify some BARs. They are needed by FSP SiliconInit API to work properly. Change-Id: Ie268c57c66b4d8fd6e00835916004058ff05762e Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14217 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-04-13soc/intel/apollolake: Reserve IMRs (Isolated Memory Regions)Andrey Petrov
Certain security features on the platform use IMRs. Unfortunately this memory is unusable for OS or firware. This patch marks IMR regions as unusable. Change-Id: I4803c41c699a9cb3349de2b7e0910a0a37cf8e59 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14245 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-04-13soc/intel/apollolake: logically group PMC BAR programmingAaron Durbin
The ACPI base address was being programmed sepearately from the other BARs in the PMC device. Group all the programming together so there isn't separate paths for programming the relevant BARs. Change-Id: Ib17684397fc19c42b39d066f981c01a886d65235 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14320 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-04-13src/soc/intel/common: Fix CID 1295499, remove dead codeLee Leahy
Restructure the nvm_is_write_protected routine to eliminate the dead code error. TEST=Build and run on Kunimitsu Change-Id: Ia9170e27d4be3a34760555c48c1635c16f06e6a3 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14337 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-04-11soc/intel/apollolake: Fill _PRT entry in DSDTZhao, Lijian
ACPI aware OS will need _PRT table to get desired interrupt resource assigned and make device driver working. The logical device within SOC gets fixed interrupt line. Change-Id: I75141bd62ca2594b74983dff54912e0b20458b9a Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/14243 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-11soc/intel/apollolake: Add lpss dsdt entryZhao, Lijian
Add southbridge and LPSS device DSDT table. Change-Id: I0607398408900d8c5d543ecd5e5d4830d2a70bf1 Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/14218 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-11soc/apollolake/acpi: Fill ACPI HPET tableZhao, Lijian
HPET table is required to report integrated HPET timer to kernel. Without HPET table added,Linux kernel will panic when loading timer driver. Change-Id: I7368bc29f4e03d5882dcfc4a770fa7bfbc6c26a0 Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/13374 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-11soc/apollolake: Add lpc device driverLance Zhao
A dedicated pci device driver required for LPC devices as the legacy IO range need to be included to avoid IO resource confilict. Blindly set to 0~0x1000 to also avoid the IO resource of COMA/COMB/LPT/FDD and LPC.Without this driver system will have assertion on load RTC DXE driver in UEFI payloads. Change-Id: Icc462c159c2cf39cc1030d55acee79e73a6bfb35 Signed-off-by: Lance Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/13356 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-11soc/apollolake/acpi: Fill in ACPI MADT tableLance Zhao
ACPI MADT tables required to describe the multiprocessor interrupt routing. Apollolake SOC also have the interrupt override table like other x86 silicons. Change-Id: I85976e227963c950aad4476d68581b96e1090559 Signed-off-by: Lance Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/13373 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-11soc/intel/apollolake: Enabling using of MRC data when availableAndrey Petrov
Change-Id: Iee30a6efb8dcdd04affd5d1105a254781287e9e4 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14253 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-04-11soc/intel/apollolake: Enable CACHE_MRC_SETTINGSHannah Williams
This enables CACHE_MRC_SETTINGS by default as well selects timer configuration. Change-Id: I0248001892ef763c39097848b5adc8c1befed1f0 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14252 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-11soc/apollolake/acpi: Fill ACPI MCFG tableLance Zhao
ACPI MCFG table is required for OS to support Enhanced Configuration Space Access.Apollolake will only support 1 PCI Segment Group, so all the pci bus number from 0 to 0xff will belong to that group. Change-Id: I3a680eb9c83290cd531159d7e796382a132cd283 Signed-off-by: Lance Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/13375 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-11soc/intel/apollolake: Implement SPI controller driverAlexandru Gagniuc
Implement flash read, write, and erase functionality using the hardware sequencing capabilities of the SOC. Due to changes in hardware requirements, the flash chip must be probed differently than on previous platforms (details explained in comments). Note that this is a minimal implementation, and does not provide all the bells and whistles. Change-Id: I6dcc3bc36dfce61927d126d231a16d485acb1bdc Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14246 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-11cpu/x86/tsc: compile same code for all stagesAaron Durbin
The delay_tsc.c code took different paths depending __PRE_RAM__ being defined or not. Also, timer_monotonic_get() was only compiled in a !__PRE_RAM__ environment. Clean up the code paths by employing CAR_GLOBAL for the global state which allows the same code to be used in all stages. Lastly, handle apollolake fallout now that init_timer() is not needed in placeholders.c. Change-Id: Ia769fa71e2c9d8b11201a3896d117097f2cb7c56 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14301 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-04-08soc/intel/apollolake: Override default to_flash_offset implementationAlexandru Gagniuc
The default nvm_mmio_to_flash_offset() implementation used by NVM code in intel/common does not work on apollolake. As a result, provide the correct override. Change-Id: I01a94f90dfdd33586a4aac5c05dd8c73e8804437 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14248 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-08soc/intel/common/nvm: Allow overriding to_flash_offset() functionAlexandru Gagniuc
On apollolake, the flash is memory-mapped differently, and the default MMIO to flash calculation does not produce correct results. While the long-term solution is to rewrite the NVM functionality to keep the flash offset as part of its context, as a temporary measure, allow overriding the to_flash_offset() function by declaring it weak. Change-Id: Ic54baeba2441a08cfe1a47e235747797f6efb59b Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14247 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-07rockchip: refactor to sharing code among similar SOCsVadim Bendebury
Upcoming designs are based on similar SOCs, this patch moves code which can be reused into a common directory under soc/rockchip. Changing spi.h to include stdder.h, as this is were check_member() is defined, this becomes necessary later when the new SOC code is added. Renaming UART driver private functions not to be bound to any particular SOC. BUG=none BRANCH=none TEST=the refactored code works fine on the new platform (with the rest of the patches applied). Change-Id: I39a505aecda8849daa58a8eca0e44a5243664423 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f63f2582042ac115481207ddf329ea2e3260e55e Original-Change-Id: I3a1139305354d460492b25a45f3da315a9a0b49e Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/335408 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14235 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-07edid: Make framebuffer row alignment configurableJulius Werner
Our EDID code had always been aligning the framebuffer's bytes_per_line (and x_resolution dependent on that) to 64. It turns out that this is a controller-dependent parameter that seems to only really be necessary for Intel chipsets, and commit 6911219cc (edid: Add helper function to calculate bits-per-pixel dependent values) probably actually broke this for some other controllers by applying the alignment too widely. This patch makes it explicitly configurable and depends the default on ARCH_X86 (which seems to be the simplest and least intrusive way to make it fit most cases for now... boards where this doesn't apply can still override it manually by calling edid_set_framebuffer_bits_per_pixel() again). Change-Id: I1c565a72826fc5ddfbb1ae4a5db5e9063b761455 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14267 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-04-05soc/intel/apollolake: Fill ACPI FADT tableLance Zhao
Fill the ACPI FADT table base on apollolake SOC definition. Change-Id: Ib7226a3b130f14810dc2af5ca484cef58f477063 Signed-off-by: Lance Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/13352 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-04-05mediatek/mt8173: fix incorrect indentYidi Lin
BUG=none BRANCH=none TEST=emerge-oak coreboot Change-Id: Ia5f2bc9b021b9051f2e5035c5d295b6b9eea1301 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7304016041d42a5317448fc2f9c58c6e6715fc25 Original-Change-Id: I7bcd1cf8dabbe190fcbc62cbf6b3a34430a97b21 Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/336592 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14236 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-05google/oak: Log hardware watchdog in eventlogJulius Werner
The MT8173 hardware watchdog can assert an external signal which we use to reset the TPM on Oak. Therefore we do not need to do the same double-reset dance as on other Chromebooks to ensure that we reset in a correct state. Still, we have a situation where we need to reconfigure the watchdog early in the bootblock in a way that will clear information about the previous reboot from the status register, and we need that information later in ramstage to log the right event. Let's reuse the same watchdog tombstone mechanism from other boards, except that we don't perform a second reset and the tombstone is simply used to communicate between bootblock and ramstage within the same boot. BRANCH=None BUG=None TEST=Run 'mem w 0x10007004 0x8' on Oak, observe how it reboots and how 'mosys eventlog list' shows a hardware watchdog reboot event afterwards. Change-Id: I1ade018eba652af91814fdaec233b9920f2df01f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 07af37e11499e86e730f7581862e8f0d67a04218 Original-Change-Id: I0b9c6b83b20d6e1362d650ac2ee49fff45b29767 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/334449 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://review.coreboot.org/14234 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-04-04soc/intel/apollolake: Fill northbridge ASLZhao, Lijian
Northbridge resource assignment: Dynamicly update memory resources for northbridge devices, exclude any fixed MMIO resources. Change-Id: I9595f9a12434fa423862836d19f7266d6023fc5a Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/13371 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-02soc/intel/apollolake: use platform_segment_loaded() for CAR coherencyAaron Durbin
Instead of using arch_segment_loaded() implement platform_segment_loaded() so as not to tangle the notion of arch and the chipset. Lastly, add a TODO to allow filtering of the L1D to L2 flush depending on the region loaded. Change-Id: I52e7cd2ae6e2d95f21bdd2fe1a471a10565309cb Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14215 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-04-02soc/intel/apollolake: use arch_segment_loaded() for CAR code coherencyAaron Durbin
Instead of using platform_prog_run() for flushing programs from L1D to L2 for code coherency purposes use arch_segment_loaded() instead as that it's primary purpose. The arch_segment_loaded() is called within the infrastructure at the appropriate places when loading programs. Therefore use that to perform the L1D flush instead of when something is just about to run. Change-Id: Ib0a6be6f676dcf2c946ef5702471af65d89133e9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14212 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-04-02soc/intel/apollolake: use CAR code coherency for all CAR stagesAaron Durbin
The flush L1D to L2 operation was only being used when loading romstage from bootblock. However, when the FSP-M component is loaded no code coherency actions are taken. I suspect this is because the FSP-M component is larger than the 24KiB L1D and the entry point is early in the image. Thus, when loading the FSP-M component the earlier part of the image is flushed out to L2 in the process of loading the latter part of the component. Also, once verstage is introduced the same code coherency actions need to be taken as well. Therefore, position the apollolake code to handle all these cases. Change-Id: Ie71764f1b420a6072c4f149ad3e37278b6cb70e1 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14210 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-04-01soc/intel/apollolake: Fix MMIO reserved ranges calculationAndrey Petrov
mmio_resource() takes memory address in kilobytes. This patch adds resources properly. Change-Id: Id78dcecf05ad5b2c84e5bb5445ae3a4e4ec9d419 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14203 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-29intel/skylake: Enable PROCHOTPratik Prajapati
This patch would enable PROCHOT feature in skylake. Asserting PROCHOT line would throttle the GPU/CPU. BUG=chrome-os-partner:51142 BRANCH=glados TEST=manually tested on lars. asserting PROCTHOT by EC reduces FSP in fish-tank from approx 40 to 20. (50 fish setting), also CPU freq. drops to from 1600000 to 400000 Change-Id: I8fc0c015ea2c26d20bbbfc619f720f231d540feb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1b88b1f183df9c7362d7e58acb0a1fa0b076d56e Original-Change-Id: Ida8636efc3d8da56ebd3931144d31ab1b88fe806 Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/331690 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-(cherry picked from commit d091a999c3827179182b62a1274a9b3581f7f006) Original-Reviewed-on: https://chromium-review.googlesource.com/333073 Original-Commit-Ready: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Original-Tested-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/14120 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-29ipq806x/storm: Return NULL for cbmem_top if DRAM is not initializedFurquan Shaikh
DRAM initialization on storm requires ipq blobs to be loaded from cbfs. vboot_locator first checks cbmem_find to see if cbmem is initialized and contains selected region info, else it falls back to vboot work buffer. Since cbmem_find calls into cbmem_top to identify the location of cbmem area, board/chipset is expected to return NULL until the backing store is ready, which in this case until DRAM is initialized in romstage, return NULL for cbmem_top. Change-Id: I1880ce61dcfdabaa527d7a6dcc3482dfe5d5fd17 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/14182 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-03-25intel/fsp_baytrail: Fix I2C abort logicBen Gardner
A call to i2c_read() for a non-existent address followed by an i2c_read() to a valid address results in a false abort status for the 2nd call. i2c_read(1, 0x40, 0, buf, sizeof(buf)) => 0x2000000 (I2C_ERR_TIMEOUT) i2c_read(1, 0x74, 0, buf, sizeof(buf)) => 0x4000000 (I2C_ERR_ABORT) Because the abort status register is cleared on read and wait_tx_fifo() reads it twice, the returned status does not contain the abort status. Fixing that changed the 2nd read to reflect the abort status. i2c_read(1, 0x40, 0, buf, sizeof(buf)) => 0x2000000 (I2C_ERR_TIMEOUT) i2c_read(1, 0x74, 0, buf, sizeof(buf)) => 0x4000001 (I2C_ERR_ABORT) Bit 0 indicates that the address was not acknowledged by any slave. That's the abort status from the previous transaction. So I added a read of the abort status before starting a transaction in both i2c_read() and i2c_write(). i2c_read(1, 0x40, 0, buf, sizeof(buf)) => 0x2000000 (I2C_ERR_TIMEOUT) i2c_read(1, 0x74, 0, buf, sizeof(buf)) => 0 (I2C_SUCCESS) Tested on a Bay Trail E3845 SoC. Change-Id: I39e4ff4206587267b6fceef58f4a567bf162fbbe Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: https://review.coreboot.org/14160 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2016-03-25intel/fsp_baytrail: Use read32() and write32() in i2c.cBen Gardner
i2c.c uses "*(volatile unsigned int *)" constructs where it could use read32() and write32(). Switch to using read32() and write32(). The remaining instances in wait_tx_fifo() and wait_rx_fifo() are fixed in https://review.coreboot.org/#/c/14160/ Change-Id: I39e4ff4206587267b6fceef58f4a567bf162fbbe (intel/fsp_baytrail: Fix I2C abort logic) I also fixed a few minor white space issues. Change-Id: I587551272ac171ef1f42c7eb26daf877dc56646b Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: https://review.coreboot.org/14162 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2016-03-24edid: Add helper function to calculate bits-per-pixel dependent valuesJulius Werner
Coreboot and most payloads support three basic pixel widths for the framebuffer. It assumes 32 by default, but several chipsets need to override that value with whatever else they're supporting. Our struct edid contains multiple convenience values that are directly derived from this (and other properties), so changing the bits per pixel always requires recalculating all those dependents in the chipset code. This patch provides a small convenience wrapper that can be used to consistently update the whole struct edid with a new pixel width instead, so we no longer need to duplicate those calculations everywhere. BUG=None TEST=Booted Oak in all three pixel widths (which it conveniently all supports), confirmed that images looked good. Change-Id: I5376dd4e28cf107ac2fba1dc418f5e1c5a2e2de6 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14158 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-03-23soc/intel/apollolake: utilize postcar phase/stageAaron Durbin
The current Apollolake flow has its code executing out of cache-as-ram for the pre-DRAM stages. This is different from past platforms where they were just executing-in-place against the memory-mapped SPI flash boot media. The implication is that when cache-as-ram needs to be torn down one needs to be executing out of DRAM since the act of cache-as-ram going away means the code disappears out from under the processor. Therefore load and use the postcar infrastructure to bootstrap this process for tearing down cache-as-ram and subsequently loading ramstage. Change-Id: I856f4b992dd2609b95375767bfa4fe64a267d89e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14141 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-03-21soc/apollolake: Add skeleton ACPI entryLance Zhao
Change-Id: Ib127af5392ca2b349480f5b21fad2186b444d7e6 Signed-off-by: Lance Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/13348 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-21mediatek/mt8173: Enable ARM trusted firmware integrationPatrick Georgi
In Chromium OS downstream this was done together with adding the support for ATF, but unfortunately ATF upstream isn't ready yet. This commit is a reminder to enable things once ATF caught up. Change-Id: Id0d6908d906a1e54cdda4f232d572d996d9c556f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13968 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-21mediatek/mt8173: Remove bl31 board parameters passing mechanismJimmy Huang
As the DA9212 and MT6311 external buck can be controlled by hardware since rev-5 board, we don't need to pass any board specific parameter to ARM TF. BRANCH=none BUG=none TEST=build pass Change-Id: I43eebe25ab14d3dd84e8bb4286e2bb55c8c3c063 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9c4dfe61c69042e464b384e2e0edbc55eda23a74 Original-Change-Id: I541357fee6afb1ff2d771bcb073f7c9a9db52f00 Original-Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/332344 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14124 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-21mediatek/mt8173: Add da9212 driverhenryc.chen
Add secondary PMIC for external buck control on Oak rev0/1/2/5 BRANCH=none BUG=none TEST=verified on Oak rev4/rev5 Change-Id: Ia000b0c7d61e8396856656247f9627e33b21b19b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 241508e7d781fac8ee085ee81962043dd654c52d Original-Change-Id: I6c75e2462363a5523bf1ebb03af7a36740293624 Original-Signed-off-by: henryc.chen <henryc.chen@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/332342 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14122 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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