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2015-04-08tegra132: Change all SoC headers to <soc/headername.h> systemJulius Werner
This patch aligns tegra132 to the new SoC header include scheme. Also alphabetized headers in affected files since we touch them anyway. BUG=None TEST=Tested with whole series. Compiled Rush_Ryu. Change-Id: I5cdf4008a65db84f15c937ef53aab5e4d3ef24c4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d5c5c63d7b6399d3eb8a211b15d47829fe93a591 Original-Change-Id: Ifafd4d42d4fb04a1c37e8a5f23877c2b550cf44c Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/224505 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9369 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-08rk3288: Add early SRAM mappingJulius Werner
Solving the DACR bug will mean that XN bits suddenly become enforced on non-LPAE systems, and we will no longer be able to execute out of a region mapped DCACHE_OFF. When we enable the MMU in romstage we are still executing out of SRAM, so we would instantly kill ourselves. Solve this issue by enabling the MMU earlier (in the bootblock) and mapping the SRAM regions as DCACHE_WRITETHROUGH. They should really be DCACHE_WRITEBACK, but it looks like there might be hardware limitations in the Cortex-A12 cache architecture that prevent us from doing so. Write-through mappings are equivalent to normal non-cacheable on the A12 anyway, and by using this attribute we don't need to introduce a new DCACHE_OFF_BUT_WITHOUT_XN_BIT type in our API. (Also, using normal non-cacheable might still have a slight speed advantage over strongly ordered since it should fetch whole cache lines at once if the processor finds enough accesses it can combine.) CQ-DEPEND=CL:223783 BUG=chrome-os-partner:32118 TEST=None (depends on follow-up CL) Change-Id: I1e5127421f82177ca11af892b1539538b379625e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e7b079f4b6a69449f3c7cc18ef0e1704f2006847 Original-Change-Id: I53e827d95acc2db909f1251de78d65e295eceaa7 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/223782 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9342 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-08rk3288: Fix some PLL divisors and improve clock codeJulius Werner
This patch does some general cleanup in the Rockchip clock code, and adds some more assertions regarding the PLL VCO and output frequency ranges. It changes all PLL divisors to use the lowest values that can still hit the target frequency, since higher NR values lead to higher jitter and higher NO values increase power draw. Also change DDR3 frequency code to hardcode the optimal divisors for certail frequencies. As a little hack we will interpret 666000000 to actually mean 666666666.6P (and analogous for 533MHz), since that's what you usually want for memory. BUG=chrome-os-partner:32139 TEST=Boot on veyron_pinky rev2, check that dpll_is shown as 666666666 in /sys/kernel/debug/clk/clk_summary. Change-Id: I57d7ef34500984184e010c0cc7d73789338834d4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7466ffc035b3f06ac280f412bc496059abf3239c Original-Change-Id: I4f3c39641955a95c6dfbe9334035eb670b138bf0 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/221801 Reviewed-on: http://review.coreboot.org/9339 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-08rk3288: Re-write spi_xfer() to support full duplexDavid Hendricks
This change re-writes the spi_xfer() function to support full-duplex transfers. Even though the code looks much different, the same basic algorithm for setting up the transfer is used. The main difference is that reads from rxdr and writes to txdr occur simultaneously and accounting is more complicated, so I separated the higher-level accounting portion from the low-level FIFO handling portion to simplify things. BUG=chrome-os-partner:31850 BRANCH=none TEST=Loaded content from SPI ROM fine, needs testing w/ EC Change-Id: Ic109a02daf52ba694b63a73fec1a72b3c5c0fd71 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6a14f5ff8ed04d62e8de6ad2f468b763ffb8213c Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I33d2f5179360baf94627c86b57d12f032897caf5 Original-Reviewed-on: https://chromium-review.googlesource.com/218881 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9338 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-07storm: fix CBFS definitionsVadim Bendebury
It's been a while since SBL blob size was reduced. As CBFS area by definition includes the bootblock, storm configuration needs to be updated to address the changes in layout. Incidentally, it looks like CBFS_SIZE configuration setting is not used on ARM platforms, this will have to be addressed separately. BRANCH=storm BUG=chromium:422501 TEST=storm firmware does not report the failure to find payload anymore Original-Change-Id: I37abf76a9d8884b3431633f57f64896c3a5fb135 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/222898 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit b104d5c1c328b8bd9c6f926ed4fe3e4948860fbc) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I2800bf4ac6383c5ceb47330f07efaaf64e5d80d9 Reviewed-on: http://review.coreboot.org/9372 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-04-07tegra132: Provide weak implementation of usb_setup_utmip in funitcfg.cFurquan Shaikh
Provide a weak implemenation of usb_setup_utmip function for those stages that do not include usb.c. BUG=chrome-os-partner:32684 BRANCH=None TEST=Compiles successfully Change-Id: Ia659b7f64e6c3e23053837337ccd267d4c179fba Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 49487e5af4471bff708d8939492af15fb5cb9e64 Original-Change-Id: Ib235cf039a17204ef7e06d545a3c86b75aff5b4c Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/221575 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9325 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-04-07pistachio: Change all SoC headers to <soc/headername.h> systemJulius Werner
This patch aligns pistachio to the new SoC header include scheme. Also alphabetized headers in affected files since we touch them anyway. BUG=None TEST=Tested with whole series. Compiled Urara. Change-Id: I0609b307695ba6a922384ac34dd604bffcb20692 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0a577918babf26adf10baa0f56a7065f5659d285 Original-Change-Id: I3ed405a3efdeec28965538d19a22f2b5b8204f01 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/224503 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9335 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-07exynos5420: Change all SoC headers to <soc/headername.h> systemJulius Werner
This patch aligns exynos5420 to the new SoC header include scheme. Also alphabetized headers in affected files since we touch them anyway. BUG=None TEST=Tested with whole series. Compiled Peach_Pit. Change-Id: If97b40101d3541a81bca302a9bd64b84a04ff24a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 570ca9ed6337d622781f37184b2cd7209de0083f Original-Change-Id: I338559564e57bdc5202d34c7173ce0d075ad2afc Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/224501 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9324 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-07exynos5250: Change all SoC headers to <soc/headername.h> systemJulius Werner
This patch aligns exynos5250 to the new SoC header include scheme. Also alphabetized headers in affected files since we touch them anyway. BUG=None TEST=Tested with whole series. Compiled Daisy. Change-Id: I39805c0346e117a0f9b2667763ecaa428f0f55a8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: db6762f0c8425371d9860f908a5cefdeee8d1abc Original-Change-Id: Ic358061ddcbbe7d83a95ca11247b8b505b20491d Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/224500 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9323 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-07broadwell: Change all SoC headers to <soc/headername.h> systemJulius Werner
This patch aligns broadwell to the new SoC header include scheme. BUG=None TEST=Tested with whole series. Compiled Auron and Samus. Change-Id: I0cb6aa3d17ce28890e586be1c2c7ad16d91dd925 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 23bcaa8110c4b63999c6ebf370045e9bef87ce6e Original-Change-Id: I613ec0e2b970c75d1f8f7d9bb454bcf11abc78f0 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/224507 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9364 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-04-07baytrail: Change all SoC headers to <soc/headername.h> systemJulius Werner
This patch aligns baytrail to the new SoC header include scheme. BUG=None TEST=Tested with whole series. Compiled Rambi. Change-Id: I0f0a894f6f33449756582eefa0b50bae545220db Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1216a86538517c03a7e5bca547d08ff3dbcaa083 Original-Change-Id: If5d2a609354b3d773aa3d482e682ab97422fd9d5 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/222026 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9363 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-04-07kconfig: drop intermittend forwarder filesStefan Reinauer
With kconfig understanding wildcards, we don't need Kconfig files that just include other Kconfig files anymore. Change-Id: I7584e675f78fcb4ff1fdb0731e340533c5bc040d Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/9298 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-04-06New mechanism to define SRAM/memory map with automatic bounds checkingJulius Werner
This patch creates a new mechanism to define the static memory layout (primarily in SRAM) for a given board, superseding the brittle mass of Kconfigs that we were using before. The core part is a memlayout.ld file in the mainboard directory (although boards are expected to just include the SoC default in most cases), which is the primary linker script for all stages (though not rmodules for now). It uses preprocessor macros from <memlayout.h> to form a different valid linker script for all stages while looking like a declarative, boilerplate-free map of memory addresses to the programmer. Linker asserts will automatically guarantee that the defined regions cannot overlap. Stages are defined with a maximum size that will be enforced by the linker. The file serves to both define and document the memory layout, so that the documentation cannot go missing or out of date. The mechanism is implemented for all boards in the ARM, ARM64 and MIPS architectures, and should be extended onto all systems using SRAM in the future. The CAR/XIP environment on x86 has very different requirements and the layout is generally not as static, so it will stay like it is and be unaffected by this patch (save for aligning some symbol names for consistency and sharing the new common ramstage linker script include). BUG=None TEST=Booted normally and in recovery mode, checked suspend/resume and the CBMEM console on Falco, Blaze (both normal and vboot2), Pinky and Pit. Compiled Ryu, Storm and Urara, manually compared the disassemblies with ToT and looked for red flags. Change-Id: Ifd2276417f2036cbe9c056f17e42f051bcd20e81 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f1e2028e7ebceeb2d71ff366150a37564595e614 Original-Change-Id: I005506add4e8fcdb74db6d5e6cb2d4cb1bd3cda5 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/213370 Reviewed-on: http://review.coreboot.org/9283 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-04-06Add predefined __ROMSTAGE__ and __RAMSTAGE__ macrosJulius Werner
This patch adds the macros __ROMSTAGE__ and __RAMSTAGE__ which get predefined in their respective stages by make, so that we have one specific macro for every stage. It also renames __BOOT_BLOCK__ and __VER_STAGE__ to __BOOTBLOCK__ and __VERSTAGE__ for consistency. This change is intended to provide finer control and clearer communication of intent after we added a new (optional) stage that falls under __PRE_RAM__, and will hopefully provide some robustness for the future (we don't want to end up always checking for romstage with #if defined(__PRE_RAM__) && !defined(__BOOT_BLOCK__) && !defined(__VER_STAGE__) && !defined(__YET_ANOTHER_PRERAM_STAGE__)). The __PRE_RAM__ macro stays as it is since many features do in fact need to differentiate on whether RAM is available. (Some also depend on whether RAM is available at the end of a stage, in which case #if !defined(__PRE_RAM__) || defined(__ROMSTAGE__) should now be authoritative.) It's unfeasable to change all existing occurences of __PRE_RAM__ that would be better described with __ROMSTAGE__, so this patch only demonstratively changes a few obvious ones in core code. BUG=None TEST=None (tested together with dependent patch). Change-Id: I6a06d0f42c27a2feeb778a4acd35dd14bb53f744 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a4ad042746c1d3a7a3bfda422d26e0d3b9f9ae42 Original-Change-Id: I6a1f25f7077328a8b5201a79b18fc4c2e22d0b06 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219172 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9304 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-04-06tegra132: Add tegra_lp0_resume codeYen Lin
BUG=chrome-os-partner:32015 BRANCH=None TEST=successfully suspend/resume on Rush/Ryu Signed-off-by: Yen Lin <yelin@nvidia.com> Change-Id: I279e42fd055805f0060951d272571bda66514ea6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a02452e431d9aa6245fb2421773d66fc416d0a6e Original-Change-Id: I11cca0a8f5e7a36c1fff690c8070c74706348949 Original-Reviewed-on: https://chromium-review.googlesource.com/214580 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Yen Lin <yelin@nvidia.com> Original-Tested-by: Yen Lin <yelin@nvidia.com> Reviewed-on: http://review.coreboot.org/9102 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-06baytrail: Fix hdmi audio choppy issueKein Yuan
Disable VC setting for HDA so hdmi audio choppy issue will be eliminated. Change HDA initialize steps to sync with UEFI reference code. BUG=chrome-os-partner:25651 BRANCH=Baytrail TEST=Does not have choppy noise during video playing Original-Signed-off-by: Kein Yuan <kein.yuan@intel.com> Original-Change-Id: I45d49123d369b7d075776215e709af5801ea696d Original-Reviewed-on: https://chromium-review.googlesource.com/186024 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Benson Leung <bleung@chromium.org> Original-Tested-by: Benson Leung <bleung@chromium.org> Original-Commit-Queue: Bernie Thompson <bhthompson@chromium.org> (cherry picked from commit 9f725a40f77cd684b2e230bd226d78d87b56e73b) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I4fc10a161e5996e14d4823491fb62a7beff39bcc Reviewed-on: http://review.coreboot.org/9297 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-06baytrail: reinitialize spi controller in SMM finalizationAaron Durbin
On the SMM APM_CNT_FINALIZE step reinitialize the SPI controller so that it can still log events after the SPI controller has been locked down. BUG=chrome-os-partner:24624 BRANCH=baytrail TEST=Built and booted. Events still logged after SPI controller has been locked down. Original-Change-Id: I41a3e12c0398303e74f95eb6df82d5bc4303898b Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/185630 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> (cherry picked from commit 28ffb1a9e761cdfeb173bd533684db1011260e0a) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ia82753cba9ae4f049de2e81061739efc21d49a1e Reviewed-on: http://review.coreboot.org/9296 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-04build system: rename __BOOT_BLOCK__ and __VER_STAGE__Patrick Georgi
Drop the inner underscore for consistency. Follows the commit stated below. Change-Id: I75cde6e2cd55d2c0fbb5a2d125c359d91e14cf6d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Based-on-Change-Id: I6a1f25f7077328a8b5201a79b18fc4c2e22d0b06 Based-on-Signed-off-by: Julius Werner <jwerner@chromium.org> Based-on-Reviewed-on: https://chromium-review.googlesource.com/219172 Reviewed-on: http://review.coreboot.org/9290 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2015-04-04rk3288: set cpu frequency up to 1.8GHzhuang lin
before the rkclk_init(), we must set rk808 buck1 voltage up to 1300mv BUG=chrome-os-partner:32716, chrome-os-partner:31896 TEST=Boot on veyron_pinky rev2,check the rk808 buck1 voltage 1300mv and check the cpu frequency up to 1.8GHz Original-Change-Id: I6a8c6e35bd7cc6017f2def72876a9170977f206e Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/222957 Original-Reviewed-by: Doug Anderson <dianders@chromium.org> (cherry picked from commit 2e7e7c265691250d4a1b3ff94fe70b0a05f23e16) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Iff89d959456dd4d36f4293435caf7b4f7bdaf6fd Reviewed-on: http://review.coreboot.org/9260 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-04rk3288: guarantee i2c low period more than 1.3ushuang lin
change i2c clock low period and high period proportion to 7:3 guarantee the low period more than 1.3us BUG=None TEST=Boot on veyron_pinky rev2,check the i2c clock frequency Original-Change-Id: I235e9e3ff54ab3b9cabad36bab58a8409f7005a0 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/223002 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 57a5d90d394086483e0dcdd6279678658d07d842) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I6b0c9dfa540354f6463ed90c9f3f9503a4d5749e Reviewed-on: http://review.coreboot.org/9259 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-04t132: Enable SMMU translationsFurquan Shaikh
BUG=None BRANCH=None TEST=Verified by reading back the value of SMMU_CONFIG register that enable bit is set to 1 Original-Change-Id: Iccc870141f9b9729971bf12119f9f3dae8181a43 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/222770 Original-Reviewed-by: Olof Johansson <olofj@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit a06b36f9003d801709d83a8faed6fc04bb91df1b) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Iae3949940a5a0efa2761542974d5c209178ce397 Reviewed-on: http://review.coreboot.org/9258 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-04tegra132: Store ODMDATA from BCT into PMC scratch for use by kernelTom Warren
In able to do earlyprintk spew on LP0 resume, the kernel needs to know the board UART. ODMDATA (in bct/odmdata.cfg) contains this info, and the kernel looks for it in PMC_SCRATCH20. Fetch the ODMDATA word from the BCT copy stored in IRAM by the BootROM. BUG=chrome-os-partner:32015 BRANCH=none TEST=Built for Rush and Ryu OK. Dumped PMC_SCRATCH20 in TegraShell on Rush and confirmed value is what's in odmdata.cfg. Original-Change-Id: I63f33558ee8b00bd6c1e313efcd531e1d5fc67eb Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/222402 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 3f6a21afdb81f7d2ae90119c563535b4c87c9ade) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I9819ffdf0f7618f0dd8dc50f81b5b26d6f94bfbd Reviewed-on: http://review.coreboot.org/9257 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-04tegra132: remove framebuffer reservationAaron Durbin
There's no need to reserve the framebuffer within coreboot. If the payloads need a framebuffer they can allocate one themselves. BUG=chrome-os-partner:31355 BRANCH=None TEST=Built and booted on ryu. Original-Change-Id: I8d8b159e7fdd877e392193c5474a7518e9b3ad21 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/221726 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 1ff8da9fed414fceeda3f94b296312f4531b320f) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I4e7c0417824f2be9836b1bc2bb99322c78490ca2 Reviewed-on: http://review.coreboot.org/9256 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-04veyron_pinky/rk3288: Use KHz, MHz and GHz constantsJulius Werner
Use the previously added frequency constants in patch titled 'stddef: Add KHz, MHz and GHz constants'. BUG=None TEST=Compiled Veyron_Pinky. Original-Change-Id: I4a1927fd423eb96d3f76f7e44b451192038b02e0 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/221800 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 41bb8026818b4381d4a6d43d2d433c207c3971bc) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I37a610d57f1a3d44796bf80de5104c2b5b3f3dac Reviewed-on: http://review.coreboot.org/9254 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-04broadwell: Enable turbo ratio if availableDuncan Laurie
When turning up the CPU frequency set it to turbo if that is a possibility. Also only set the frequency on the boot CPU since that is all we need it on, this will allow the 1-core turbo ratio. BUG=chrome-os-partner:28234 BRANCH=samus,auron TEST=build and boot on samus Change-Id: I573eb7a507305814ec48cc2f624b8e6ddad43f84 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: d408c1b462983c682d61c6c447692391c2b52183 Original-Change-Id: Ib5ad746767ee0a56bc7e59de679a9342f053c0e5 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/234401 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9281 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04Broadwell: Pass TSC value to romstage_mainLee Leahy
The romstage_main routine takes three parameters: bist, tsc_low and tsc_hi. However in cache_as_ram.inc only the bist value is being passed. This patch adds the two halves of the TSC value. BRANCH=none BUG=None TEST=Build and run on Samus Change-Id: I3d216edd0be65f29b51a66ed67b2d17910a594d4 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: de565f28dce8a549d74defbcf5eaf8116bb1b831 Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Original-Change-Id: I34fb21e493dcb3a44426ba7964cd72a319a4254e Original-Reviewed-on: https://chromium-review.googlesource.com/231173 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9280 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04broadwell: fix typo in pei_dataDuncan Laurie
This was copied and pasted more than it should have been... BUG=chrome-os-partner:28234 BRANCH=samus,auron TEST=build and boot on samus Change-Id: I5008f2992d8ab3b952042415af6d7844788e14fc Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: bff4570dffa413c4fc4dfd8c49920f6b951e944a Original-Change-Id: I2af9a30f3df733af147e8759f78a9802d2296c0f Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/230753 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9276 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04broadwell: Add USB3 PHY tuning fields to PEI DATADuncan Laurie
These are board specific adjustments that can be made for each USB3 port. BUG=chrome-os-partner:28234 BRANCH=samus,auron TEST=build and boot on samus Change-Id: Iaa3ce09419dfd64e3e8187f6dc073a8c68565337 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 21000496bb4560c9d1452a128335bbf24ca1b0aa Original-Change-Id: Iab92ff7b0218d4abd9eba8a94d34ddd9a30ddb87 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/230231 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9275 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04Baytrail: Fix no_dev_behind_port not executed for RP1/2/3.Kenji Chen
BRANCH=master BUG=chrome-os-partner:33113 TEST=Build a image and test on Rambi. Signed-off-by: Kenji Chen <kenji.chen@intel.com> Change-Id: I37add87e6fd3e7ad4eee09b8e0b312a2a89c7948 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 59b4c94be46b4397de7cb32726da9fa216e75a4c Original-Change-Id: I22c8f9730cc0e1ecc991f2dd7f2a1e7c548a1789 Original-Reviewed-on: https://chromium-review.googlesource.com/226654 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Kenji Chen <kenji.chen@intel.com> Original-Tested-by: Kenji Chen <kenji.chen@intel.com> Reviewed-on: http://review.coreboot.org/9272 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04Broadwell: Fix PCIe L1 Sub-State capability ID not filled.Kenji Chen
Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 31d7276fbdca67937bcdf0d5c2af371a2fd1a510 Original-BUG=chrome-os-partner:31424,chromeos-os-partner:32380 Original-TEST=Build a BIOS image and check the value is applied correctly. Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com> Original-Change-Id: I0adda3643776b259a635a021babd983090f1df43 Original-Reviewed-on: https://chromium-review.googlesource.com/220475 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Id88c11ed128b44c3a60ef1a141b99071c1ee15d3 Reviewed-on: http://review.coreboot.org/9267 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04broadwell: Fix building with USE=quiet-cbDuncan Laurie
This function needs to be available in different LOGLEVELs. BUG=chrome-os-partner:28234 BRANCH=samus TEST=USE=quiet-cb emerge-samus coreboot Change-Id: Ib56995db64a7417a637eb8a93350fc40e6f83340 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 716d26c82a7df1dccf8956f301ab0e103fcedcff Original-Change-Id: Ia8f0d05af24c9070c8c9241a3a7e137f845d1cab Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/221540 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9262 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-04tegra124: use known-good drive for fast-train onlyNeil Chen
A higher drive setting is used for fast link training, once the link training succeeds, a known-good drive setting will be used for the main stream transactions. For full link training sequence, the sink devices may ask for a preferred drive setting, thus this drive setting should be used for the main stream transactions too. BUG=chrome-os-partner:32129 TEST=all panels on blaze/big devices work fine. Original-Change-Id: Icc540650dc1329af07fd9ee4661eb7fad435fde4 Original-Signed-off-by: Neil Chen <neilc@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/219544 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 13d6accfdbe678e785851057f0800a3bbef11bea) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: If2fe7d5621f15aa3134d2a3920220e149bb64be6 Reviewed-on: http://review.coreboot.org/9248 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-04tegra124: add support for full DP link trainingNeil Chen
The original dp driver supports only fast link training and a special drive setting is used for the link training sequence. This might not be accepted by all panels. The better way is to go through full link training sequence to negotiate for a best drive setting. With the change, dp driver will try fast link training first, this is same as before. If it fails in fast link training, will try full link training. BUG=chrome-os-partner:32129 TEST=all panels on blaze/big devices work fine. Original-Change-Id: I6f3402c4c5993a156c965c7f52b011d336a2946f Original-Signed-off-by: Neil Chen <neilc@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/219543 Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 24966517d41252384af3c2784def36aebad42434) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I3e7e7e749e5c8a9f07ac6132859fcad6fc96c39c Reviewed-on: http://review.coreboot.org/9247 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-04-04rk3288: Replace SPI fifo_size with constantDavid Hendricks
rockchip_spi_slave has a fifo_size member which doesn't change. This just replaces the struct member with a #define. BUG=none BRANCH=none TEST=built and booted on Pinky Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I9ea5cdad49ee10c5f32304d0909c4a7e74a261f9 Original-Reviewed-on: https://chromium-review.googlesource.com/220471 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit f76cce3b38ac37f4df8abf6eebb8f7c7b29da095) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I3ab4eecfcce98aff3f6c9bd8f6c4e589784c60be Reviewed-on: http://review.coreboot.org/9246 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-04rk3288: Pass SPI bus speed in as parameter to init functionDavid Hendricks
This re-factors rockchip_spi to remove speed_hz which will instead be passed in via rockchip_spi_init(), thus making it easier to support other boards which may have different slave devices attached. BUG=none BRANCH=none TEST=built and booted on Pinky Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I7baf0fa0a2660e3c975847fdec3eb92bcd0d6c10 Original-Reviewed-on: https://chromium-review.googlesource.com/220411 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit de33d2ed6352fc4c8e81dc53451f164a8792daf2) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ie6473e47d50b7e633688185e8d8036980b833f1c Reviewed-on: http://review.coreboot.org/9245 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-03tegra132: implement platform_prog_run()Aaron Durbin
The tegra132 SoC is currently booting up on the AVP cpu which bootstraps the rest of the SoC. Upon exiting romstage it runs ramstage from its faster armv8 core. Instead of hard coding the stage loading operations use run_ramstage(). Change-Id: Ib9b3eecf376ae022f910295920a085bde6e17f9f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8848 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-03tegra124: implement platform_prog_run()Aaron Durbin
The tegra124 SoC is currently booting up on the AVP cpu which bootstraps the rest of the SoC. Upon exiting bootblock it runs romstage from its faster armv7 core. Instead of hard coding the stage loading operations use run_romstage(). Change-Id: Idddcfd5443f08d4dd41e1d9b71650ff6d4b14bc4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8847 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-03rmodule: use struct prog while loading rmodulesAaron Durbin
The rmod_stage_load structure contained the same fields as struct prog. In order to more closely integrate with the rest of program loading use struct prog. Change-Id: Ib7f45d0b3573e6d518864deacc4002802b11aa9c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9143 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-02pinky: Move some init to mainboard bootblockDavid Hendricks
This patch moves init for I2C, SPI, ChromeOS GPIOs to the board-specific bootblock init function on Pinky, the idea being to isolate SoC code so that it's more readily adaptable for different boards. BUG=none BRANCH=none TEST=built and booted on Pinky Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I75516bbd332915c1f61249844e18415b4e23c520 Original-Reviewed-on: https://chromium-review.googlesource.com/220410 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 0a7dec2fe70679c3457b0bfc7138b4a90b6217c8) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ib2c2e00b11c294a8d5bdd07a2cd59503179f0a84 Reviewed-on: http://review.coreboot.org/9243 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
2015-04-02rk3288/pinky: Move uart address to mainboard KconfigDavid Hendricks
Since the UART which is used for the serial console may change from board-to-board, this moves CONSOLE_SERIAL_UART_ADDRESS from rk3288's Kconfig into Pinky's Kconfig. BUG=none BRANCH=none TEST=built and booted on pinky Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I29837a72d8cf205a144494a6c8ce350465118b34 Original-Reviewed-on: https://chromium-review.googlesource.com/221438 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 53bff629f2e9865656beabd81e6ce1eab7c728a9) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I65835c07a49dc3a3518c6bb24a29bc6ae7dd46c9 Reviewed-on: http://review.coreboot.org/9242 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-04-02rk3288: remove duplicated #define `PERI_ACLK_DIV_SHIFT`Aaron Durbin
I'm not sure how the build didn't fail before. In either case remove the duplication. Change-Id: I764774f2b8a5839512af3f054b844a1a86efdb45 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9244 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-04-02Nyans: replace cpu_reset with hard_resetDaisuke Nojiri
The existing cpu_reset does board-wide reset, thus, should be renamed. BUG=none BRANCH=none TEST=Built firmware for Nyans. Ran faft on Blaze. Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: I5dc4fa9bae328001a897a371d4f23632701f1dd9 Original-Reviewed-on: https://chromium-review.googlesource.com/212982 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit 29753b9c1dfe7ecd156042d69b74e9fe4244f455) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I98eca40c50637bda01a9029a904bca6880cd081f Reviewed-on: http://review.coreboot.org/9179 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-04-02Broadwell: Select PCIE_L1_SUB_STATE and apply Broadwell settings.Kenji Chen
Signed-off-by: Stefan Reinauer <reinauer@chromium.org> BUG=chrome-os-partner:31424 TEST=Build an image and confirm the settings are correctly applied to registers for PCIe L1 Sub-State feature enabling. Original-Commit-Id: b94c8c715febe3a04bfdf52f7b69d73ece0f6faf Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com> Original-Change-Id: I07ce6eea648b1b37d606f5529edad184e3de70ac Original-Reviewed-on: https://chromium-review.googlesource.com/222599 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I07336599797c09bf23e5b15059d6ad812fdc7c61 Reviewed-on: http://review.coreboot.org/9223 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-04-02pistachio: add gpio type definitionVadim Bendebury
This is necessary to support generic gpio interface in src/lib. This file will be later populated with more GPIO definitions. BRANCH=none BUG=chrome-os-partner:31438 TEST=none Change-Id: I3fa93f1b3b1ce99d921bbfb378b3f7ae4eb652c2 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 26f564ee10a770d57cb4af0a8ab5a264aaf1a7cd Original-Change-Id: I68c9c3a28fcc747575436b502cb25b31afed8700 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/226181 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9184 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-04-02urara: Fix CBFS header definitionsVadim Bendebury
Urara CBFS header configuration is broken. CBFS header needs to be right above the bootblock, and the CBFS data - 0x100 bytes above, to allow room for proper CBFS wrapper structures. Ideally only the header offset should be specified (and even that could be derived from the bootblock size). But this is a more generic problem to be addressed with different architectures' image layout requirements in mind. BRANCH=none BUG=chrome-os-partner:31438 TEST=coreboot image passes the integrity check now (it was failing before because CBGS header was overlaying the bootblock) $ FEATURES=noclean emerge-urara coreboot $ /build/urara/tmp/portage/sys-boot/coreboot-9999/work/coreboot-9999/build/util/bimgtool/bimgtool \ /build/urara/firmware/coreboot.rom.serial $ cbfstool /build/urara/firmware/coreboot.rom.serial print coreboot.rom.serial: 1024 kB, bootblocksize 9956, romsize 1048576, offset 0x4100 alignment: 64 bytes, architecture: mips Name Offset Type Size fallback/romstage 0x4100 stage 7100 fallback/ramstage 0x5d00 stage 18995 config 0xa780 raw 2452 (empty) 0xb140 null 1003096 Change-Id: Id615bdcc6261dea9f36a409bd90f1e4764353bb9 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 8a0115963aa7460e4c7255ab8508d7d52d67fb67 Original-Change-Id: Id200ab5421661ef39b7c7713e931c39153fdc8be Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/227523 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/9187 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-04-02coreboot: rk3288: add new ddr config and support ddr3 freq up to 800mhzjinkun.hong
Add ddr3-samsung-2GB config and modify 533mhz linit. Support ddr3 freq up to 800mhz. Enable ODT at LPDDR3. BUG=None TEST=Boot Veyron Pinky Original-Change-Id: Ic02a381985796a00644c5c681b96f10ad1558936 Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/220113 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Tested-by: Lin Huang <hl@rock-chips.com> Original-Commit-Queue: Julius Werner <jwerner@chromium.org> Change-Id: I867753bc5d1eb301eb4975f5a945bfdba9b8f37d (cherry picked from commit e6689cbb0ec50317672c8ebe4e23555ca2f01005) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9239 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02rockchip: support pwm regulatorhuang lin
BUG=None TEST=Boot Veyron Pinky and test the VDD_LOG Original-Change-Id: Ie2eef918e04ba0e13879e915b0b0bef44aef550e Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/219753 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Julius Werner <jwerner@chromium.org> Change-Id: I444b47564d90b3480b351fdd8460e5b94e71927c (cherry picked from commit 4491d9c4037161fd8c4cc40856167bf73182fda6) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9240 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-04-02rockchip: support i2c clock settinghuang lin
BUG=None TEST=Boot Veyron Pinky and measure i2c clock frequency Original-Change-Id: I04d9fa75a05280885f083a828f78cf55811ca97d Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/219660 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Julius Werner <jwerner@chromium.org> Change-Id: Ie7ac3f2d0d76a4d3347bd469bf7af3295cc454fd (cherry picked from commit 4b9b3c2f8b7c6cd189cb8f239508431ee08ebc52) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9241 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-04-02veyron_pinky: Add rev2 support, clean up mainboard.cJulius Werner
This patch adds support for the board changes in rev2 (board_id = 0001). It also moves the existing mainboard.c code around a bit to group it by component. BUG=chrome-os-partner:32139 TEST=Booted on rev1. Confirmed SD card still works. Confirmed power button was still as broken as before. Original-Change-Id: Ifc4876687db64ca50e41d009d911446129d57b1b Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220251 (cherry picked from commit 9428e0d1b784b27790b3b3dbbb18a769e51c6fd3) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I8d3479aa314f8c6f1591c1b69b0a3827234fc730 Reviewed-on: http://review.coreboot.org/9237 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-02veyron: select rw romstage using vboot2Daisuke Nojiri
this change makes veyron pinky to select a rw romstage using vboot2. BUG=None TEST=Booted Veyron Pinky. Verified firmware selection in the log. BRANCH=None Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> CQ-DEPEND=CL:219100 Original-Change-Id: Ia1cfdacde9f8b17b00e7772a02e0d266afedb82f Original-Reviewed-on: https://chromium-review.googlesource.com/219103 Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit 69c1e4b9ee200645d38d28165389aa85ef9b36cd) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I7b4a2db8bcb95038dfb55bb7ceee66ac4a6c9475 Reviewed-on: http://review.coreboot.org/9234 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-12 12:04:16 +0000