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2018-01-22AMD/stoneyridge: Fix SATA reset inconsistencyRichard Spiegel
At AGESA AmdInitReset, SATA enable and IDE enable (elements of FCH_RESET_INTERFACE) are programmed twice (before calling AGESA for AmdInitReset and from said AGESA function call out), using different functions with different results. The first would result in TRUE/FALSE, the second set would result in TRUE/TRUE. Use the functions of the second set within the first set, and remove them from the second set. BUG=b:71754828 TEST=Build kahlle without the change, boot and record output. Rebuild kahlee with the change, boot and record output. Compare both outputs, the should be no change except in timing. Change-Id: I326fcc8801542aa7feef286d02abdfe63354cdd0 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/23295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-19amd/stoneyridge: Remove unused S3 NVRAM save/restoreMarshall Dawson
Remove the BiosRam read and write functions that were brought over from the hudson source. The functionality will be superseded later with new general-purpose functions. Change-Id: Ib80c66b838fdbdd388a392b4fedaac36bf0bbb0c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22725 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-19amd/stoneyridge: Add BIOS RAM R/W functionsMarshall Dawson
The internal FCH contains 256 bytes of "BiosRam" that maintains its state until RSMRST# is asserted or standby power is lost. Add functions to support read and write operations. Change-Id: I2ddf58a63e69b2775de9a8163534b13dad2ea2fe Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-01-19amd/stoneyridge: Move SB index/data pairs to iomap.hMarshall Dawson
Relocate the I/O registers to the iomap for PM, PM2, and BIOSRAM. Change-Id: I3a59adc974a8a90bfc586188b829a7252356b3cb Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22723 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-19amd/stoneyridge: Move acpi_get_sleep_type to sb_utilMarshall Dawson
Relocate the acpi_get_sleep_type() function out of the southbridge ramstage file. This will make it more convenient for using elsewhere. Change-Id: Id7ba709bb867fb00ed6c7fa7526de087a3b9b3ca Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-19soc/amd/common: Make agesa_heap_base non-staticMarshall Dawson
The cbmem location holding the heap will be used to store additional information in subsequent patches. Remove the static designation from agesa_heap_base. Change-Id: Ic607432fd6500ef69b5d47793896cf12a699d8b7 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22721 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-19amd/common: Remove GetHeapBase camel caseMarshall Dawson
A subsequent patch will use GetHeapBase() in more files than heapmanager.c. Convert it to a format more similar to existing coreboot source. Change-Id: I8362af849fc9d7cb1b8a93113e8d78dcac51c20a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22903 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-19amd/common: Define regions in AGESA cbmemMarshall Dawson
In 6c747068 "amd/stoneyridge: Put AGESA heap into cbmem" the AGESA heap was moved completely into cbmem. This was a departure from the "late cbmem init" method of adding it late in post, then storing the S3 volatile data to the region. Remove the hardcoded base address that was missed in that commit. To prepare for S3 support, split the region into subregions for heap, AGESA's S3 volatile storage, and an MTRR save area. BUG=b:69614064 Change-Id: I06c137f56516f3a04091d1191cd657a0aa07320b Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22720 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-19amd/common/s3: Remove legacy spi.cMarshall Dawson
Remove the original spi.c file that writes S3 NV data to flash in a proprietary format. The s3 folder is retained to facilitate new development. Change-Id: I1b5fe8e854c3d2dd71506c2acd6ff73e4b86d7d4 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/23305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-18security/tpm: Change TPM naming for different layers.Philipp Deppenwiese
* Rename tlcl* to tss* as tpm software stack layer. * Fix inconsistent naming. Change-Id: I206dd6a32dbd303a6d4d987e424407ebf5c518fa Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-18security/tpm: Move tpm TSS and TSPI layer to security sectionPhilipp Deppenwiese
* Move code from src/lib and src/include into src/security/tpm * Split TPM TSS 1.2 and 2.0 * Fix header includes * Add a new directory structure with kconfig and makefile includes Change-Id: Id15a9aa6bd367560318dfcfd450bf5626ea0ec2b Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-17soc/intel/cannonlake: Reserve PMC IO resourcesSubrata Banik
PMC controller gets hidden during FSP Silicon initialization using sideband interface on CNP-PCH. Hence unable to reserve PMC IO resources during PCI enumeration process. This causes hang issue on non-chrome platform with CNP-PCH due to ABASE corruption. This patch ensures PMC IO resource (ABASE) is getting reserved (IO address 0x1800-0x1900) and ACPI base is not overwritten by other devices. TEST=ABASE range is reserved along with LPC IO range during PCI enumeration. PCI: 00:1f.0 resource base 1800 size 100 align 0 gran 0 limit 0 flags c0000100 index 20 Change-Id: I1fbc4339ae11058fb3daedf4ffedda1904fa52ec Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-17soc/intel/common: Add option to pass SoC IO resourceSubrata Banik
This patch ensures common block has option to reserve IO resources based on SOC requirements. Also add pch_lpc_ prefix to maintain same function nomenclature across all intel common block. Change-Id: Ic00af688104bcea1aff06be6cbb20208a60e5f1d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-17soc/intel/apollolake/meminit_util_glk.c: Check for NULLRavi Sarawadi
We check for NULL here for memory_info_hob and return if it's NULL so that the future dereferencing is proper. Change-Id: Ie34931504ad92739fdaa68ec7989e76e8eee2595 Found-by: Klockworks Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/23223 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-17soc/intel/apollolake: Fix prev_sleep_state on G3 exitHannah Williams
If waking up from S5, then prev_sleep_state was correct but not when waking up from G3. Change-Id: I39011a0846f042d224a7cd65f736e749acc8ec75 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/23221 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-17soc/amd/common/block/pi: Fix AGESA heap deallocatorMarc Jones
The deallocation was always subtracting the header, even when it shouldn't. This caused problems for the allocator where buffer sizes were incorrect and freed and used buffers could collide. Fix the deallocation size. Clear deallocated concatinated buffer header memory. Fix the initial calculation of the total buffer size available to be allocated. BUG=b:71764350 TEST= Boot grunt. BRANCH=none Change-Id: I2789ddf72d662f24709dc5d9873741169cc4ef36 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/23284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-17soc/intel/cannonlake: Add option to select FSP_CARSubrata Banik
This patch provides an option for non-chrome devices to make use of FSP-T for performing cache-as-ram initialization. Majority of IOTG users are using FSP-T for CAR implementation and aren't able to select FSP_CAR Kconfig from SoC without conflicting with existing CAR config. TEST=Ensure that both the Chrome platform and non Chrome OS platform can select either CAR implementation based on Kconfig options FSP_CAR or CAR_NEM_ENHANCED. By default Chrome platform choose CAR_NEM_ENHANCED Kconfig and non Chrome platforms choose FSP_CAR by default. Change-Id: If565b649fe1c2abdbcf0a740c15db7253c084ae7 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-16soc/intel/cannonlake: Program DMI PCR settingsLijian Zhao
According to CNL PCH BIOS spec (570374) 2.4.1, DMI cycle decoding needs to be programmed before it gets locked. Update lpc programming to add decode programming on DMI side as well. Also enabled io port 0x200 decoding by default. BUG=b.70765863 TEST=Apply changes and add chromeos EC decoding in mainboard devicetree.cb, then read back IO port in depthcharge cli and check that return is not zero. Change-Id: I6b8f393c92cbd0632fed86212ae384ff53c9f8c3 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-16soc/intel/apollolake: Set ACPI_FADT_LOW_PWR_IDLE_S0 for S0ixShaunak Saha
This patch sets the ACPI FADT flag ACPI_FADT_LOW_PWR_IDLE_S0 if S0IX is enabled for the platform. TEST= Boot to OS and check the ACPI_FADT_LOW_PWR_IDLE_S0 flag is set in FACP table. Change-Id: Ibb43d5c8024dcdf753416e4bd2a457991cc7a433 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/23095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-01-15Intel sch board & chip: Remove - using LATE_CBMEM_INITMartin Roth
All boards and chips that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards and chips are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. chips: soc/intel/sch Mainboards: mainboard/iwave/iWRainbowG6 Change-Id: Ida0570988a23fd0d13c6fcbe54f94ab0668c9eae Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/22027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-01-15DMP Vortex86ex board & chip: Remove - using LATE_CBMEM_INITMartin Roth
All boards and chips that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards and chips are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. chips: soc/dmp/vortex86ex Mainboards: mainboard/dmp/vortex86ex Change-Id: Iee7b6005cc2964b2346aaf4dbd9b2d2112b7403f Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/22026 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-01-13soc/amd/stoneyridge: Add definition for GENINT_DISABLEMartin Roth
BUG=b:71867096 TEST=None Change-Id: Ic8111d34355e6667c37a51d285ebb50c1659f4e5 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/23227 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-13soc/amd/stonyridge: Give I2C devices unique _UIDsDaniel Kurtz
The ACPI unique identifier (_UID) should be unique. This doesn't actually matter much for Linux, though, since the kernel can handle it when the BIOS doesn't get this right. See: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=b4b6cae2f36d92b31788f10816709d5290a1119a b4b6cae2f36d ACPI / platform: use ACPI device name instead of _HID._UID Change-Id: I8b1b3143174584a93f3d45bf482b8922b3f0ec12 Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/23233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2018-01-13Revert "soc/amd/common/pi: Fix issue in AGESA heap allocator"Marc Jones
This reverts commit 0f5651584ebb8e2ccfa151275bfd2f70e74bae9b. This is not the correct fix for the heap allocator. It looks like the root cause is in the buffer size of the deallocate function. Change-Id: I33c479a30d89a665677d3e4914194ae8136504af Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/23245 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Chris Ching <chingcodes@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-12soc/intel/common/block: Check for NULL before dereferenceShaunak Saha
We check for NULL from the return of function acpi_device_path before passing it to acpigen_write_scope to avoid NULL pointer dereference. Change-Id: I997461c9b639acc3c323263d304333d3a894267c Found-by: Klockworks Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/23094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-12soc/intel/skylake: Override KBL IccMax settingsGaggery Tsai
According to Intel document #559100 KBL EDS v2.8, section 7.2 DC specifications, the IccMax setting for KBL-U, KBL-U42 and Celeron/Pentium are different. This patch overrides the IccMax settings for KBL-U/R/Y since device tree could not handle all KBL-U/R combinations when multiple SKUs are adopted in a project. Besides, it is inefficient to maintain the same code for all variants. Hence, place it in the common code so that all variants could leverage the benefits. +----------------+-------------+---------------+------+-----+ | Domain/Setting | SA | IA | GTUS | GTS | +----------------+-------------+---------------+------+-----+ | IccMax(KBL-U/R)| 6A(U42) | 64A(U42) | 31A | 31A | | | 4.5A(Others)| 29A(Celeron) | | | | | | 32A(i3/i5) | | | +----------------+-------------+---------------+------+-----+ | IccMax(KBL-Y) | 4.1A | 24A | 24A | 24A | +----------------+-------------+---------------+------+-----+ BUG=b:71369428 BRANCH=None TEST=Remove icc_max setting from devicetree & emerge-fizz coreboot chromeos-bootimage & Ensure the KBL-U42, KBL-U22 and Celeron SKUs are identified correctly and IccMax settings are passed to FSPS correctly. Change-Id: I291462b73d3fbd17f17975de7fd77dc48ca99251 Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/23060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-12soc/intel/common: Add Intel HDA common block driverDuncan Laurie
There is common HDA code in soc/intel/common that provides generic HDA support functions, but it does not provide a driver. This change adds a common block driver for HDA that provides a ramstage driver for SOCs that need to initialize an HDA codec. This was tested on a board with an HDA codec to ensure that it properly detected it and ran the codec init steps. Change-Id: I41b4c54d3c81e1f09810cfaf934ffacafca1cf38 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/23187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-12amd/stoneyridge: Keep SPI flash cacheable during POSTMarshall Dawson
A side effect of using the common MTRR assignment code is the flash device loses its WP setting and is no longer cacheable. After MTRR setup, reenable the setting for the duration of POST. TEST=Run on Kahlee and inspect MTRRs prior to AmdInitLate() BUG=b:70536683 Change-Id: Ib4924e96e2876e1e92121bb52d1931ead723d730 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/23205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-01-12soc/amd/common/pi: Fix issue in AGESA heap allocatorMarc Jones
The heap allocator would try to split a buffer node that was too small for another node. In the failing case, the buffer node was 0x140 bytes and the requested size was 0x133 bytes. The logic would check that there was room for the header and buffer and try to split the buffer node. The buffer node header is 0xC bytes, so 0x13F bytes are need. The problem is that it didn't leave room for another node header and a little space for a buffer. BUG=b:71764350 TEST= Boot grunt. BRANCH=none Change-Id: Iece5e12d5787415a335bb953985331a5dc312152 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/23211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Daniel Kurtz <djkurtz@google.com>
2018-01-10soc/rockchip/rk3399: Ensure full eDP init sequenceEge Mihmanli
This patch fixes 2 edp display issues: 1. When rk_edp_prepare fails >3 times, edp_init isn't run because while-condition is not satisfied. Then, only a partial init sequence is ran. This causes all aux transactions to fail. 2. If rk_edp_prepare never succeeds, coreboot never leaves link training stage due to infinite loop. Boot process is stuck. TEST=Boot past eDP initialization stage and make sure AP logs don't have show aux transaction fails. Change-Id: I44c3f53e8786558c43078d4afe9acde4d64796e7 Signed-off-by: Ege Mihmanli <egemih@google.com> Reviewed-on: https://review.coreboot.org/23152 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-01-10soc/intel/cannonlake: Add a call to gspi_early_bar_init in bootblockFurquan Shaikh
This change adds a call to gspi_early_bar_init in bootblock to allocate a temporary BAR for any GSPI buses that are accessed before resource allocation is done in ramstage. Change-Id: I82387a76d20fb272da6271dd9e5bf2c835d5b146 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22781 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-10soc/amd/common/block/acpi: Add halt.cChris Ching
Creating initial common acpi and implement halt.h BUG=b:71575631 BRANCH=none TEST=put poweroff() call in Kahlee's mainboard_final and board turns off correctly Change-Id: Ie7dd9851dcb240c53f2487b4f4b8a3e51d6b98d6 Signed-off-by: Chris Ching <chingcodes@chromium.org> Reviewed-on: https://review.coreboot.org/23074 Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-09soc/intel/cannonlake: Remove redundent CNL CPUID macrosSubrata Banik
This patch ensures all CannonLake CPUIDs are part of mp_init.h hence remove duplicate macro definitions from SoC code. TEST=Build and boot CannonLake RVP Change-Id: Ibb6a22d5c708248bb53522f906cffb462142b7bf Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23159 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-08soc/amd/stoneyridge/i2c: fix formatting and global symbolAaron Durbin
The i2c_bus_address array doesn't need to be a global symbol. Also, the array initializer had some weird indention and there was an extra new line. For consistency the first entry is multiplied by 0 so the formatting is similar. BUG=b:69416132 Change-Id: I74f6dca3a22a245759536f792ce04ac61735b6d0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Chris Ching <chingcodes@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-01-08soc/intel/cannonlake: Initialize DDI-A lane in Normal modeAbhay Kumar
Enable DDI-A (eDP) when pre-OS graphics is not Loaded or in normal mode. This will make sure that kernel will detect eDP. TEST=Edp should come up in normal mode. Change-Id: I6353020f892f2d7b75997eace88b3074adc32aef Signed-off-by: Abhay Kumar <abhay.kumar@intel.com> Reviewed-on: https://review.coreboot.org/22799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-08soc/amd/stoneyridge: Define CONSOLE_UART_BASE_ADDRESSArthur Heymans
The build system for the SeaBIOS payload needs this when DRIVERS_UART_8250MEM is set. Set it to the first uart controller, which the coreboot code also seems to do. Fixes: https://ticket.coreboot.org/issues/150 Change-Id: I962f750f89e0352082e0b7415ceaa9bd350fdf0b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-07soc/amd/common: Only load post-memory AGESA into RAM when split enabledDaniel Kurtz
CONFIG_AGESA_SPLIT_MEMORY_FILES controls whether AGESA is split into pre- and post-memory binaries when it is built. Building AGESA this way is required when doing the new "load post-memory AGESA binary into ram" feature. Thus, condition this new path on the CONFIG option being enabled. BUG=b:71641792 TEST=build and boot kahlee with CONFIG_AGESA_SPLIT_MEMORY_FILES disabled Change-Id: Ibec9db67437c57092e0f7acf0e3185865dc02688 Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/23141 Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-07soc/intel/cannonlake: provide LPDDR4 memory initNick Vaccaro
Instead of having the mainboards duplicate logic surrounding LPDDR4 initialization provide helpers to do the heavy lifting. It also handles the quirks of the FSP configuration which allows the mainboard porting to focus on the schematic/design. BUG=b:64395641 BRANCH=None TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a" compiles successfully. Change-Id: I4a43ea121e663b866eaca3930eca61f30bb52834 Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/22204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-073rdparty/blobs/soc/amd/stoneyridge: Use new location of stoneyridge blobRichard Spiegel
Stoneyridge related contents of 3rdparty/blobs/southbridge/amd/kern were moved to 3rdparty/blobs/southbridge/amd/stoneyridge. Commit the new blob to coreboot, and modify src/soc/amd/stoneyridge/Kconfig to use it. BUG=b:69613465 TEST=Build and run kahlee. Change-Id: I1784824dc7767c620e2fcbad7c6e5674934832ff Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/23125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-05soc/intel/cannonlake: Correct PMC/GPIO routing informationLijian Zhao
PMC and GPIO DWx definition is not identical, hence update that to correct information. For cannonlake lp PCH, GPIO group C, group E and group GPD is different for PMC GPIO_CFG and GPIO MISCCFG. Also add function call to set up GPE routing in bootblock stage. TEST=Boot up into OS, and manually check PMC GPE status Change-Id: I1edb83edabc72e8a762b129cf51dcd936cd37ddf Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-01-05soc/amd/common: load post-memory AGESA as rmoduleAaron Durbin
Now that the AGESA binary is split into two sections load the post-memory AGESA binary into ram. It needs to be an rmdoule so that it can be relocated into ram. agesawrapper_amdinitenv() entry CBFS: 'VBOOT' located CBFS at [10000:cfd40) CBFS: Locating 'AGESA_POST_MEM' CBFS: Found @ offset 875c0 size 11c5e Decompressing stage AGESA_POST_MEM @ 0xc757ffc0 (183452 bytes) Loading module at c7580000 with entry c7580000. filesize: 0x2bafc memsize: 0x2bb0d Processing 1112 relocs. Offset value of 0xc7780000 AGESA call 00020001 using c75818fe AGESA call 00020003 using c75818fe Fch OEM config in INIT ENV Done agesawrapper_amdinitenv() returned AGESA_SUCCESS BUG=b:68141063,b:70714803 TEST=Booted kahlee. Change-Id: Ic0454e0d6909cb34ae8be2f4f221152532754d61 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-05soc/amd/common: Allow AGESA file split for pre- and post-memoryJustin TerAvest
By splitting the binary files for platform initialization, the post-memory code can be modified to stop executing in place (--xip). This change creates two separate sections in CBFS for AGESA and loads the appropriate file at the correct stage. BUG=b:68141063 TEST=Booted kahlee with split agesa enabled. Change-Id: I2fa423df164037bc3738476fd2a34522df279e34 Signed-off-by: Justin TerAvest <teravest@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-03soc/amd/stoneyridge: Add I2C supportChris Ching
BUG=b:69416132 BRANCH=none TEST=make Change-Id: Id940af917c9525aba7bc25eea0821f5f36a36653 Signed-off-by: Chris Ching <chingcodes@chromium.org> Reviewed-on: https://review.coreboot.org/22959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-02soc/amd/common/block/pi: Format files to standardsRichard Spiegel
Files agesawrapper.c and heapmanager.c have several non-conformity with coreboot standards, including lines longer than 80 characters, use of "} else {" after a return and wrong comment block formatting. Fix all such issues, so that it passes commit tests. BUG=b:69262110 TEST=Build with no error gardenia and kahlee (no code change, just file formatting). Change-Id: Iefe741cd62bc41a7975c3dd10ac9355352de3abb Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-02soc/intel/skylake: Add device setting for sata power optimizationKane Chen
This change provides option in devicetree and feeds the option to FSP SataPwrOptEnable UPD for power saving purpose BUG=b:70491485 Change-Id: I9099c5c97765a118bdee64da303cb3ba6ceb951b Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/23018 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-23soc/intel/cannonlake: Select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2Furquan Shaikh
BUG=b:70628116 Change-Id: I40ebbb143b4618f83f454b9db2717589ba5ce99e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/22956 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-23soc/intel/common/block/gspi: Add SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2Furquan Shaikh
Even though kaby lake and cannon lake are using the same GSPI controller, bit meanings (for polarity and state) in SPI_CS_CONTROL register are significantly different. This change provides a new Kconfig option that can be selected by SoCs using these new bit definitions of SPI_CS_CONTROL. Common code takes care of setting the right value for polarity and state field depending upon the version selected by SoC. BUG=b:70628116 Change-Id: Ic69321483a58bb29f939b0d8b37f33ca30eb53b8 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/22954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-12-23soc/intel/{apollolake, cannonlake, common, skylake}: Add _soc_ prefix in ↵Subrata Banik
weak function This patch ensures all soc function name is having _soc_ prefix in it. TEST=Able to compile SMM common code for all supported SOC. Change-Id: Iab1b2f51eaad87906e35dbb9e90272590974e145 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-22soc/amd/stoneyridge/chip.c: Move setup_bsp_ramtop to soc_init()Richard Spiegel
Issue first reported at commit 1587dc8a2b, the call of functions setup_bsp_ramtop() and setup_uma_memory() should be moved from enable_dev() to soc_init(). The function setup_uma_memory() no longer exists, its functionality transfered to agesawrapper_amdinitpost. Move setup_bsp_ramtop() as required. BUG=b:62240756 TEST=Build and boot kahlee. Change-Id: I44e6cab17a8f7f364fc57657f41b211ec9d17641 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22948 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-12-22soc/intel: Treat time-out as failure in HECILijian Zhao
If HECI gets times out when waiting for read slots, there's no need to read back reply message to decide if the HECI recieve successed or not. Otherwise, system will stuck after global reset required. BUG=b:707290799 TEST=Boot up meowth board without battery, and confirm hard reset got trigged after heci time out. Change-Id: I7c1655284d7027294d8ff5d6a5dbbebe4cbd0c47 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
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