summaryrefslogtreecommitdiff
path: root/src/soc
AgeCommit message (Collapse)Author
2016-11-10mrc: Add support for separate training cache in recovery modeFurquan Shaikh
1. Re-factor MRC cache driver to properly select RW_MRC_CACHE or RECOVERY_MRC_CACHE based on the boot mode. - If normal mode boot, use RW_MRC_CACHE, if available. - If recovery mode boot: - Retrain memory if RECOVERY_MRC_CACHE not present, or recovery is requested explicity with retrain memory request. - Use RECOVERY_MRC_CACHE otherwise. 2. Protect RW and RECOVERY mrc caches in recovery and non-recovery boot modes. Check if both are present under one unified region and protect that region as a whole. Else try protecting individual regions. 3. Update training data in appropriate cache: - Use RW_MRC_CACHE if normal mode. - Use RECOVERY_MRC_CACHE if present in recovery mode. Else use RW_MRC_CACHE. 4. Add proper debug logs to indicate which training data cache is used at any point. BUG=chrome-os-partner:59352 BRANCH=None TEST=Verified that correct cache is used in both normal and recovery mode on reef. Change-Id: Ie79737a1450bd1ff71543e44a5a3e16950e70fb3 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17242 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-09soc/intel/skylake: fix memory access beyond array boundsRizwan Qureshi
chip.h has a config array PcieRpClkReqNumber which corresponds to a FSP UPD parameter, the size is currently set to 20. However the size of PcieRpClkReqNumber UPD in FSP2.0 is 24, so memcpy (config buffer to UPD buffer) in chip_fsp20.c will read beyond the bounds of config array. Hence set the size of PcieRpClkReqNumber array based on the FSP in use. Found-by: Coverity Scan #1365385, #1365386 Change-Id: I937f68ef33f218cd7f9ba5cf3baaec162bca3fc8 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/17292 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-08soc/intel/apollolake: Provide chipset value for ifdtoolAndrey Petrov
Change-Id: I99454a9fca3b677a389bcaf7693ff4e18415c9ad Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/17259 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-08intel car: Remove references to DCACHE_RAM_ROMSTACK_SIZEKyösti Mälkki
Not referenced in code. Change-Id: Iea91f4418eb122fb647ec0f4f42cb786e8eadf23 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17268 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-07soc/intel/skylake: Add _ACx methods for TSR0 sensor for fan controlSumeet Pawnikar
This patch updates below info, [1] Delete the DPTF_CPU_ACTIVE_AC* values because these are not being used. Hence, removing unnecessary defines. [2] Add new DPTF_TSR0_ACTIVE_AC* temperature trip points for TSR0 external thermal sensor. These trip points are being used by _ACx methods to control the fan speed on Skylake-U fan based Lars and Kunimitsu platforms. [3] Follow up patches are using DPTF_CPU_ACTIVE_AC* temperature trip points in board specific acpi/dptf.asl (for lars, kunimitsu, etc) to control the fan speed as per the CPU temperature trip points. [4] Newly added _ACx methods for thermal sensor TSR0 in this patch has nothing to do with DPTF_CPU_ACTIVE_AC*. We can control fan speed using various different thermal sensors. In this patch, we have added new _ACx methods for TSR0 thermal sensor. We run the fan at different speeds to cool down the system at different TSR0 temperatures. Similarly, we considered CPU sensor temperature values and ran the fan at different speeds to cool down the system. BUG=chrome-os-partner:51025 BRANCH=firmware-glados-7820.B TEST=Built and booted on kunimitsu and lars EVT boards. Verified these _ACx methods with _ART table on these boards with different workloads. Change-Id: Ia7b81e03da936c4a0f69057e43f18efd7c3b9f17 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://chromium-review.googlesource.com/332368 Reviewed-on: https://review.coreboot.org/17067 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-07lpss_i2c: Increase transaction timeoutDuncan Laurie
When doing long transcations on an I2C bus at standard speed we saw that long transactions could go over the 4ms limit while waiting for it to complete on the bus. Increase this so we can use standard speed for testing and debug in firmware. (as there is no way to force standard speed in the kernel) BUG=chrome-os-partner:58666 TEST=boot eve board with cr50 TPM and I2C bus at 100khz Change-Id: I2987ae6a5aa024b373eb088767194c70b0918b6f Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17213 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-07soc/intel/{sky,apollo}lake: Wait until GPE is clear when readingDuncan Laurie
When reading+clearing a GPE for use as an interrupt we need to re-read the status register and keep setting the clear bit until it actually reads back clear. Also add a 1ms timeout in case the status never clears. This is needed if a device sends a longer interrupt pulse and it is still asserted when the "ISR" goes to clear the status. BUG=chrome-os-partner:59299 TEST=test cr50 TPM with 20us pulse to ensure it can successfully communicate with the TPM and does not get confused due to seeing interrupts that it should not. Change-Id: I384f484a1728038d3a355586146deee089b22dd9 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17212 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-07soc/intel/apollolake: Add pmc_ipc device supportLijian Zhao
A dedicated pmc_ipc DSDT entry is required for pmc_ipc kernel driver. The ACPI mode entry includes resources for PMC_IPC1, SRAM, ACPI IO and Punit Mailbox. BRANCH=None BUG=chrome-os-partner:57364 TEST=Boot up into OS successfully and check with dmesg to see the driver has been loaded successfully without errors. Change-Id: Ib0a300febe1e7fc1796bfeca1a04493f932640e1 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/17181 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-11-07soc/intel/skylake: Fix SATA booting to OS issueSubrata Banik
SATA device remains unrecognized if connected at Port 2. Port control and Status register (PCS) is by default set by hardware to the disabled state as a result of an initial power on reset. OS read PCS register during boot causes disabling of SATA ports and can't detect any devices. BRANCH=none BUG=chrome-os-partner:59335 TEST=Build and boot SKL from SATA device connected at Port 2. Change-Id: I4866ca44567f5024edaca2d48098af5b4c67a7ac Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/17229 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-07soc/intel/skylake: Avoid use of variable Local0 in TEVT in thermal.aslNaresh G Solanki
Avoid use of Local0 variable in TEVT acpi method. If mainboard doesn't expose any thermal sensor, then warning is generated for variable Local0 not been used. Change-Id: I0634961a01144e41a8480c8c6ed8b7fdd358e768 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17245 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-07soc/intel/skylake: Add device id for PCH-YNaresh G Solanki
Add device id for PCH-Y used in Kaby Lake RVP3 board. Change-Id: I9235265cf88e4d044e7216f53e6da7021fb68238 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17244 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-06soc/intel/common: log event when MRC cache is updatedAaron Durbin
Log when the MRC cache is attempted to be updated with status of success or failure. Just one slot is supported currently which is deemed 'normal'. This is because there are more slots anticipated in the future. BUG=chrome-os-partner:59395 Change-Id: I0f81458325697aff9924cc359a4173e0d35da5da Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17231 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-11-03rockchip/rk3399: sdram.c: Fix msch ddrconfig register errorLin Huang
Fix msch ddrconfig register write error. Also make sure that the row number configured in msch is equal to the row number configured in the DDR controller. This would not affect systems with 4GB of memory, but is needed for 2GB configurations. BUG=None BRANCH=None TEST=Boot from kevin Change-Id: Ic95b3371faec5b31c32b011c50e55e83d949e74d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: dfa43d3d44839d9685b6393157f51b646e9996de Original-Change-Id: I0c95378bf937a245b7cdc0583c5d2ed1347f2a3e Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/399563 Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17208 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-03soc/intel/apollolake: Implement SPI flash status register readFurquan Shaikh
This was a dummy implementation until now which returned -1 always. Add support for reading SPI flash status register (srp0). BUG=chrome-os-partner:59267 BRANCH=None TEST=Verified by enabling and disabling write-protect on reef that the value of SRP0 changes accordingly in status register read. Change-Id: Ib1349605dd87c4a087e416f52a8256b1eaac4f4c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17205 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-02soc/intel/apollolake: Skip FSP initiated core/MP initVenkateswarlu Vinjamuri
Enable skip FSP initiated core/MP init as it is implemented in coreboot. BUG=chrome-os-partner:56922 BRANCH=None Change-Id: I9417dab3135ca1e0104fc3bde63518288bcfa76a Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/17201 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-02soc/intel/apollolake: Disable Monitor and Mwait featureVenkateswarlu Vinjamuri
Monitor/Mwait is broken on APL. So, it needs to be disabled. BUG=chrome-os-partner:56922 BRANCH=None Change-Id: I12cd4280de62e0a639b43538171660ee4c0a0265 Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/17200 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-11-02rockchip/rk3399: display: Do not allocate framebuffer in corebootLin Huang
framebuffer address is dynamically chosen by libpayload now, so there's no need to configure it in coreboot. CQ-DEPEND=CL:401402 BUG=chrome-os-partner:58675 BRANCH=none TEST=Boot from kevin, dev screen is visible Change-Id: I9f1e581d5c63b3579b26be22ce5c8d1e71679f6f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b3b6675420592c30e1e0abc8f8e9dd6ed5abd04c Original-Change-Id: I7e3162f24a4dc426fe4e10d74865cf0042c80db5 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/401401 Original-Commit-Ready: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17109 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-02rockchip/rk3399: sdram: Reset system if switch to index1 failsLin Huang
Near the end of DDR initialization, the system switches to the index1 configuration. Sometimes this failed and a status bit that coreboot was waiting for was never set, hanging the system. Instead, give the system 100ms to reach the new configuration or reboot it, which generally fixes the issue. Also reset when training the index1 configuration fails. BUG=chrome-os-partner:57988 BRANCH=None TEST=The error condition now leads to a reboot of coreboot which recovers the system, instead of hanging. Change-Id: Icb4270369102ff7a4ce91b0677e04b4eb10f1204 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ca250d0628ea3b6b39d5131246eaba68637c5140 Original-Change-Id: Id6e8936d90e54b733ac327f8476d744b45639232 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/399681 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17106 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-02rockchip/rk3399: sdram: Fix data training functionLin Huang
1. Update write leveling value to 0x200. When the wrdqs slave delay is changed to 0x200, the phase between the dqs and the clock is 0 degrees. The pcb layout can make sure the tDQSS timing is smaller than 0.25tck, so this value is useful for both higher and lower frequencies. 2. Disable read leveling for LPDDR3. The read leveling result is unreliable - the value is not in the middle of the read eye. To fix this, disable read leveling and fix the read DQSn slave delay setting for DQn to 0x080 (1/4 cycle delay of the input signal). BUG=None BRANCH=None TEST=Boot from kevin; Check by shmoo read eye and stability test, that the updated value of 0x80 is better. Change-Id: Ia72b601d9bf4e34ba1b0b4584b2c5c3ce9dafbd4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 37e8dfe783db3ce71aa026b4609ed0bfa16db06f Original-Change-Id: I2a5d40c0348449b2a7c609c1db65da4ed5f1c09f Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Jeff Chen <cym@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/396598 Original-Commit-Ready: Douglas Anderson <dianders@chromium.org> Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org> Reviewed-on: https://review.coreboot.org/17105 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-02rockchip/rk3399: sdram: also prepare the index1 configurationLin Huang
To enable DDR Dynamic Voltage and Frequency Scaling (DVFS) we need to train alternative configurations first, so do the training and store the values. BUG=None BRANCH=None TEST=Boot from kevin Change-Id: I944a4b297a4ed6966893aa09553da88171307a42 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 94533ff3ba21bcb0ace00bedcf0cebb89a341be2 Original-Change-Id: I4a98bc0db5553d154fedb657e35b926a92aa80c7 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/386596 Original-Commit-Ready: Douglas Anderson <dianders@chromium.org> Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17104 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-02intel/{skylake,apollolake}: Enable signalling of error conditionPatrick Georgi
Testing for "devfn < 0" on an unsigned doesn't work, and i2c_bus_to_devfn returns an int (with -1 for "error"), so use int for devfn. Adapt Change-Id I7d1cdb6af4140f7dc322141c0c018d8418627434 to fix more instances. Change-Id: I001a9b484a68e018798a65c0fae11f8df7d9f564 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1357450, #1357449 Reviewed-on: https://review.coreboot.org/17054 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-02rockchip/rk3399: Reserve enough framebuffer memory for 32bpp hires panelsJulius Werner
Some of our RK3399 devices have panel resolutions as high as 2400x1600. With 16bpp that barely still fit into an 8MB framebuffer, but then we changed it to 32bpp for better image quality... Note that this is a band-aid. Coreboot-allocated framebuffers shouldn't be used at all on ARM64 devices, since libpayload is perfectly capable to dynamically allocate it with the right size based on EDID-information on this architecture. That will require some more elaborate work to be fixed with later patches. BRANCH=gru BUG=chrome-os-partner:58044 TEST=Warm-reboot Kevin on the dev screen, confirm that you don't see the lower half of the screen that overflowed our allocated framebuffer preserved from the last boot as soon as the backlight turns on. Change-Id: I00a63cfef35a8ee734543abbdb298344fb529283 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d2718efcacb50371624d9f6a3b586c298e8c2fec Original-Change-Id: Ia1fa28971c65d7d0639966e715f742309245172b Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/399966 Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/17108 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-01soc/apollolake: Add soc core initRavi Sarawadi
Add soc core init to set up the following feature MSRs: 1. C-states 2. IO/Mwait redirection BUG=chrome-os-partner:56922 BRANCH=None TEST= Check C-state functioning using 'powertop'. Check 0xE2 and 0xE4 MSR to verify IO/Mwait redirection. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: I99b66b02eb790b6b348be7c964d21ec9a6926926 Reviewed-on: https://review.coreboot.org/17168 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-10-31lib/prog_loaders: use common ramstage_cache_invalid()Aaron Durbin
All current implementations of ramstage_cache_invalid() were just resetting the system based on the RESET_ON_INVALID_RAMSTAGE_CACHE Kconfig option. Move that behavior to a single implementation within prog_loaders.c which removes duplication. Change-Id: I67aae73f9e1305732f90d947fe57c5aaf66ada9e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17184 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-10-29soc/intel/common: Add reset.c to postcarFurquan Shaikh
ramstage_cache_invalid which was added in I83fe76957c061f20e9afb308e55923806fda4f93 (review.coreboot.org/#/c/17112) requires hard_reset to be defined in postcar stage. BUG=None BRANCH=None TEST=Compiles successfully for reef. Change-Id: I283277c373259e0e2dfe72e3c889ceea012544f2 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17182 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-10-28soc/intel/skylake: don't hardcode GPE0 standard regAaron Durbin
While using '3' is fine for the standard gpe0 for skylake, I want to make sure anyone that copies this code doesn't tweak GPE0_REG_MAX without the hard coded index. If that does happen now things will still work, but it may just not match the hardware proper. BUG=chrome-os-partner:58666 Change-Id: I434b9a765a0a2f263490bb2b4ecb3635292d46c9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17160 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-10-28skylake: Add GPIO macro for configuring inverted APIC inputDuncan Laurie
Add a GPIO macro that allows a pin to be routed to the APIC with the input inverted. This allows a normal interrupt to get used as a GPE during firmware and still be used as a perhiperal interrupt in the kernel. BUG=chrome-os-partner:58666 TEST=boot en eve and use TPM IRQ in firmware and OS Change-Id: I77f727f749fdd5281ff595a9237fe1e634daba96 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17176 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-28soc/intel/skylake: put back uart_debug.c into verstageAaron Durbin
uart_debug.c was accidentally dropped in verstage in 64ce1d122c0464a4ef138fb7452a91b408b1a7c2 (https://review.coreboot.org/17136). Fix that. Change-Id: If37a028550d419bada80d157c4de02fd82d26c89 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17175 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-10-27soc/intel/skylake: make inline function staticNaresh G Solanki
Make bootblock_fsp_temp_ram_init as static inline. Change-Id: Iacf24728a45fc6554d7a425feecc25e55ac5da6c Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17084 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-27skylake: Add support for eSPI SMI eventsDuncan Laurie
Add the necessary infrastructure to support eSPI SMI events, and a mainboard handler to pass control to the EC. BUG=chrome-os-partner:58666 TEST=tested on eve board with eSPI enabled, verified that lid close event from the EC during firmware will result in an SMI and shut down the system. Change-Id: I6367e233e070a8fca053a7bdd2534c0578d15d12 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17134 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-10-27skylake: Prepare GPE for use in bootblockDuncan Laurie
Export the pmc_gpe_init() function from pmc.c to pmutil.c so it can be used in bootblock, and then call it from there to initialize any GPEs for use in firmware. BUG=chrome-os-partner:58666 TEST=test working GPE as TPM interrupt on skylake board Change-Id: I6b4f7d0aa689db42dc455075f84ab5694e8c9661 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17135 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-27skylake: Support for early I2C TPM driverDuncan Laurie
Add the SOC definition for acpi_get_gpe() so it can be used by the I2C TPM driver. Also add the I2C support code to verstage so it can get used by vboot. BUG=chrome-os-partner:58666 TEST=boot with I2C TPM on skylake board Change-Id: I553f00a6ec25955ecc18a7616d9c3e1e7cbbb8ca Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17136 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-10-27skylake: Fix wake source reporting with Deep S3Duncan Laurie
The Deep S3 state will lose a lot of register contents that we used to rely on for determining wake source. In order to make use of this override the enable bit for wake sources that are enabled for Deep S3 in devicetree.cb. BUG=chrome-os-partner:58666 TEST=check for _SWS reporting wake source on S3 resume on skylake Change-Id: If5113d6890f6cbecc32f92af67a29952266fe0ac Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17137 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-10-27skylake: Use COMMON_FADTDuncan Laurie
Remove the FADT from the individual mainboards and select and use COMMON_FADT in the SOC instead. Set the ACPI revision to 5. Change-Id: Ieb87c467c71bc125f80c7d941486c2fbc9cd4020 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17138 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-10-26intel/skylake: Add support to enable wake-on-usb attach/detachFurquan Shaikh
Three things are required to enable wake-on-usb: 1. 5V to USB ports should be enabled in S3. 2. ASL file needs to have appropriate wake bit set. 3. XHCI controller should have the wake on attach/detach bit set for the corresponding port in PORTSCN register. Only part missing was #3. This CL adds support to allow mainboard to define a bitmap in devicetree corresponding to the ports that it wants to enable wake-on-usb feature. Based on the bitmap, wake on attach/detach bits in PORTSCN would be set by xhci.asl for the appropriate ports. BUG=chrome-os-partner:58734 BRANCH=None TEST=Verified that with port 5 enabled, chell wakes up from S3 on usb attach/detach. Change-Id: I40a22a450e52f74a0ab93ebb8170555d834ebdaf Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17056 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-26soc/intel/apollolake: Enable write-protect SPI flash range supportFurquan Shaikh
Use intel common infrastructure to enable support for write-protecting SPI flash range. Also, enable this protection for RW_MRC_CACHE. BUG=chrome-os-partner:58896 TEST=Verified that write to RW_MRC_CACHE fails in OS using "flashrom -p host -i RW_MRC_CACHE -w /tmp/test.bin" Change-Id: I35df12bc295d141e314ec2cb092d904842432394 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17117 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-10-26soc/intel/skylake: Use intel common support to write-protect SPI flashFurquan Shaikh
BUG=chrome-os-partner:58896 Change-Id: I281c799a1798f3353d78edd8a6cd16bbe762bc2c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17116 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-26soc/intel/common: Enable support to write protect SPI flash rangeFurquan Shaikh
Write-protect SPI flash range provided by caller by using a free Flash Protected Range (FPR) register. This expects SoC to define a callback for providing information about the first FPR register address and maximum number of FPRs supported. BUG=chrome-os-partner:58896 Change-Id: I4e34ede8784e5587a5e08ffa10e20d2d14e20add Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17115 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-10-25riscv: add the lowrisc System On Chip supportRonald G. Minnich
Change-Id: I8d81b9cf280e724c935106c8f00692300094ad3f Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/17119 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2016-10-25Revert "soc/apollolake: Add soc core init"Aaron Durbin
This reverts commit a52f883b100f3229dd4d86c81c08781993861f73 (https://review.coreboot.org/16587). The above commit caused another sever kernel boot regression upwards of 2 minutes to get through kernel init on quad core systems. BUG=chrome-os-partner:58994 Change-Id: Id4abc332bf2266e3b3b7be714371ce9cf329bcd9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17121 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-10-25rockchip/rk3399: reset system if DDR init failsLin Huang
We found sdram may fail in pctl_cfg(), so we check the status in this function. If it exceeds 100ms still in this function, we will restart the system. We also found there are rare chances DDR training fails, so also restart system in that case. BUG=chrome-os-partner:57988 BRANCH=None TEST=coreboot resets on failure and eventually the system comes up Change-Id: Icc0688da028a8f4f81eafe36bbaa79fdf2bcea74 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 89e45f8352f62e19a203316330aba14ccc5c8b11 Original-Change-Id: If4e78983abcfdfe1e0e26847448d86169e598700 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/397439 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17045 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-25soc/intel/apollolake: Implement GPIO ACPI AML generating functionsFurquan Shaikh
Implement GPIO ACPI AML generating functions that can be called by coreboot drivers to generate GPIO manipulation code in AML. Following functions are implemented: 1. acpigen_soc_read_rx_gpio 2. acpigen_soc_get_tx_gpio 3. acpigen_soc_set_tx_gpio 4. acpigen_soc_clear_tx_gpio BUG=chrome-os-partner:55988 Change-Id: I3d8695d73a1c43555032de90f14ee47ccee45559 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17082 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-10-21marvell/mvmap2315: Compose BOOTBLOCK regionDaisuke Nojiri
This patch adds a Makefile rule for mvmap2315 to install a BDB and bootblock code in the BOOTBLOCK region. The resulting BDB has a header and data both signed by a RSA-4096 key. BUG=chrome-os-partner:57889 BRANCH=none TEST=emerge-rotor coreboot and examined the output binary. Booted coreboot.rom. Change-Id: I1e20a09b12f8f8ed4d095aa588e3eb930f359fc5 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/16747 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-19intel/broadwell: "free" memory after usePatrick Georgi
While we stub out free(), tools like coverity scan have no idea, and it might change in the future. So free it. Change-Id: I1d93a6f45b64445662daa95b51128140ad0a87e2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1260716 Reviewed-on: https://review.coreboot.org/17055 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2016-10-19soc/intel/skylake: Allow selecting FSP driver in KconfigNaresh G Solanki
Enable mainboard Kconfig to select between FSP 2.0 & 1.1 driver to be used. If mainboard Kconfig selects MAINBOARD_USES_FSP2_0 the FSP2_0 driver is used else FSP1_1. Change-Id: I724aaa87c2b0b8f6ddb18f61af9c37176ef632f2 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/17044 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-18rk3399: display: Use edid_set_framebuffer_bits_per_pixel() helperJulius Werner
This refactoring was already carried into RK3288 with commit 6911219 (edid: Add helper function to calculate bits-per-pixel dependent values) but it seems that the code for RK3399 was copy&pasted from it too early to pick this up. Fix that so that future Rockchip SoCs can copy&paste the right thing. Change-Id: I5050c58d18db38fffabc7666e67a622d4a828590 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17050 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-10-16soc/apollolake: Add soc core initRavi Sarawadi
Skip FSP initiated core/MP init as it is implemented and initiated in coreboot. Add soc core init to set up the following feature MSRs: 1. C-states 2. IO/Mwait redirection BUG=chrome-os-partner:56922 BRANCH=None TEST= Check C-state functioning using 'powertop'. Check 0xE2 and 0xE4 MSR to verify IO/Mwait redirection. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: I97c3d82f654be30a0d2d88cb68c8212af3d6f767 Reviewed-on: https://review.coreboot.org/16587 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-16soc/intel/apollolake: Set PL1 limits for RAPL MSR registersSumeet Pawnikar
This patch sets the package power limit (PL1) value in RAPL MSR and disables MMIO register. Added configurable PL1 override parameter to leverage full TDP capacity. BUG=chrome-os-partner:56922 TEST=webGL performance(fps) not impacted before and after S3. Change-Id: I34208048a6d4a127e9b1267d2df043cb2c46cf77 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/16884 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-16soc/intel/skylake: Handle platform global resetSubrata Banik
In FSP1.1 all the platform resets including global was handled on its own without any intervention from coreboot. In FSP2.0, any reset required will be notified to coreboot and it is expected that coreboot will perform platform reset. Hence, implement platform global reset hooks in coreboot. If Intel ME is in non ERROR state then MEI message will able to perform global reset else force global reset by writing 0x6 or 0xE to 0xCF9 port with PCH ETR3 register bit [20] set. BUG=none BRANCH=none TEST=Verified platform global reset is working with MEI message or writing to PCH ETR3. Change-Id: I57e55caa6d20b15644bac686be8734d9652f21e5 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/16903 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-16soc/intel/skylake: Implement Global Reset MEI messageSubrata Banik
As per ME BWG, there are two mechanism to generate a Global Reset (resets both host and Intel ME), one is through CF9h IO write of 6h or Eh with "CF9h Global Reset" (CF9GR) bit set, PMC PCI offset ACh[20]. Another is to issue the Global Reset MEI message. Because any attempts to cause global reset without synchronizing the two sides might cause unwanted side effects, such as unwritten flash data that will get destroyed if the host were to cause a global reset without informing Intel ME firmware, the recommended method is to send a Global Reset MEI message when the following conditions are met: The PCH chipset firmware just needs to complete the Intel ME Interface #1 initialization and check the Intel ME HFSTS state if Intel ME is not in ERROR state and is accepting MEI commands then firmware should be able to use Global Reset MEI message to trigger global reset. Furthermore, if Intel ME is in ERROR state, BIOS can use I/O 0xCF9 write of 0x06 or 0x0E command with PCH ETR3 register bit [20] to perform the global reset. BUG=none BRANCH=none TEST=Verified Global Reset MEI message is able to perform platform global issue in ME good state. Change-Id: If326a137eeadaa695668b76b84c510e12c546024 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/16902 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-24 13:23:43 +0000