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2014-12-19nyan*: Add fast link training functionsJimmy Zhang
Some panels (including those on Big DVT) cannot work fine without link training before sending the video signals, especially multi-lane Full HD panels. We need to use the fast link training functions from kernel to support them. BRANCH=Nyan BUG=chrome-os-partner:28128, chrome-os-partner:28129 TEST=tested on nyan, nyan_big dvt. Vince verified on Full HD panels. Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Change-Id: Ifde8daf0ebdc6fb407610d3563f3311b2a72dbc4 Original-Reviewed-on: https://chromium-review.googlesource.com/196162 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Commit-Queue: Hung-Te Lin <hungte@chromium.org> Original-Tested-by: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit 992132ff3431fc7abba10cc8e910e36d4f3a3f7a) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I5ed091ae7a872fd674ab21f9f80267052fcd24b1 Reviewed-on: http://review.coreboot.org/7864 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-19fsp_baytrail: Initialize LPC pads in bootblock for port 80Martin Roth
Port 80h codes were coming out of bootblock and romstage scrambled, or were not coming out at all. Initializing the LPC signal pads as LPC fixes that issue. Change-Id: I16943513f2eb6fe8fa58766aaa82dac182440c34 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7802 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@gmx.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-19fsp_baytrail: Remove GPIO_NC1 #defineMartin Roth
The GPIO_NC1 #define was added to handle GPIOs that are not on func0. This is already handled elsewhere in the GPIO code, so is not needed. - Remove the single GPIO_NC1 from platforms using fsp_baytrail - Revert the GPIO_INPUT_PU_10k #define to remove the _func argument. Update everywhere this macro is called. - Remove GPIO_NC1 Change-Id: I32f337af7bc88eab821d9a8c375145b45718275f Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7849 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-19baytrail SOCs: Add missing comma in gpio.hMartin Roth
The GPIO_OUT_LOW #define was missing an internal comma in both soc/intel/baytrail and soc/intel/fsp_baytrail. Thanks to Werner Zeh for pointing this out. Change-Id: I2e5507058739e5fdc2c0e43e0380058458870e46 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7801 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Werner Zeh <werner.zeh@gmx.net>
2014-12-17baytrail: initialize backlight PWM frequencyAaron Durbin
In order to protect ourselves from the kernel driver not honoring or placing the correct frequency in the backlight register always set one. This code path picks 200Hz as the default if nothing is specified in device tree. It's somewhat arbitrary but that frequency is valid for all the eDP panel specs we've seen being used on baytrail devices. BUG=chrome-os-partner:28267 BRANCH=baytrail TEST=Built and booted in normal mode. Noted register write stuck. Original-Change-Id: Ifec29f0671e9f14ba57b9643c29d8bb2cd07eef5 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/196821 Original-Reviewed-by: Marc Jones <marc.jones@se-eng.com> (cherry picked from commit 2eaa650860ebbc838dbf8c1c1ca2259ac64141ac) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ifec29f0671e9f14ba57b9643c29d8bb2cd07eef5 Reviewed-on: http://review.coreboot.org/7845 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-17x86: Initialize SPI controller explicitly during PCH initDavid Hendricks
This ensures that SPI is ready when eventlog code is used. x86 platforms which use eventlog invoke elog_clear() in GSMI and elog_add_event_raw() when deciding the boot path based on ME status. For the SMM case spi_init() is called during the finalize stage in SMM setup. For the boot path case we can call spi_init() at the beginning of BS_DEV_INIT and it will be ready to use when the boot path is determined from the ME status. BUG=none BRANCH=none TEST=tested on Link (bd82x6x), Beltino (Lynxpoint), and Rambi (Baytrail) with follow-up patch Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: Id3aef0fc7d4df5aaa3c1c2c2383b339430e7a6a1 Original-Reviewed-on: https://chromium-review.googlesource.com/194525 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 173d8f08e867bab8c97a6c733580917f5892a45d) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ifaed677bbb141377b36bd9910b2b1c3402654aad Reviewed-on: http://review.coreboot.org/7756 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-12-17tegra124: modify panel init sequenceKen Chang
Panel datasheet defines some delay between PWM signal out and backlight enable. This change fixes the current sequence and makes the delays adjustable by dt setting. BRANCH=none BUG=chrome-os-partner:28008 TEST=Verified on Big DVT and Nyan/Norrin panels. Panel works fine with dev mode, and the measurement of power on sequence meets panel requirements. Original-Change-Id: If6015bbb6015a3b203d425f5e90f676ad786b5e8 Original-Signed-off-by: Ken Chang <kenc@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/196183 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit 2bbcaa7281222ffc0b4026e8b1eb4c210a8e308a) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Id6424f66eb8dc6adeb70eaa33df742f4e57983c3 Reviewed-on: http://review.coreboot.org/7776 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-12-17nyan*: enable CLAMP_INPUTSKen Chang
Enable pinmux clamp function to avoid pinmux conflict. For pins which are configured to tristate enabled, the inputs to the controller will be clamped to zero. This can be used to avoid pinmux conflicts since the tristate bit is set to 1 in the power-on-reset pinmux setting. With pinmux clamp enabled, we need to configure all the input pins to tristate disabled. BUG=chrome-os-partner:27091 BRANCH=None TEST=built and booted successfully, display worked fine. Original-Change-Id: Id79a717f2025c812908c7152d439351208aee8d2 Original-Signed-off-by: Ken Chang <kenc@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/194060 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit c95d6fe79810612cfad721667657cdcb87068d23) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I1b23df8b90f83ea2b2c08c4364d90fe71533a5a0 Reviewed-on: http://review.coreboot.org/7775 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-12-17fsp_baytrail: Add code to read GPIOs in romstageMartin Roth
- Build gpio.c into romstage - Add functions to translate the GPIO # to a pad #, then return the value read from the GPIO. - Add functions to configure the GPIO - Function, Pull up/down, pull strength, Input/Output, and Output level. Change-Id: Ic37dfc9a74a598023bdf797d31087428adec176a Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7796 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@gmx.net>
2014-12-17ARM: Use LPAE for Virtual Address TranslationDaisuke Nojiri
This change introduces LPAE for virtual address translation. To enable it, set ARM_LPAE. Boot slows down about 4ms on Tegra124 with LPAE enabled. TEST=Booted nyan with and without LPAE. Built nyan_big and daisy. BUG=None BRANCH=none Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@google.com> Original-Change-Id: I74aa729b6fe6d243f57123dc792302359c661cad Original-Reviewed-on: https://chromium-review.googlesource.com/187862 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit 6d8c8b2bbdc70555076081eb3bfaabde7b4a398f) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I8980375c14758af35f7d5ec5244be963e5462d8a Reviewed-on: http://review.coreboot.org/7749 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-12-17tegra124: change PLLD VCO calculation algorithmKen Chang
The current algo sets dc shift clock divider to 5 and PLLD DIVP to 0, this is causing VCO out of the characterized range for some panels. This CL changes the dc shift clock divider to 1 and calculates a proper DIVP to have the VCO inside the characterized range, i.e., 500MHz ~ 1000MHz. BRANCH=none BUG=none TEST=Verify on below panels the pixel clock frequencies are correct. 1. AUO B133XTN01.3 (69.5 MHz) pixelclk(MHz), pll_d(MHz), m/n/p without: 69.5 695 12/695/0 with: 69.5 139 3/139/2 2. AUO B140HTT01.0 (141 MHz) pixelclk(MHz), pll_d(MHz), m/n/p without: VCO (1410000000) out of range. Cannot support. with: 141 282 2/94/1 3. LG LP140WH8 (76.32 MHz) pixelclk(MHz), pll_d(MHz), m/n/p without: 76.32 763.2 5/381/0 with: 76.3125 152.625 8/407/2 4. N116BGE-EA2 (76.42 MHz) pixelclk(MHz), pll_d(MHz), m/n/p without: 76.40 764 3/191/0 with: 76.375 152.75 12/611/2 Original-Change-Id: Id4b3a4865acde37a97d7346ec88406f5237304eb Original-Signed-off-by: Ken Chang <kenc@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/195534 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit 1b56566786aa86c14f691fa3858b878f27b6b4de) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ia9de93420e60323f143a42db842febdd3706fe44 Reviewed-on: http://review.coreboot.org/7773 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-12-16tegra124: Allow "best" PLLD parameters for unmatched pixel clock.Hung-Te Lin
The pixel clock for some panel (ex: CMN N116BGE-EA2: 76420000) cannot be matched by our PLLD params finding algorithm, after VCO/CF limitations are applied. To support these panels, we want to allow "best matched" params. BRANCH=nyan BUG=none TEST=emerge-nyan_big coreboot chromeos-bootimage; emerge-nyan coreboot chromeos-bootimage; # Successfully brings up display on Nyan_Big EVT2 and Nyan Norrin. Original-Change-Id: If8143c2062abd2f843c07698ea55cab47bf1e41a Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/195327 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 8aa66e659e3c60296f05e59b4343496a850ea019) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I623db44de35fecee5539e4d72f93f28b5fa0b59c Reviewed-on: http://review.coreboot.org/7771 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-12-16tegra124: Always enable DC when attaching SOR.Hung-Te Lin
We found that without enabling DC in tegra_dc_sor_enable_dc, kernel would have problem showing the text console before graphics interface is initialized, for example "chromeos factory install shim (text only)" or the "splash screen". BRANCH=none BUG=chrome-os-partner:28082 TEST=emerge-nyan coreboot chromeos-bootimage Boots factory install shim and see text console. Original-Change-Id: I6fce963ceddd125dd52789d2ec843cc2ee05f1f5 Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/195388 (cherry picked from commit 375a86be9b23650cd96e46b07c7a0b5c10970797) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ib75e3ffac9b216c7486845cb8459dd8952d51fe6 Reviewed-on: http://review.coreboot.org/7770 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-12-16nyan*: debug: Add sor registers dump functionJimmy Zhang
Dump all SOR registers for debug purpose. By default, this function is not being built in. BRANCH=none BUG=chrome-os-partner:27413 TEST=build nyan and nyan_big. Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Change-Id: I7f44709b8572b9eac33c2193b92a65bf2b22aa76 Original-Reviewed-on: https://chromium-review.googlesource.com/194738 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Commit-Queue: Tom Warren <twarren@nvidia.com> Original-Tested-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit d08c0f7c5e8ac094987b09fae96e8133ed9c08c5) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I1341bbbd0ea6277e5a1b286d6f088f2961070416 Reviewed-on: http://review.coreboot.org/7769 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-12-16tegra124: clock: Enforce PLL constraints for VCO and CFJulius Werner
This patch adds some documentation to the additional PLL divisor constraints on the intermediary VCO and CF values that we just found out about. PLLC divisors for some oscillators had to be adjusted accordingly. It also adds a new clock_get_pll_input_khz() function to replace clock_get_osc_khz() in cases where you want to factor in the built-in predivider for 38.4 and 48 MHz oscillators. BUG=None TEST=Still boots. Original-Change-Id: Ib6e026dbab9fcc50d6d81a884774ad07c7b0dbc3 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/194474 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit 3f1f565baf100edcd486055e4317c675c882396f) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I091f42bf952a4b58ef2c30586baa5bf7496fa599 Reviewed-on: http://review.coreboot.org/7768 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-12-16nyan*: Set SOR_NV_PDISP_SOR_DP_SPARE0 registerJimmy Zhang
This register needs to be set properly during display init. BRANCH=none BUG=chrome-os-partner:27413 TEST=build nyan and nyan_big. nyan display works fine. nyan_big display works as well. However, the mode setting needs to be based on either devicetree or EDID. Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Change-Id: I93c69d8042a3f3c19f4e24801423b73246e37031 Original-Reviewed-on: https://chromium-review.googlesource.com/194739 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Commit-Queue: Hung-Te Lin <hungte@chromium.org> Original-Tested-by: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit ee9a3c472c5621edebefcc8882582c6fc01255e2) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ie642a008eaf6c4ab68ede1dde98ff4268f51fc9c Reviewed-on: http://review.coreboot.org/7767 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-12-16nyan*: merge a couple of sor setting difference from kernel driverJimmy Zhang
BRANCH=none BUG=chrome-os-partner:27413 TEST=build nyan and nyan_big. nyan display works fine. nyan_big display still does't work until all related patches are built in. (CL:194739) Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Change-Id: Ic5d977f695be127693f1ecc3ba52d478f524d20f Original-Reviewed-on: https://chromium-review.googlesource.com/194737 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Commit-Queue: Hung-Te Lin <hungte@chromium.org> Original-Tested-by: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit ef3208d8ff3c3dcfaeda9c0146bf1ae920682dea) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ide1cd28ecc0ae1cd4d8603a52975592daee4bce8 Reviewed-on: http://review.coreboot.org/7766 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-12-16nyan*: Apply sor fix from kernel dc driverJimmy Zhang
Correct SOR attaching sequence. https://chromium-review.googlesource.com/190300 BRANCH=none BUG=chrome-os-partner:27413 TEST=build nyan and nyan_big. nyan display works fine. nyan_big display still doesn't work until all related patches are built in. (CL:194737 and CL:194739) Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Change-Id: I8aaf65db90e5e45bd9097c9d38b231bd7d41d997 Original-Reviewed-on: https://chromium-review.googlesource.com/194403 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Commit-Queue: Hung-Te Lin <hungte@chromium.org> Original-Tested-by: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit fea9d288b98dcc6fc32dc93212fa7c4185603646) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I6646816809e29c63de65caa7e7146cd3d02902cf Reviewed-on: http://review.coreboot.org/7765 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-12-16tegra124: Initialize display panel by EDID.Hung-Te Lin
Tegra124 family products may want to use many different display panels with various timing settings. To support them, we should initialize display panel by EDID instead of hard-coded values. BUG=none TEST=emerge-nyan coreboot chromeos-bootimage BRANCH=none Original-Change-Id: Ib125a7f9cb1e6c8cf2d79e0baab525acfd1b7a6e Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/192730 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 43ecd473419aa0fbdd22487416b0b6cfea6a20d1) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I6af47db113035e9440e663a769318776c7b6b70b Reviewed-on: http://review.coreboot.org/7764 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-12-16CBMEM console: Fix boards with BROKEN_CAR_MIGRATEKyösti Mälkki
There is no need to call cbmemc_reinit() exclusively in romstage, that is done as part of the CAR migration of cbmem_recovery(). CBMEM console for romstage remains disabled for boards flagged with BROKEN_CAR_MIGRATE, but with this change it is possible to have it for ramstage. Change-Id: I48c4afcd847d0d5f8864d23c0786935341e3f752 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7592 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-12-16Intel FSP: Move to DYNAMIC_CBMEMKyösti Mälkki
Flag the boards with BROKEN_CAR_MIGRATE, as testing for EARLY_CBMEM_INIT is not enough to disable CBMEM console for romstage on these platforms. To have CBMEM early in ramstage, define get_top_of_ram() on sandy/ivy. Change-Id: Ieefc12099a0e043eb1a7e14bdc7c6e3d209b3d8f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7468 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-12-16i2c: Replace the i2c API.Gabe Black
The new API is in use in depthcharge and is based around the "i2c_transfer" function instead of i2c_read and i2c_write. The new function takes an array of i2c_seg structures which represent each portion of the transfer after a start bit and before the stop bit. If there's more than one segment, they're seperated by repeated starts. Some wrapper functions have also been added which make certain common operations easy. These include reading or writing a byte from a register or reading or writing a blob of raw data. The i2c device drivers generally use these wrappers but can call the i2c_transfer function directly if the need something different. The tegra i2c driver was very similar to the one in depthcharge and was simple to convert. The Exynos 5250 and 5420 drivers were ported from depthcharge and replace the ones in coreboot. The Exynos 5420 driver was ported from the high speed portion of the one in coreboot and was straightforward to port back. The low speed portion and the Exynos 5250 drivers had been transplanted from U-Boot and were replaced with the depthcharge implementation. BUG=None TEST=Built and booted on nyan with and without EFS. Built and booted on, pit and daisy. BRANCH=None Original-Change-Id: I1e98c3fa2560be25444ab3d0394bb214b9d56e93 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/193561 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 00c423fb2c06c69d580ee3ec0a3892ebf164a5fe) This cherry-pick required additional changes to the following: src/cpu/allwinner/a10/twi.c src/drivers/xpowers/axp209/axp209.c Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I691959c66308eeeec219b1bec463b8b365a246d7 Reviewed-on: http://review.coreboot.org/7751 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-12-15tegra124: set MOT bit for I2C-over-AUXKen Chang
According to DP version 1.2a, The MOT (Middle-of-Transaction) bit must be set when the I2C transaction does not stop with the current AUX transaction. Thus the correct steps for an I2C read shall be: 1. I2C command write with MOT set to 1 2. I2C command read to the same address with MOT set to 0 BUG=chrome-os-partner:27679 TEST=EDID data read from LP140WH8 panel is correct while it's a repeated pattern of the first 16 bytes without this CL BRANCH=none Original-Change-Id: I0526beffb8852fbbe0eb5bb80e370261617a59b8 Original-Signed-off-by: Ken Chang <kenc@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/194915 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit 466ab0e00744f79ae3720474140d95e5f0828de9) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ic8ad38b4b08989dd7178d59151e1e276b8a58439 Reviewed-on: http://review.coreboot.org/7763 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-15tegra124: Setup clock PLLD by approximating display panel pixel clock.Hung-Te Lin
PLLD, the clock for display, was previously hard-coded to 306MHz. To support more different panels, we should calcualte PLLD by panel pixel clock configuration. Note existing pixel clock configurations for nyan* boards won't work (they used to rely on hard-coded approximated values) so the device trees are also modified. BRANCH=none BUG=chrome-os-partner:25933 TEST=emerge-nyan_big coreboot chromeos-bootimage See panel correctly initialized and got DEV screen. Original-Change-Id: I8d592f0cc044e7c4e4803c45955642e791210ad3 Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/193565 (cherry picked from commit 4f9b793633ebb2d104b0544e3b72fa0d105951c4) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ib2cabbad60af010e872505e888eab485ba8c2916 Reviewed-on: http://review.coreboot.org/7762 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-15tegra124: Release DMA channel at end of transactionDavid Hendricks
This adds a missing dma_release() at the end of DMA transfers. It probably doesn't matter since we don't do many DMA transfers, though I wouldn't want to hit some corner case with EFS and eventlog. BUG=none BRANCH=none TEST=tested on nyan Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I79b30455babe75a13aac827caac88bf7053ec9e4 Original-Reviewed-on: https://chromium-review.googlesource.com/194479 Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: David Hendricks <dhendrix@chromium.org> (cherry picked from commit dc7dc1d25bd88873b4c1198a6f3723d27c914ddc) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I8c5da4e104328fd8bce71942e6eda458a37bfe06 Reviewed-on: http://review.coreboot.org/7761 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-15tegra124: Use correct mask for APB bus widthDavid Hendricks
It worked earlier since the APB and AHB bus widths occupy the same bits in their respective registers. BUG=none BRANCH=none TEST=tested on Nyan Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I9b18c648c60dcc4ad62ca1f514d253f8cccaeee7 Original-Reviewed-on: https://chromium-review.googlesource.com/194478 Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 1d912302e9dcc9c6ba69e15434bb1841e1196208) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I2ea7ac83d3501876df52018aed467ec33074817e Reviewed-on: http://review.coreboot.org/7760 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-15nyan: Enable the cbmem console on nyan and allocate space for it in SRAM.Gabe Black
This change takes about 8K of space away from the cbfs cache and repurposes it for the cbmem console buffer. This is a little more than twice the space we currently need for the bootblock and ROM stage to give us some room to grow and for extra debug output if needed. BUG=None TEST=Built and booted on nyan. Checked the cbmem output. BRANCH=None Original-Change-Id: I6543bf5efddcf2377528a273f846b8090cd8be55 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/193169 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 32e9ea6f9ecaa9b5441c91acab96514222f3af2c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ia9e5cc7a4b561bd89137cdc8b594584b272d9fab Reviewed-on: http://review.coreboot.org/7757 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-15tegra124: More improvements to the clock initialization macros.Gabe Black
Consolidate the register setting clrsetbits_le32 call to simplify the macros. Add a check for bits of the divisor being dropped. The clock source registers will throw away bits that aren't supported, so we can check for divisor overflow by checking for dropped bits. BUG=None TEST=Purposefully tried to set a clock to a rate which overflows its divisor. Verified that the check triggered. Booted on nyan. Verified the TPM i2c bus frequency was still correct. BRANCH=None Original-Change-Id: I3b1b6ba57f6b7729f303d15a16b685a48751d41f Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/193348 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 9cd79dd974d8a3c31398f8fbd62750b194867891) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Id4d8ecfeff52737cdd68999028b37cbdedb0d116 Reviewed-on: http://review.coreboot.org/7738 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-15tegra: spi: Read the command1 register to ensure the write to it completes.Gabe Black
To ensure that the command1 write which sets the "go" bit completes before other reads to the device. Otherwise, there's a race condition where those register values might still have their values from the last transfer. With different SPI clock frequencies, that could lead to spi_delay being told there were negative bytes still to send. Its expected delay would wrap to a negative value, that was passed to udelay, and the system would sit there for 4 seconds not doing anything. BUG=None TEST=Built and booted on nyan. Set the SPI bus frequency to a value which was causing the 4+ second delay and verified that it no longer happened. BRANCH=None Original-Change-Id: I8b4090efc69f34d0413e3f63c59c1825dd151cec Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/193347 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit d7ea9febdf2c5942f81607ee6ded786c9a8954bb) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I095bfc745eda37b8e666475ceb41684152f3709a Reviewed-on: http://review.coreboot.org/7737 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-15tegra124: A couple clock fixes.Gabe Black
This fixes two problems with the clock configuration on tegra124. First, the macro which set up the i2c clocks tried to account for the fact that the i2c divisor's lsb represents 1.0 where it normally represents 0.5 by multiplying the target frequency by 2. That doesn't work, unfortunately, because the divisor is actually n + 1, and what n + 1 means depends on where the one's place is in the divisor. Also, when calculating the divisor, the standard C division operator uses truncation to deal any remainder which tends to make the divisor smaller. That has the effect of making the output frequency higher than what was requested. Since it's usually safer to undershoot a frequency than overshoot it, this change makes those divisions round up instead. Finally, the hand tuned temporary UART clock configuration was adjusted so that it still ends up with the same divisor. Without that, very early output from the bootblock is garbled, specifically the coreboot welcome banner, build timestamp, etc. BUG=chrome-os-partner:27220 TEST=Built and booted on nyan. Used a logic analyzer to verify that the TPM i2c bus ran at 400KHz instead of 660KHz, and that the divisor was the expected value. Measured boot time with and without EFS and verified that there was no change. Spot checked the output for errors and verified that none of the bootblock output was garbled. BRANCH=None Had to add the stdlib.h from 89ed6c that hadn't been merged correctly. Original-Change-Id: I7e948c361ed4bf58c608627d32f2e3424faea1fb Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/193362 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 164f7010a47d3bbdbc8bb572106140ae186f3807) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I317b66eda929c0e5a5832adca267b8b54c6aae34 Reviewed-on: http://review.coreboot.org/7736 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-15tegra124: Add tegra_dc_i2c_aux_read to allow reading EDID.Hung-Te Lin
To read EDID, we need to access I2C via DP AUX channel. BRANCH=none BUG=chrome-os-partner:25933 TEST=emerge-nyan coreboot chromeos-bootimage Original-Change-Id: I2666b5d46843485b79265a537f19bd8eab5e1a26 Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/188858 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 8f8e98ff5038b57f89332aee75573095c3933dd2) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I5b1b6ab2940c8265483059fd94a2c4db2a41144a Reviewed-on: http://review.coreboot.org/7735 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-15tegra124: Skip display init when vboot says we don't need it.Gabe Black
If EFS is enabled and vboot didn't tell us it's going to use the display, we can skip initializing it and save some boot time. BUG=chrome-os-partner:27094 TEST=Built and booted on nyan without EFS in recovery mode and normal mode. Built and booted on nyan with EFS in recovery mode and normal mode. Verified that in normal mode with EFS the display initialization was skipped and boot time was essentially the same as when display initialization was simply commented out. BRANCH=None Original-Change-Id: I1e2842b57a38061f40514407c8fab1e38b75be80 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/192544 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit a672d18c3570e6991a1c1c0089697112a4cd71d0) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I95e8bd7a447876174305f755cc632365ed6f5a30 Reviewed-on: http://review.coreboot.org/7734 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-09spi: Eliminate the spi_cs_activate and spi_cs_deactivate functions.Gabe Black
They were only used internal to the SPI drivers and, according to the comment next to their prototypes, were for when the SPI controller doesn't control the chip select line directly and needs some help. BUG=None TEST=Built for link, falco, and rambi. Built and booted on peach_pit and nyan. BRANCH=None Original-Change-Id: If4622819a4437490797d305786e2436e2e70c42b Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/192048 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 1e2deecd9d8c6fd690c54f24e902cc7d2bab0521) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ida08cbc2be5ad09b929ca16e483c36c49ac12627 Reviewed-on: http://review.coreboot.org/7708 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-12-09spi: Remove the spi_set_speed and spi_cs_is_valid functions.Gabe Black
spi_set_speed was never implemented, and spi_cs_is_valid was only implemented as a stub and never called. BUG=None TEST=Built for rambi, falco, and peach_pit. BRANCH=None Original-Change-Id: If30c2339f5e0360a5099eb540fab73fb23582905 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/192045 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 98c1f6014c512e75e989df36b48622a7b56d0582) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Iebdb2704ee81aee432c83ab182246d31ef52a6b6 Reviewed-on: http://review.coreboot.org/7707 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-12-09spi: Factor EC protocol details out of the SPI drivers.Gabe Black
The SPI drivers for tegra and exynos5420 have code in them which waits for a frame header and leaves filler data out. The SPI driver shouldn't have support for frame headers directly. If a device uses them, it should support them itself. That makes the SPI drivers simpler and easier to write. When moving the frame handling logic into the EC support code, EC communication continued to work on tegra but no longer worked on exynos5420. That suggested the SPI driver on the 5420 wasn't working correctly, so I replaced that with the implementation in depthcharge. Unfortunately that implementation doesn't support waiting for a frame header for the EC, so these changes are combined into one. BUG=None TEST=Built and booted on pit. Built and booted on nyan. In both cases, verified that there were no error messages from the SPI drivers or the EC code. BRANCH=None Original-Change-Id: I62a68820c632f154acece94f54276ddcd1442c09 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/191192 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 4fcfed280ad70f14a013d5353aa0bee0af540630) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Id8824523abc7afcbc214845901628833e135d142 Reviewed-on: http://review.coreboot.org/7706 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-12-09UCB RISCV: Switch to DYNAMIC_CBMEMKyösti Mälkki
Change-Id: Iaaf68fd19f7b9a5b6849fffde3a9c68cb7862367 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7619 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-12-09fsp platfoms: add prototype & consolidate main entry-pointMartin Roth
- In '-ffreestanding' main() is just as any other function and so it needs a type-signature. Fixes a clang warning. - Bay Trail and Rangeley have the updated romstage.c with the code moved into the chipset, put the prototype in romstage.c. - The sandybridge code has not been updated, so the prototype for it goes into chipset_fsp_util.h, next to the prototype for romstage_main_continue. - Correct the return value of baytrail main() from void * to void and remove the unnecessary asmlinkage tag. I'm surprised that this didn't generate a warning... Change-Id: I85ac0797d1e55d2b7ffdca039a52820d7827e704 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7724 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-12-08intel/baytrail: Spelling fixesMartin Roth
Change-Id: Ideb58634a029d55746421ad1ea4b80811bca403c Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7705 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-08intel/fsp_baytrail: Spelling fixesMartin Roth
Change-Id: Ica9e3a91718a7e490ff80e5029fc29650355eb47 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7704 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-08samsung/exynos5420: Spelling FixesMartin Roth
Change-Id: I966645c83ae78943a7dbb9dc05af4fded6f4e5b5 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7703 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-08intel/broadwell: Spelling fixesMartin Roth
Change-Id: I2f970c6970b4996fcefbde89332210f5a1afe836 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7702 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-06soc/qualcomm/ipq806x/Kconfig: Fix indent styleEdward O'Callaghan
Change-Id: I72c9c1f5811fafaeec9572b05726d5677e2c28b1 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7669 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-05fsp_baytrail: Update function disable codeMartin Roth
- The EDS has the function disable bit for eMMC incorrectly listed as 8. Changing it back to the correct bit 11. - The FSP will disable functions that it is told are disabled, so coreboot code that disables the functions is redundant. Removing it. Change-Id: I95c31d92d3af5182ddf7fd47f651bbb61cdedb82 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7653 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-12-05fsp_baytrail: Kconfig update for Gold 3 FSPMartin Roth
The documentation for the FSP gives the name as BAYTRAIL_FSP.fd instead of the old FvFsp.bin. Change-Id: I69c7c5ff49afd6552612cf50c9ca9b30cfb003e2 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7648 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-12-05fsp_baytrail: Update microcode for Gold 3 FSP releaseMartin Roth
New microcode for Bay Trail I B2/B3 and D0 parts was released in the Gold 3 Bay Trail FSP release. Change the microcode size to an area instead of the exact size of the patches. This will hopefully reduce updates to the microcode size. Change-Id: I58b4c57a4bb0e478ffd28bd74a5de6bb61540dfe Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7647 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-12-05FSP platform microcode: Update to remove Kconfig variableMartin Roth
Move the Kconfig variable into a .h file - this does not need to be in Kconfig. Change-Id: I1db20790ddb32e0eb082503c6c60cbbefa818bb9 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7646 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-12-05ipq8064: Make clock code build in corebootVadim Bendebury
Include clock.c in the appropriate coreboot stages, modify the code to build cleanly. Use proper pointer cast in .h files. BUG=chrome-os-partner:27784 TEST='emerge-storm coreboot' still succeeds Original-Change-Id: I227c871b17e571f6a1db3ada3821dbb1ee884e59 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/196407 (cherry picked from commit 75decceccd97298974891bb98b796eccfe11f46c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I7d44464d4ca8153e84407fc05a25e2e79e74901e Reviewed-on: http://review.coreboot.org/7271 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-12-05ipq8064: prepare UART driver for use in corebootVadim Bendebury
These driver needs to be in src/lib, and the include file needs to be renamed to avoid collision with the top level uart.h. BUG=chrome-os-partner:27784 TEST=emerge-storm coreboot still works Original-Change-Id: Ie12f44e055bbef0eb8b1a3ffc8d6742e7a446942 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/196393 (cherry picked from commit c5618fd418642f5b009582f5f6bc51f7c9d54bec) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I5e25ae350ac5e71b47a0daef078b03cc5ac35401 Reviewed-on: http://review.coreboot.org/7270 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-05fsp_baytrail: remove register option for TSEG sizeMartin Roth
Set the UPD entry based on the Kconfig value instead of having two separate places that the value needs to be set. Change-Id: I3d32111b59152d0a8fc49e15320c7b5a140228a6 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7490 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
2014-12-05fsp_baytrail: update printk to use FSP_INFO_LEVELMartin Roth
Update the printk statements to use FSP_INFO_LEVEL instead of BIOS_DEBUG. These values are currently identical, but by using the second #define, it lets them all be changed as a unit. This can be overridden for a particular platform by adding a #define in chipset_fsp_util.c. Change-Id: Idbf7e55090230ec940c7c8cd3ec8632461561428 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7520 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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