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2017-10-16intel/common: CAR setup CQOSNaresh G Solanki
Enable CQOS on Geminilake. In Apololake, CBM_LEN is 0x7. Whereas the same in Geminilake is 0xF. Thus get CBM_LEN using cpuid instruction & generate CBM_LEN_MASK. Later use the CBM_LEN_MASK when writing to IA32_L2_MASK_* to set right bits. BUG=None TEST= Build for Geminilake platform i.e., glkrvp & check for successful CAR setup. Even verified the same on APL platform i.e., on Reef Change-Id: Ic736dba1a46629ff5bf3183082799c0c1468e6d9 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com Reviewed-on: https://review.coreboot.org/21701 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-16soc/amd/common: Clean up file includesFrank Vibrans
Remove unnecessary header file includes. Change-Id: I9ad9e86f3c75903e278e898602caec04351f64b6 Signed-off-by: Frank Vibrans <frank.vibrans@scarletltd.com> Reviewed-on: https://review.coreboot.org/21989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-16soc/amd/stoneyridge: Check UART indexMarshall Dawson
The Stoney Ridge APU has only two internal UARTs. Add checks for invalid settings. When enabling the UART, return if the console is on any UART not equal 0 or 1. The base address returned is 0 if an invalid configuration is used. All callers check the return value before using the returned value. Finally, provide an assert at the earliest availability of the console to get the notice into the cbmem console. BUG=b:62201567 TEST=Build with UART = -1, 0, 2. Inspect objdump and boot to OS. Build without ST UART and inspect with objdump. Change-Id: I9432571712bae15a604f4280ea5e0f81fd68604d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-16soc/amd/stoneyridge: Update AMD firmware placement optionsMartin Roth
- Don't force the selection of placing the firmware outside of cbfs when using vboot. - Set a prompt to allow the option of placing it outside of cbfs. - Leave all Kconfig defaults the same. - Place the AMD firmware directory table in the specified location even when using the 'outside of cbfs" option. - Print where the firmware is being placed when placing it outside of cbfs. BUG=b:65484600 TEST=Assign PSP firmware location, build & test. Firmware shows up inside CBFS. Set 'outside of cbfs' option, verify firmware gets written to the correct location. Change-Id: Ia8258b5c2ecfaaa42d623e3376ec3233115aed58 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21867 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-15amd/stoneyridge: Add function to find PmControl registerMarshall Dawson
Find the PmControl register's I/O address by checking the hardware in PMx62. Don't rely on the address being the coreboot default. PmControl is the first register in the AcpiPm1CntBlk. Change-Id: Ibb608dcaa7801af067d6edd86f92c117c2ac08a6 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21882 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-15amd/soc/common: Print an error if an AGESA callout isn't supportedMarc Jones
Let the developer or user know that a callout isn't supported. Change-Id: I73a6c6930a6661627ad76e27bbb78be99e237949 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/21998 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-15soc/amd/stoneyridge/lpc.c: Refactor lpc_enable_childrens_resourcesRichard Spiegel
Factor out the code into separate functions. Create set_lpc_resource that will set the resource for a particular child while lpc_enable_childrens_resources finds all children and calls set_lpc_resource for each child found. This creates well defined boundaries for each function. Change-Id: I265cfac2049733481faf8a6e5b02e34aadae11f5 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/21904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-14intel/skylake: Use Sata related registers from devicetreeYouness Alaoui
Enable the use of the SataPortsEnable and SataPortsDevSlp registers which were being ignored from the devicetree and were not affecting the resulting UPD parameters. SataPortsEnable was only being copied for the first SATA port, while the other ports were left ignored. Change-Id: Iae70a4d6375fa5d1b05ee89f6b97c65dbbf28dda Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/21958 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-10-13amd/stoneyridge: Make all AGESA reset requests immediateMarc Jones
The AGESA RESET_WHENEVER request were never doing a reset in coreboot. We don't have a way to collect a whenever and reset at some later time, so just do the reset immediately. BUG=b:64719937 BRANCH=none TEST=Check AGESA reset request in booblock does a reset in the serial console or ec console. Change-Id: If2654ec0c5c5dbdcea6fc9374371c3388d29fdc7 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/21978 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-12intel/common/pmc: Disable all GPEs during pmc_initFurquan Shaikh
If GPEs are not cleared during pmc_init, it could result in issues if standard wake events are generated while coreboot is initializing. e.g. (Observed on soraka): 1. Suspend to S3 2. Lidclose 3. Lidopen 4. EC wakes up the host using WAKE# pin 5. On wakeup, pmc_init occurs which does not clear GPEs 6. MP init enables SMI 7. In order to add wake event to elog, coreboot sets wake mask on the EC, which causes the EC to assert WAKE#. 8. Since WAKE# is asserted, it results in an SMI#. However, EC does not de-assert WAKE# until host queries and clears the host event bit (which does not happen since coreboot is stuck in handling the SMIs). This is one of the issues that can occur when GPEs are unnecessarily enabled in coreboot. Before the move to PMC common library, SKL PMC driver set all GPEs to 0 and hence this issue did not occur. This change explicitly disables all GPEs during pmc init in order to avoid any side-effects. BUG=b:67712608 TEST=Verified that device resumes fine using lidclose/lidopen to suspend and resume. Change-Id: Ic5be02a23a8dbf43c4d7adf00251639ded4a94c9 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21969 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-12soc/intel/common: Clean up PMC library GPE handling APIFurquan Shaikh
1. Update gpe handling function names to explicitly mention if they are operating on: a. STD GPE events b. GPIO GPE events c. Both 2. Update comment block in pmclib.h to use generic names for STD and GPIO GPE registers instead of using any one platform specific names. BUG=b:67712608 Change-Id: I03349fe85ac31d4215418b884afd8c4b531e68d3 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21968 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-12soc/intel/cannonlake: add length information for communitiesBora Guvendik
TEST = Boot to OS, check if pinctrl probed successfully Change-Id: Ib20c955d535cd9c48175b4d3934b4699b6186874 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/21974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2017-10-12soc/intel/cannonlake: Add ACPI platform sleep capabilityVaibhav Shankar
Add the required ACPI sleep states Change-Id: I7750062554f087e4f88da56790e4122d5fa20529 Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/21975 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2017-10-12soc/amd/stoneyridge: Clean up sata.cRichard Spiegel
Clean up ahci_ptr declaration. Remove incorrect PCI device IDs. BUG=b:62200375 Change-Id: I9058d9102fc8ea0bd03ea089ba98da4590dd3533 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/21973 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-12intel/fsp_broadwell_de: Add timestamp functionalityWerner Zeh
Add a little code to enable timestamps on FSP based implementation of Broadwell-DE. I have tested it by reading back the timestamps with cbmem utility once the board has booted into Lubuntu. Change-Id: Idaa65a22a00382bf0c37acf2f5a1e07c6b1b42d9 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/21932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-12soc/intel/skylake: Enable bus master for sataKane Chen
The bus master needs to be enabled so that the busy bit in AHCI PORT_TFDATA will be cleared by controller when depthcharge tries to wait for sata to complete spin-up during AHCI init. Otherwise, the timeout will happen and cause 5 seconds delay in depthcharge. BUG=b:37639063 BRANCH=none TEST=verify that the sata timeout is gone in depthcharge Change-Id: I19eadbb2943fda8a5babc82ca87b1ecaab5e2ed8 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/21890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-10-11soc/intel/cannonlake: Change default UART number to 2Lijian Zhao
Set default UART number to 2 if 32bit PCI got selected, the proper debug print can be seen from serial port in case of switch between platforms, especially when change to lpss uart from legacy uart or vise versa. Change-Id: If2e0e8c8ac86e49a245f3d1d4722d40be9c01e25 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21544 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-10soc/intel/skylake: Fix broken suspend/resume for deep S3Furquan Shaikh
Change d3476809 (soc/intel/skylake: Add support in SKL for PMC common code) changed the logic for obtaining previous sleep state by unconditionally checking for PWR_FLR and SUS_PWR_FLR. In case of deep S3, SUS_PWR_FLR is set in gen_pmcon_b (just like resume from deep S5/G3) and hence the check for power failure should be done only when WAK_STS bit is not set. This is necessary to differentiate wakes from deep S3 and G3. This change restores the original logic by performing power failure check only in cases where WAK_STS bit is not set. BUG=b:67617726 TEST=Verified following: 1. When WAK_STS bit is not set and SUS_PWR_FLR is set, coreboot correctly identifies that the system prev sleep state was S5. 2. When WAK_STS bit is set and SUS_PWR_FLR is set, coreboot correctly identifies that the system prev sleep state was S3. Change-Id: Ic97bbc9911ba34aa21f4728c77fc20c5bb08f6f9 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-09soc/intel/*lake: Load vbt when it's neededPatrick Georgi
That removes the need for another global variable. Change-Id: I25e12ba724836de4c8afb25cd347cafe6df8cea9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/21907 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-06soc/intel/skylake: use locate_vbt directly instead of calling a wrapperPatrick Georgi
Change-Id: I65c423660ab1778f5dd9243e428a4d005bd1699a Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/21898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-06soc/intel/common: refactor locate_vbt and vbt_getPatrick Georgi
Instead of having all callers provide a region_device just for the purpose of reading vbt.bin, let locate_vbt handle its entire life cycle, simplifying the VBT access API. Change-Id: Ib85e55164e217050b67674d020d17b2edf5ad14d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/21897 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-06soc/intel/common: refactor locate_vbtPatrick Georgi
All callers of locate_vbt just care about the file content and immediately map the rdev for its content. Instead of repeating this in all call sites, move that code to locate_vbt. Change-Id: I5b518e6c959437bd8f393269db7955358a786719 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/21896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-06soc/intel/common: Allow overriding CBFS filename of VBTPatrick Georgi
When reusing the same image across multiple devices, they sometimes need different VBTs, so provide a hook for mainboard code to specify which file is required. Change-Id: Ic7865dc0e0c9ea3077b749d9d0482079877e9c4f Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/21724 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-06soc/intel/cannonlake: Enable MRC cacheLijian Zhao
Enable MRC cache by default. TEST=Warm reset and check coreboot serial log, MRC related log can be seen. Change-Id: I76ece361867737c01cc848c24d8893d43a3d292e Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-06soc/intel/cannonlake: reduce bootblock sizeAaron Durbin
Reduce the bootblock size to 16KiB from the default 64KiB. Not all that space is necessary. Change-Id: I5c15d0af0f85282b84c8983f0a015aeb45c00a07 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-10-06soc/intel/common: remove invalid path from Kconfig includeAaron Durbin
The src/soc/intel/common/basecode/Kconfig path does not exist. Remove the inclusion of the invalid path. Change-Id: Icbd8f310cad4246b72bc869bcf4a089ae2f0c5a3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-10-05soc/intel/cannonlake: Add all the SOC level DSDT tablesLijian Zhao
Add all the SOC level DSDT tables, reference from skylake/kabylake. Change-Id: Ia72bbe87b32d37db01f8768bd8447cb6ee1567a9 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-05soc/intel/skylake: Add support in SKL for PMC common codeShaunak Saha
Change-Id: I3742f9c22d990edd918713155ae0bb1853663b6f Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/20499 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-05soc/intel/common/block: Manage power state variable from common PMC blockShaunak Saha
This patch helps managing power state variables from within the library. Adds migrate_power_state which migrates the chipset power state variable, reads global power variable and adds it in cbmem for future use. This also adds get_soc_power_state_values function which returns the power state variable from cbmem or global power state variable if cbmem is not populated yet. Change-Id: If65341c1492e3a35a1a927100e0d893f923b9e68 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/21851 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-05soc/amd/stoneyridge: Pass firmware dir location to amdfwtoolMartin Roth
The amdfwtool now outputs firmware that is correctly built for the new location. BUG=b:65484600 TEST=Assign PSP firmware location, build & test. Change-Id: Ifa2e99ea031fc0d9f165ae44ff6b1afef369eb28 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-05soc/intel/{common,apollolake}: Add checks to handle negative valuesRizwan Qureshi
Fix issues reported by coverity scan in the below files. src/soc/intel/common/block/i2c 1375440: Improper use of negative value 1375441: Improper use of negative value 1375444: Improper use of negative value src/soc/intel/apollolake/i2c.c 1375442: Unsigned compared against 0 Change-Id: Ic65400c934631e3dcd3aa664c24cb451616e7f4d Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/21875 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-05soc/intel/skylake: Add config for mbx command for Intersil VR C-state issuesRizwan Qureshi
Config for activating VR mailbox command for Intersil VR C-state issues. 0 - no mailbox command sent. 1 - VR mailbox command sent for IA/GT rails only. 2 - VR mailbox command sent for IA/GT/SA rails. BUG=b:65499724 BRANCH=none TEST= build and boot soraka. Change-Id: Ibcced31b7ba473ffa7368c90c945d07a81a368d4 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/21680 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-05vendor/intel/skykabylake: Update FSP header files to version 2.7.2Balaji Manigandan B
Update FSP header files to version 2.7.2. New UPDs added FspmUpd.h: *CleanMemory FspsUpd.h: *IslVrCmd *ThreeStrikeCounterDisable Structure member names used to specify memory configuration to MRC have been updated, SoC side romstage code is updated to handle this change. CQ-DEPEND=CL:*460573,CL:*460612,CL:*460592 BUG=b:65499724 BRANCH=None TEST= Build and boot soraka, basic sanity check and suspend resume checks. Change-Id: Ia4eca011bc9a3b1a50e49d6d86a09d05a0cbf151 Signed-off-by: Balaji Manigandan B <balaji.manigandan@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/21679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-10-04chromeec: Remove checks for EC in RODaisuke Nojiri
This patch removes checks that ensure EC to be in RO for recovery boot. We do not need these checks because when recovery is requested automatically (as opposed to manually), we show 'broken' screen where users can only reboot the device or request recovery manually. If recovery is requested, Depthcharge will check whether EC is in RO or not and recovery switch was pressed or not. If it's a legitimate manual recovery, EC should be in RO. Thus, we can trust the recovery button state it reports. This patch removes all calls to google_chromeec_check_ec_image, which is called to avoid duplicate memory training when recovery is requested but EC is in RW. BUG=b:66516882 BRANCH=none CQ-DEPEND=CL:693008 TEST=Boot Fizz. Change-Id: I45a874b73c46ea88cb831485757d194faa9f4c99 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/21711 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-04soc/amd/stoneyridge: Drop some amdlib.h includesKyösti Mälkki
Change-Id: Ief00a74a9ab4cb6783ea17cebc924b5c4852f228 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-10-03soc/intel/cannonlake: change gpio device nameBora Guvendik
TEST=Boot to OS Change-Id: Iace5dc748435b48b50faae6f60a10f1f7ae058ff Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/21758 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-03soc/intel/cannonlake: Disable CPU ratio overrideLijian Zhao
Disable CPU Ratio override as input to FSP Memory init. Change-Id: I4a1df15c619038f17c1bef5b7f53d322e352c56b Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-03soc/intel/cannonlake: add initial ASL methods for SCS, GPIOBora Guvendik
Add ACPI methods for gpio, scs and pcr. TEST=Boot to OS. Change-Id: I0dc31662dd3f5dbb3bda43aa8cf507128facde51 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/21685 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-03soc/intel/cannonlake: Add northbridge dsdt tableLijian Zhao
Add ACPI dsdt table for northbridge, report proper resources in dsdt entries. TEST=Boot up into OS fine. Change-Id: I382d87da087ae7828eaa7ff28bc9597a332ca5bc Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-03soc/intel/cannonlake: Fill the SMI usageLijian Zhao
Add SMM support for Cannonlake on top of common SMM, also include the SMM relocate support. Change-Id: I9aab141c528709b30804d327804c4031c59fcfff Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-03soc/intel/cannonlake: Add lpc pci driverLijian Zhao
1.Add common ITSS support as part of LPC driver init code. 2.Add LPC pci driver for CNL Change-Id: I6c810fd7158e1498664b77eecae22132e2f6878f Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-03soc/intel/skylake: Enable common LPC IPRavi Sarawadi
Enable Skylake to use the new common LPC code. This will help to reduce code duplication and streamline code bring up. Change-Id: I042e459fb7c07f024a7f6a5fe7da13eb5f0dd688 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/20120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-03soc/intel/common/block: Update LPC libRavi Sarawadi
Add support for following functionality: 1. Set up PCH LPC interrupt routing. 2. Set up generic IO decoder range settings. 3. Enable CLKRUN_EN for power gating LPC. Change-Id: Ib9359765f7293210044b411db49163df0418070a Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/21605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-03soc/amd/stoney: Allow alternative placement for AMD FW directoryMartin Roth
Allow the AMD FW directory to be placed at one of the alternative locations within the ROM. BUG=b:65484600 TEST=Assign PSP firmware location, build & test. Change-Id: I9c95b9805c60ab6204750f7929049c7382e0c6cd Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21456 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-10-03soc/amd/stoneyridge: Wait for UART to be readyMarc Jones
The Stoney Ridge UART and AMBA devices must be powered and report power and clock OK prior to using the coreboot serial console. The code used to have a delay to wait for the power and clock, but didn't check the OK bits. This caused long delays on a reboot, as each byte would time out until the console was reset again at romstage. This change also removes the UART reset. The device has just been powered and is in reset already. Testing indicates the reset isn't needed. BUG=b:65853981 TEST=Boot to Chrome OS, run the reboot command, verify that the long delay is gone. Change-Id: I410700df5df255d20b8e5d192c72241dd44cf676 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/21731 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-02amd/stoneyridge: Remove 16MB cbmem assertMarshall Dawson
Do not check for the top of memory being 16MB-aligned near the end of romstage. This is not the expected alignment using the default 8MB SMM region size. BUG=b:67320715 Change-Id: I6bf0b9141232dea1a3b02794fda7af08887df119 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21850 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-02soc/intel/common/block: Move power button SMI functions to common PMC blockShaunak Saha
This patch moves the functions update_pm1_enable and read_pm1_enable to common block PMC. We rename the functions to pmc_update_pm1_enable and pmc_read_pm1_enable to keep semantics consistent. Change-Id: I9a73a6348fc22367ee2e68bf2c31823ebfefc525 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/21755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-02soc/intel/skylake: Use common/block/gpioHannah Williams
Other than switch to use common gpio implementation for skylake based platform, also apply the needed changes for purism board. Change-Id: I06e06dbcb6d0d6fe277dfad57b82aca51f94b099 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/19201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Youness Alaoui <snifikino@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-02amd/stoneyridge: Change SMM setup functionsMarshall Dawson
Remove the APMC-specific initialization call. Make the function which programs the event type not static and call it from the southbridge.c file. Change-Id: I1e3cf898637720fa835de0a6e735c6a65fe2d3a2 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-02amd/stoneyridge: Add PM defintions to southbridge.hMarshall Dawson
Change-Id: I2534ab34f8a8d151e80004ee05d3061f013316b0 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21747 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-23 19:55:59 +0000