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2020-12-25soc/intel/common/gfx: rename and guard graphics_soc_init()Matt DeVillier
Rename to graphics_soc_panel_init, to more accurately convey operations performed by the function. Guard execution so we don't attempt to reconfigure the panel after FSP has already done so. This fixes FSP/GOP display init on APL/GLK, which was broken by attempting to configure the panel after FSP had already done so. Change-Id: I8e68a16b2efb59965077735578b1cc6ffd5a58f0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48884 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-24soc/intel/xeon_sp/cpx: Disable isoch operation for performanceJohnny Lin
Isochronous operation negatively impacts memory performance, as per Intel MLC (Memory Latency Checker) benchmark results. Thus, disable isochronous operation, like analogous UEFI firmware does. The MLC results after disabling isoch: "--max_bandwidth" ALL Reads : 106948.17 3:1 Reads-Writes : 101580.46 2:1 Reads-Writes : 100523.26 1:1 Reads-Writes : 99059.44 Stream-triad like : 97762.47 "--peak_injection_bandwidth" ALL Reads : 105724.3 3:1 Reads-Writes : 100655.8 2:1 Reads-Writes : 99463 1:1 Reads-Writes : 98708 Stream-triad like : 91515 The MLC results before disabling isoch: "--max_bandwidth" ALL Reads : 88824.96 3:1 Reads-Writes : 94820.81 2:1 Reads-Writes : 94867.53 1:1 Reads-Writes : 92567.36 Stream-triad like : 91900.43 "--peak_injection_bandwidth" ALL Reads : 88859.6 3:1 Reads-Writes : 94064 2:1 Reads-Writes : 94186.2 1:1 Reads-Writes : 92516.1 Stream-triad like : 85147.4 TEST=On OCP Delta Lake, verify that MLC benchmark results have improved. Change-Id: I08c22ee001b601e607452b3f23fad969ecb484b4 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48738 Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-23soc/intel/common: Remove unused SOC_INTEL_COMMON_ACPIMarc Jones
Remove the unused SOC_INTEL_COMMON_ACPI Kconfig option. Change-Id: Id62cd44e0f7e4175ae65c9388569231d5c8c1fbc Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-23src/soc/intel/xeon_sp/acpi.c: Remove unnecessary .hMarc Jones
Remove the unnecessary header file includes. Change-Id: I0d849cb236f304b87332aa64b2f10c73cad2d4dd Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2020-12-23Makefile: Add $(xcompile) to specify where to write xcompileRaul E Rangel
This file was being written to the root src directory. It is the only file being written to src during a normal build, while all others are being written to $(obj). I added a new variable to allow specifying the xcompile path. This allows generating a single file if building multiple boards. I also moved the default location into $(obj) so we don't pollute the src directory by default. I also cleaned up the generation of xcompile by removing the unnecessary eval and NOCOMPILE check. I also left .xcompile in distclean so it cleans up stale files. Since .xcompile is written into $(obj), `make clean` will now remove it. The tegra Makefiles are outside of the normal build process, so I just updated those Makefiles to point to the default xcompile location of a normal build. The what-jenkins-does target had to be updated to support these special targets. We generate an xcompile specifically for these targets and pass it into the Makefile. Ideally we should get these targets added to the main build. BUG=b:112267918 TEST=ran `emerge-grunt coreboot` and `make what-jenkins-does` Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia83f234447b977efa824751c9674154b77d606b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/28101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-12-23soc/intel/alderlake: Enable support for extended BIOS windowSubrata Banik
Port commit ba75c4c (soc/intel/tigerlake: Enable support for extended BIOS window) for Alderlake Change-Id: Iaa8464d45884de433cca4f6a250cdd8d4c8f3661 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-23soc/intel/alderlake: Add SPI DMI Destination IDSubrata Banik
Port commit 237afda (src/soc/intel/tigerlake: Add SPI DMI Destination ID) into Alderlake. Change-Id: Ia0b465d405ab3c70b7d4094d32c182cab30fe531 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-22soc/intel/common: Fix XHCI elog driverTim Wawrzynczak
Commit 56fcfb5 misused the PCH_DEVFNs passed to the XHCI elog driver, by passing them directly to pci_s_read_config32. This is incorrect, as it is the wrong PCI devfn encoding to pass to that function. BUG=b:175996770 TEST=abuild Change-Id: Id7c146c1f50ee64a725bd50f9f11a7f159013a2b Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48827 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-22soc/intel/common/block/acpi: Fix get_cores_per_packagePatrick Rudolph
Current implementation uses CPUID 0Bh function that returns the number of logical cores of requested level. The problem with this approach is that this value doesn't change when HyperThreading is disabled (it's in the Intel docs), so it breaks generate_cpu_entries() because `numcpus` ends up being zero due to integer division truncation. - Use MSR 0x35 instead, which returns the correct number of logical processors with and without HT. - Use cpu_read_topology() to gather the required information Tested on Prodrive Hermes, the ACPI code is now generated even with HyperThreading disabled. Change-Id: Id9b985a07cd3f99a823622f766c80ff240ac1188 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48691 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-22soc/intel/cannonlake: Add Iccmax and loadlines for CML-SGaggery Tsai
Following up 3ccae2b7, this patch adds Iccmax and AC/DC loadlines and iPL2 for CML-S CPUs. The information is from CML EDS volume 1, doc #606599 and pdg #610244. Change-Id: Id2797a979a8b6a52a34baae66f95c7136ed1dc72 Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38288 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-22soc/intel/apl/graphics: add missing left-shiftMichael Niewöhner
According to doc# IHD-OS-BXT-Vol 2b-05.17 the cycle delay is in the bit range 8:4 of register PP_CONTROL. The current code writes the value to bits 4:0, though. Correct that by shifting the value left by 4 bits. Change-Id: If407932c847da39b19e307368c9e52ba1c93bccd Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-12-22sb,soc/intel: Drop unnecessary headersKyösti Mälkki
Files under sb/ or soc/ should not have includes that tie those directly to external components like ChromeEC os ChromeOS vendorcode. Change-Id: Ib56eeedaa9d7422e221efa9c8480ed5e12024bca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48765 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-22soc/amd/common/psp: Remove files from bootblockMarshall Dawson
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I8d775d2d813cf92245f3be4d41b3295ca6da18ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/48798 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-22soc/amd/stoneyridge: Remove unused psp.hMarshall Dawson
psp.h was first included when Stoney Ridge began loading the first SMU firmware. That step was later moved from bootblock to romstage. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Id646390ce377143d09455f797de1b149dbb615b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48797 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-22soc/mediatek/mt8192: Do dramc software impedance calibrationHuayang Duan
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: I2c6ffe885717997540a0a9721310e355a3b6a87d Reviewed-on: https://review.coreboot.org/c/coreboot/+/44704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-22soc/mediatek/mt8192: Do EMI init before dram calibrationHuayang Duan
Reference datasheet: External Memory Interface (EMI).pdf, Document No: RH-A-2020-0055. Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: I3b778698a09c999252fef3153ac1e869ea9d90cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/44703 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-12-22soc/mediatek/mt8192: Do memory pll init before calibrationHuayang Duan
Memory PLL is used to provide the basic clock for dram controller and DDRPHY. PLL must be initialized as predefined way. First, enable PLL POWER and ISO, wait at least 30us, release ISO, then configure PLL frequency and enable PLL master switch. At last, enable control ability for SPM to switch between active and idle when system is switched between normal and low power mode. TEST=Confirm Memory PLL frequency is right by frequency meter Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: Ieb4e6cbf19da53d653872b166d3191c7b010dca6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-12-22soc/intel/xeon_sp: Use common block ACPIMarc Jones
Use the common block ACPI to further reduce the duplicate code. Change-Id: If28d75cbb2a88363d70e3ae6a2cace46cb6bbbab Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48248 Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-21soc/intel/xeon_sp/skx: Properly set up MTRR'sArthur Heymans
Don't depend on the MTRR setup left over from FSP-M ExitTempRam. Change-Id: I299123b3cd3c37b4345102c20fda77bf261892a2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2020-12-21soc/intel/xeon_sp: Fix compiling with CONFIG_DEBUG_RESOURCESArthur Heymans
Change-Id: I42ddea2c04bf1ecb2466db3d56d15d51bda486c8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2020-12-21soc/intel/common/block/acpi: Add soc MADT IOAPIC hookMarc Jones
Add a hook for SOCs to provide an IOAPIC MADT table. If the SOC doesn't provide a table then a standard setting is used. Change-Id: Ic818a634e4912d88ef93971deb4da5ab708c9020 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-21soc/intel/common/block/acpi: Make calculate_power() globalMarc Jones
Change static calculate_power() function to global and update the name to common_calculate_power_ratio() for SOC ACPI code use. Change-Id: I0e2d118ad52b36859bfc6029b7dee946193841f4 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48739 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
2020-12-19soc/amd/picasso: move sb_clk_output_48Mhz from acp to fchEric Lai
Move sb_clk_output_48Mhz out of acp. It should be called unconditionally. We may have another device need this clock e.g. superio chip. BUG=b:174121847 BRANCH=zork TEST= build passed Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I30ad6c60066f17cc83e7feb40675610f4853a022 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-18soc/amd/picasso: Add acp_i2s_use_external_48mhz_osc flagEric Lai
If we have use external clock source for I2S, we don't need to enable internal one. Add acp_i2s_use_external_48mhz_osc flag for the project which uses external clock source. BUG=b:174121847 BRANCH=zork TEST= build passed Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ica68ee2da5a05231eb6db0218bd0f19907507273 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48637 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-18soc/amd/cezanne: add GPIO supportFelix Held
This still uses the common GPIO code that supports setting up SMI/SCI support for the GPIOs in all stages, which will get removed in future patches, so for now the SoC's gpio.c needs to be included in all stages. Change-Id: I6c12d1d6c605b7eb063eef62a1f71860f602f8dd Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48565 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-18soc/amd/cezanne: Add SMI supportZheng Bao
Change-Id: I83b9a91cbab297d032292997a4d5768b89fe97dd Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48645 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-17azalia: Use `azalia_enter_reset` functionAngel Pons
Also tidy up some adjacent comments. Change-Id: I2e881900a52e42ab3f43ffe96cfbdcc63ff02e23 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-17soc/intel/common/hda_verb.c: Clarify mask usageAngel Pons
The `azalia_set_bits` will mask out all bits, so just use zero for clarity. The resulting behavior is the same in both cases. Change-Id: I27777f1e836fa973859629d48964060bec02c87a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48357 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-17soc/intel/skylake: Drop duplicate PmConfigPciClockRun configurationBenjamin Doron
coreboot already unconditionally enables CLKRUN_EN in SoC common code. Tested on an out-of-tree Acer Aspire VN7-572G, PCCTL[CLKRUN_EN] of LPC is still enabled. Change-Id: I65e85015bdd0f766ca8021a3d4c0b0d799f0ccc5 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48325 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-17soc/amd/cezanne: add GPIO definitionsFelix Held
Change-Id: I67930267a89ba0c64ec7e40e2bfa30a0618d104b Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-12-17azalia: Use `azalia_exit_reset` functionAngel Pons
Change-Id: I346040eb6531dac6c066a96cd73033aa17f026d0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-17azalia: Replace `hda_find_verb` usesAngel Pons
This function is equivalent to `azalia_find_verb` in its current form, so replace them. Also, adapt and move the function description comment. Change-Id: I40d1e634c31b00bd7808a651990d9bd6f0d054e9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-17azalia: Make `set_bits` function non-staticAngel Pons
There's many copies of this function in the tree. Make the copy in azalia_device.c non-static and rename it to `azalia_set_bits`, then replace all other copies with it. Since azalia_device.c is only built when AZALIA_PLUGIN_SUPPORT is selected, select it where necessary. This has the side-effect of building hda_verb.c from the mainboard directory. If this patch happens to break audio on a mainboard, it's because its hda_verb.c was always wrong but wasn't being compiled. Change-Id: Iff3520131ec7bc8554612969e3a2fe9cdbc9305e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48346 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-17soc/intel/cannonlake: Change mainboard_silicon_init_params argumentPatrick Rudolph
Use FSPS_UPD instead of FSP_S_CONFIG as argument as already done on xeon_sp and denverton_ns. This allows to set test config UPDs from mainboard code as well. Change-Id: I6d67264e22df32b9210ce88b99d6a7a4f6b97ffb Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-12-17drivers: Replace set_vbe_mode_info_validPatrick Rudolph
Currently it's not possible to add multiple graphics driver into one coreboot image. This patch series will fix this issue by providing a single API that multiple graphics driver can use. This is required for platforms that have two graphic cards, but different graphic drivers, like Intel+Aspeed on server platforms or Intel+Nvidia on consumer notebooks. The goal is to remove duplicated fill_fb_framebuffer(), the advertisment of multiple indepent framebuffers in coreboot tables, and better runtime/build time graphic configuration options. Replace set_vbe_mode_info_valid with fb_add_framebuffer_info or fb_new_framebuffer_info_from_edid. Change-Id: I95d1d62385a201c68c6c2527c023ad2292a235c5 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-12-16soc/amd/picasso: Fix the typo in GPIO defineZheng Bao
Change-Id: I8c9eed5d0e320b02382c24304a44e51e89eb6ac5 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-16soc/intel/xeon_sp: Move DMICTL lockArthur Heymans
On SKX FSP-M does not return if this is set too early. Tested on OCP/Tiogapass, boots. Change-Id: Ib8ef7bab36bfd4b62988768753d10b4d7b7d567f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48657 Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-16soc/amd/common/gpio_banks: Drop underscore in __gpioKyösti Mälkki
The local function names were chosen such that they don't collide with <gpio.h> so the prefix is unnecessary. Change-Id: I4799a6d6b87e8081324d88b0773e61cbda0d4cfb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-16soc/mediatek/mt8192: Do the dramc pinmux selectionHuayang Duan
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: I7bc1971646a65db8eef5eb5223c919645c6e8ed9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-16soc/intel/broadwell: Drop unnecessary `sa_dev`Angel Pons
Change-Id: Icc70adb0c3527a082622fd0ab70888e6cdf6b0ed Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46982 Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-16arch/x86: Clean up bootblock assemblyKyösti Mälkki
We have identical gdtptr16 and gdtptr. The reference in gdtptr_offset calculation is not accounted for when considering --gc-sections, so to support linking gdt_init.S separately add dummy use of gdtptr symbol. Realmode execution already accessed gdt that was located outside [_start16bit,_estart16bit] region. Remove latter symbol as the former was not really a start of region, but entry point symbol. With the romcc bootblock solution, entry32.inc may have been linked into romstage before, but the !ENV_BOOTBLOCK case seems obsolete now. Change-Id: I0a3f6aeb217ca4e38b936b8c9ec8b0b69732cbb9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-12-16soc/mediatek/mt8192: Correct return value of VM18 voltageHsin-Hsiung Wang
The voltage of vm18 should be microvolt instead of millivolt. BUG=b:155253454 BRANCH=none TEST=boot asurada correctly Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Change-Id: Iea5b46c1df358dc350506d29cc033d01631b37b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48110 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-16soc/mediatek/mt8192: Keep CONN MCU in reset stateWeiyi Lu
Keep the CONN MCU in reset state to prevent CONN from asserting the clk26m request to SPM. TEST=clk26m request from conn has been released. Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Change-Id: Ia1b706da497ba2827341051459c3628e2ae9240f Reviewed-on: https://review.coreboot.org/c/coreboot/+/46447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-16soc/mediatek/mt8192: Do dramc init settingsHuayang Duan
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: Ie4877b69de1bfa4ff981d8eb386efbddb9e0f5c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-16soc/amd/common: Use only byte access for IOMUXKyösti Mälkki
Change-Id: Ia3c4fb41b5851b1c0ffc6bbec7d1c051e232fc94 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42978 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-16soc/mediatek/mt8192: Enable DCMmtk15698
Enable DCM settings. Change-Id: I5528d176b6bb1f9a5960de981766235510e6ebf1 Signed-off-by: mtk15698 <michael.kao@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-16soc/mediatek/mt8192: ufs: Disable reference clockWenbin Mei
UFS reference clock (refclk) is enabled by default, which will cause the UFSHCI to hold the SPM signal and lead to suspend failure. Since UFS kernel driver is not built-in, disable refclk in coreboot stage. Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com> Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> Change-Id: If11c1b756ad1a0b85f1005f56a6cb4648c687cf0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-16soc/mediatek/mt8192: Initialize audio pll tuner frequencyWeiyi Lu
Add AUDPLL TUNER init code. TEST=Boots correctly on MT8192EVB. Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Change-Id: I1f1b5b55a0a16d42311b16b89b15b31e1aa04670 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-15soc/amd/picasso/smi: add missing bits to GEVENT_MASKFelix Held
GEVENT_MASK should cover all GEVENT pins, but was missing SMITYPE_G_AGPIO9 and SMITYPE_G_AGPIO8. Change-Id: Ia676476e2d2cf468d82d6d90e9fc11d34f56f153 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-12-15soc/amd/common,picasso: Place some ENV_X86 guardsKyösti Mälkki
Base address symbols for ACPIMMIO banks that would not get assigned at runtime must not resolve at linker-stage either. The build of PSP-verstage should pass without the preprocessor macros that have x86-centric view of memory space. Change-Id: I3cb1b5a90023ebc4359835be716c5e3f9451df60 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42523 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-18 04:50:23 +0000