coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2018-09-14	soc/sifive/fu540: Initialize SDRAM	Philipp Hug
2018-09-14	soc/sifive/fu540: Switch clock to 1GHz in romstage	Philipp Hug
2018-09-14	soc/sifive/fu540: create ram_resource with actual memory size	Philipp Hug
2018-09-14	arch/riscv: provide a monotonic timer	Philipp Hug
2018-09-14	soc/sifive/fu540: add SiFive supplied header files for SDRAM initialization	Philipp Hug
2018-09-14	complier.h: add __always_inline and use it in code base	Aaron Durbin
2018-09-13	soc/sifive/fu540: Get SDRAM controller out of reset	Philipp Hug
2018-09-13	soc/sifive/fu540: Update clock settings according SiFive bootloader	Philipp Hug
2018-09-13	uart/sifive: make divisor configurable	Philipp Hug
2018-09-13	src/*/intel/: clarify Kconfig options regarding IFD	Stefan Tauner
2018-09-12	soc/sifive/fu540: Initialize PLL and clock	Philipp Hug
2018-09-12	soc/amd/stoneyridge: Fix more GPIO functions	Jonathan Neuschäfer
2018-09-11	amd/stoneyridge: Enable BERT table generation	Marshall Dawson
2018-09-11	amd/stoneyridge: Set BERT region size when no TSEG used	Marshall Dawson
2018-09-11	soc/intel/baytrail: Remove trailing space in log message	Paul Menzel
2018-09-10	soc/sifive: fix compiler warning	Philipp Hug
2018-09-10	soc/sifive/fu540: Makefile: include mtime_init in ramstage	Philipp Hug
2018-09-10	soc/sifive/fu540: Add driver for OTP memory	Philipp Hug
2018-09-10	soc/intel/cannonlake: Correct number of root ports for CNL PCH H	Maulik V Vaghela
2018-09-10	soc/sifive/fu540: add CLINT support	Xiang Wang
2018-09-10	riscv: update mtime initialization	Xiang Wang
2018-09-10	complier.h: add __noreturn and use it in code base	Aaron Durbin
2018-09-10	soc/intel/skylake: Add support for CmdTriStateDis UPD in devicetree	Shaunak Saha
2018-09-07	amd/stoneyridge: Construct ACPI BERT table	Marshall Dawson
2018-09-07	amd/stoneyridge: Construct BERT region from machine check	Marshall Dawson
2018-09-07	amd/stoneyridge: Create an MCA structure	Marshall Dawson
2018-09-07	amd/stoneyridge: Relocate MCA error identification	Marshall Dawson
2018-09-07	amd/stoneyridge: Adjust memory map for reserved	Marshall Dawson
2018-09-07	fsp_broadwell_de: enable spi console	Okash Khawaja
2018-09-06	soc/intel/cannonlake: Fix Coverity Scan report	Lijian Zhao
2018-09-06	mediatek: Refactor memory test code among similar SoCs	Tristan Shieh
2018-09-06	soc/intel/common: Add function to set BILD bit in RTC	Rizwan Qureshi
2018-09-06	chromeos/gnvs: remove function and naming cleanup	Joel Kitching
2018-09-02	riscv: separately define stack locations at different stages	Xiang Wang
2018-08-31	siemens/mc_apl1: Correct the Tx signal from SATA interface	Mario Scheithauer
2018-08-30	soc/intel/cannonlake: Fix comment errors for SMBUS	Lijian Zhao
2018-08-30	soc/amd/stoneyridge/enable_usbdebug.c: Update pci_ehci_dbg_set_port()	Richard Spiegel
2018-08-30	soc/intel/cannonlake: Update PMC base address for CNP H and LP	Maulik V Vaghela
2018-08-28	soc/intel/cannonlake: Change LPDDR4 to MEMCFG	Lijian Zhao
2018-08-28	siemens/mc_apl1: Extend circuit life by clock gating and power gating	Mario Scheithauer
2018-08-27	intel: Use common HPET table revision function	Marc Jones
2018-08-27	update all FADT version 3.0 to use the get tables function	Marc Jones
2018-08-24	soc/intel/apollolake: Make eMMC max speed configurable	Mario Scheithauer
2018-08-24	soc/cn81xx: Add vboot support	Philipp Deppenwiese
2018-08-24	soc/cavium/cn81xx: Don't directly manipulate devicetree data	Patrick Rudolph
2018-08-24	device_tree/fit: Constify data structures	Patrick Rudolph
2018-08-22	soc/intel/apollolake: Fix logical vs. bitwise operator	John Zhao
2018-08-22	soc/amd/stoneyridge/smihandler.c: Report pending wake event	Richard Spiegel
2018-08-22	cbtable: remove chromeos_acpi from cbtable	Joel Kitching
2018-08-22	acpi: remove CBMEM_ID_ACPI_GNVS_PTR entry	Joel Kitching