coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2020-07-28	soc/amd/picasso: Add controls for SMT and downcoring	Marshall Dawson
2020-07-28	src/soc/amd: Add include <types.h>	Elyes HAOUAS
2020-07-28	soc/amd/picasso: Enable VBNV_BACKUP_TO_FLASH for psp_verstage	Martin Roth
2020-07-28	soc/amd/picasso: Init SPI in psp_verstage	Martin Roth
2020-07-28	soc/amd/picasso/Makefile.inc: force an error if PSPBTLDR_FILE is not set	Ronald G Minnich
2020-07-28	src: Never set ISA Enable on PCI bridges	Angel Pons
2020-07-28	soc/intel/braswell/fadt.c: Use `ACPI_ADDRESS_SPACE_IO` macro	Angel Pons
2020-07-28	broadwell: Factor out PIRQ routing from devicetree	Angel Pons
2020-07-28	soc/intel/cannonlake: Configure SataPwrOptEnable only if SATA is enabled	Felix Singer
2020-07-28	soc/intel/apollolake: Simplify is-device-enabled checks	Felix Singer
2020-07-28	soc/intel/jasperlake: Simplify is-device-enabled checks	Felix Singer
2020-07-28	soc/intel/tigerlake: Simplify is-device-enabled checks	Felix Singer
2020-07-28	Revert "src: Remove unused include <cpu/x86/smm.h>"	Patrick Rudolph
2020-07-27	soc/amd: Use spi_writeX & spi_readX for all spi accesses	Martin Roth
2020-07-27	soc/amd/common: Move spi access functions into their own file	Martin Roth
2020-07-27	soc/amd/picasso: Set __USER_SPACE__ for psp_verstage	Martin Roth
2020-07-27	soc/amd/picasso: make USB over-current pin mapping configurable	Felix Held
2020-07-27	soc/intel/jasperlake: Invoke PCIe root port swapping	Karthikeyan Ramasubramanian
2020-07-26	soc/intel/tigerlake: Disable CPU PCIe in FSP	Shaunak Saha
2020-07-26	soc/intel/tigerlake: Disable VT-d and no DMAR table for pre-QS platform	John Zhao
2020-07-26	soc/intel/common/basecode: Implement CSE update flow	Rizwan Qureshi
2020-07-26	soc/amd/common/block/psp/psp_smm.c: Add missing <string.h>	Elyes HAOUAS
2020-07-26	src/soc/qualcomm: Add include <types.h>	Elyes HAOUAS
2020-07-26	src/soc/mediatek: Add include <types.h>	Elyes HAOUAS
2020-07-26	src/soc/intel: Add include <types.h>	Elyes HAOUAS
2020-07-26	soc/intel/common/gpio_defs: Remove PAD_CFG_NF_BUF_TRIG	Maxim Polyakov
2020-07-26	soc/intel/common/hda: Add HDA ID for Jasper Lake	yan.liu
2020-07-26	soc/intel/jasperlakelake: Rename pch_init() code	Usha P
2020-07-26	src: Update bare access to BOOL CONFIG_ vals to CONFIG()	Martin Roth
2020-07-26	src: Change BOOL CONFIG_ to CONFIG() in comments & strings	Martin Roth
2020-07-26	src: Remove whitespace between 'sizeof' and '('	Elyes HAOUAS
2020-07-26	{sb,soc}/intel/*/.c: Use macros for PCI COMMAND bits	Angel Pons
2020-07-26	soc/amd/common: Refactor and consolidate code for spi base	Martin Roth
2020-07-26	soc/amd/picasso: Update postcode value	Martin Roth
2020-07-26	Kconfig: Remove unnecessary choice names	Martin Roth
2020-07-26	smp/spinlock: Do not define barrier() globally	Kyösti Mälkki
2020-07-26	arch/x86: Move cpu_relax()	Kyösti Mälkki
2020-07-26	cpu,soc/intel: Drop select SMP	Kyösti Mälkki
2020-07-26	src: Remove unused 'include <cbmem.h>'	Elyes HAOUAS
2020-07-26	src: Remove extra lines in license header	Elyes HAOUAS
2020-07-26	skylake boards: Factor out copy-pasted PIRQ routes	Angel Pons
2020-07-26	src: Remove unused include <cpu/x86/smm.h>	Elyes HAOUAS
2020-07-26	amd/picasso: rework USB2 PHY tune parameter handling	Felix Held
2020-07-26	soc/skylake: Configure SATA options only if SATA is enabled	Felix Singer
2020-07-25	soc/amd/picasso: don't apply unconfigured USB2 PHY tune parameters	Felix Held
2020-07-25	soc/intel/baytrail/southcluster.c: Align with Braswell	Angel Pons
2020-07-25	soc/intel/baytrail/include/soc/irq.h: Add braces	Angel Pons
2020-07-25	soc/intel/baytrail: Simplify pattrs definitions	Angel Pons
2020-07-25	soc/intel/baytrail/smm.c: Align with Braswell	Angel Pons
2020-07-25	soc/intel/baytrail/smihandler.c: Align with Braswell	Angel Pons