summaryrefslogtreecommitdiff
path: root/src/soc
AgeCommit message (Collapse)Author
2020-06-19Kconfig: Escape variable to accommodate new Kconfig versionsPatrick Georgi
Kconfig 4.17 started using the $(..) syntax for environment variable expansion while we want to keep expansion to the build system. Older Kconfig versions (like ours) simply drop the escapes, not changing the behavior. While we could let Kconfig expand some of the variables, that only splits the handling in two places, making debugging harder and potentially messing with reproducible builds (e.g. when paths end up in configs), so escape them all. Change-Id: Ibc4087fdd76089352bd8dd0edb1351ec79ea4faa Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2020-06-18soc/amd/picasso/i2c: use config_of_soc()Felix Held
Change-Id: I2ebe072a5c887b16d2a39f029069bc8674f8eaea Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-18soc/amd/picasso/acp: use config_of_soc()Felix Held
Change-Id: I815b013438d66eef6605dba7cfbd96b9a4aff9b2 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-18soc/amd/picasso: Add ability to enable/disable UART to device treeRaul E Rangel
If we are not using the UARTs or they don't have the correct GPIOs configured we should let the mainboard disable them. BUG=b:153001807 TEST=Dump SSDT and see UART device is disabled Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ifc04e36e0ebe5cce4b6cc228c7174dc76f2ffa4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/42327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-06-18soc/amd/picasso: remove AMDFW_OUTSIDE_CBFS optionFelix Held
The option to have amdfw outside of CBFS used dd to write amdfw at a given location overwriting anything that was there before, which may cause the build to fail due to the FMAP header being overwritten resulting in a not too obvious error that the image is a legacy image without FMAP header. Mandolin was the only board using this functionality, but I fixed the placement of components in the flash image there, so that amdfw can just be placed in CBFS avoiding those problems. Change-Id: I0f3abab9d3939da43e1681d5cfe2c8d494402acf Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42438 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-18soc/intel,chromeos: Fix EC RO/RW status in GNVSKyösti Mälkki
For baytrail and braswell, explicitly initialise it to ACTIVE_ECFW_RO without ChromeEC. For broadwell and skylake, fix it to report actual google_ec_running_ro() status. Change-Id: I30236c41c9261fd9f8565e1c5fdbfe6f46114e28 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42389 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-18soc/intel/tigerlake: Enable FSP-S compressionKarthikeyan Ramasubramanian
Use LZ4 compression technique to compress FSP-S. This provides some SPI ROM space savings (~36 KiB) in each CBFS. FSP-M is XIP and hence not compressed. LZ4 is chosen over LZMA since the decompression saves ~25 ms for an extra overhead of ~1KiB. LZ4 Compression: fsps.bin 0xe6fc0 fsp 254262 LZ4 (290816 decompressed) LZ4 Decompression: 17:starting LZ4 decompress (ignore for x86) 712,361 (1,072) 18:finished LZ4 decompress (ignore for x86) 750,695 (38,334) LZMA Compression: fsps.bin 0xe6fc0 fsp 253415 LZMA (290816 decompressed) LZMA Decompression: 15:starting LZMA decompress (ignore for x86) 707,696 (1,150) 16:finished LZMA decompress (ignore for x86) 767,763 (60,067) BUG=b:158034451 TEST=Build and boot volteer mainboard. Change-Id: I91e33eb7b688b5383f3a0075a28ac21250314973 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42444 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-18soc/intel/jasperlake: Enable FSP-S compressionKarthikeyan Ramasubramanian
Use LZ4 compression technique to compress FSP-S. This provides some SPI ROM space savings(~60 KiB) in each CBFS. FSP-M is XIP and hence not compressed. LZ4 is chosen over LZMA since the decompression saves ~50 ms for an extra overhead of ~1.5 KiB. LZ4 Compression: fsps.bin 0xa9fc0 fsp 203423 LZ4 (262144 decompressed) LZ4 Decompression: 17:starting LZ4 decompress (ignore for x86) 433,550 (1,154) 18:finished LZ4 decompress (ignore for x86) 461,620 (28,069) LZMA Compression: fsps.bin 0xa9fc0 fsp 202132 LZMA (262144 decompressed) LZMA Decompression: 15:starting LZMA decompress (ignore for x86) 478,448 (1,174) 16:finished LZMA decompress (ignore for x86) 557,725 (79,277) BUG=b:158034451 TEST=Build and boot waddledoo mainboard. Change-Id: I416b1d91d7f4836b1e9c641b0fe07b39876364ba Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42445 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-18soc/intel/cannonlake: Enable FSP-S compressionKarthikeyan Ramasubramanian
Use LZMA compression technique to compress FSP-S. This provides some SPI ROM space savings(~27 KiB) in each CBFS. FSP-M is XIP and hence not compressed. LZMA is chosen over LZ4 since it provides extra space savings of ~1 KiB for the decompression overhead of ~7 ms. LZMA Compression: fsps.bin 0xd1fc0 fsp 190132 LZMA (217088 decompressed) LZMA Decompression: 15:starting LZMA decompress (ignore for x86) 343,289 (417) 16:finished LZMA decompress (ignore for x86) 373,922 (30,632) LZ4 Compression: fsps.bin 0xd1fc0 fsp 191310 LZ4 (217088 decompressed) LZ4 Decompression: 17:starting LZ4 decompress (ignore for x86) 345,676 (581) 18:finished LZ4 decompress (ignore for x86) 369,101 (23,424) BUG=b:158034451 TEST=Build and boot helios mainboard. Change-Id: Ic0d0d81c81eaa365f3dbfdd2e00ac76cea287387 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42446 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-18soc/intel: remove unused dptf.asl file and other definesSumeet R Pawnikar
Remove unused cannonlake dptf.asl file and cleanup defines from apollolake dptf.asl file as per soc/intel/common/acpi code changes for dptf. BUG=None BRANCH=None TEST=Build and boot on the system Change-Id: I4c8bf2bd5da9d5881e7690bff34816b19dd96072 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-18soc/intel/common: make dptf acpi device ids configurableSumeet R Pawnikar
Make dptf acpi device ids configurable for thermal functionality as per soc/intel/common/acpi code changes for dptf. BUG=None BRANCH=None TEST=Build and boot on volteer system Change-Id: I5161d19dc663cdb9a7b004bb681059c9af2aaf4f Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42039 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-06-18soc/intel/common: Introduce ASL2.0 syntaxAlexey Buyanov
Fix last legacy ASL syntax match in acpi/pcr.asl BUG=none TEST=Deltan coreboot binary remains the same after the changes are applied Signed-off-by: Alexey Buyanov <alexey.buyanov@intel.com> Change-Id: Ia1021851b42b8fad52b3197d9003056d3dd2db04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42437 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17Revert "soc/amd/picasso: Reconfigure SPI speeds after FSP-S has run"Furquan Shaikh
This reverts commit d5f1e0f9734273f79ebd313bb6a17eda04c22c11. Reason for revert: FSP-S is now fixed to not touch the SPI configuration registers. Thus, coreboot does not need to reconfigure SPI after FSP-S has run. BUG=b:153506142 TEST=Verified that SPI configuration registers look the same before and after FSP-S has run. em100 works fine without any additional changes in coreboot to reconfigure SPI. Change-Id: I4832e62e0331aa39abe0cca7725915262bb2cf83 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin Frodsham <justin.frodsham@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-17soc/amd/picasso: rename PICASSO_UART Kconfig optionFelix Held
The PICASSO_UART Kconfig option is about using the internal MMIO UART controllers in Picasso for console, so rename it to PICASSO_CONSOLE_UART Change-Id: I38ac9ee96af826fe49307b4d0e055a43fcbd4334 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-17soc/amd/picasso: fix build if PICASSO_UART is unsetFurquan Shaikh
This change includes uart.c in bootblock, romstage, ramstage and verstage unconditionally because this file is handling more than just the UART console configuration. This allows boards to take advantage of picasso_uart_mmio_ops even if PICASSO_UART is not selected. uart_platform_base and uart_platform_refclk mustn't be provided if PICASSO_UART is unset, so add an #if around those functions. BUG=b:158346697 TEST=Mandolin builds again. Change-Id: If1173034b0d2ed32f77241768e1e8abb208aac3a Signed-off-by: Furquan Shaikh <furquan@google.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42339 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17soc/soch/intel/tigerlake: Integrate PCIe hot-plug config UPDWonkyu Kim
This patch adds support for enabling/disabling PCIe hot-plug via a chip config option PcieRpHotPlug, which is copied to the corresponding FSP-S UPD. BUG=b:156879564 BRANCH=none TEST=Boot Volteer/RVP with FSP log and check hotplug enabled/disabled Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I4c0187644b6ca9735f1b159e110e3466af14ff71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41794 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17soc/intel/cannonlake/vr_config: Add CFL defaults to TDC powerlimitPatrick Rudolph
Add CFL defaults for VR TDC config and provide Iccmax for additional Xeon CPUs tested on the Prodrive/Hermes board. Based on the following Intel documents: * Document Number 570805 (XEON E EDS Vol 1) * Document Number 337344 (CFL Datasheet Vol 1) * Document Number 571264 (CFL CNP PDG) Change-Id: I681de076318fb647c44cc8b8c42eb297018cc540 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-06-17soc/intel/cannonlake: Use table instead of switch-casePatrick Rudolph
This makes future changes easier to review. Change-Id: I5d67801a46a1613fbc7f813e94933fa30c1b92df Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41507 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-06-16soc/amd/picasso/include/soc/memmap.c: Add missing <stdint.h>Elyes HAOUAS
include <stdint.h> for 'uint32_t'. Change-Id: I8768b7f0692ed703a060dc0406b517dc001cc25d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42338 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-16cpu/x86: Define MTRR_CAP_PRMRRKyösti Mälkki
Followups will remove remaining cases of PRMRR_SUPPORTED and SMRR_SUPPORTED in the tree. Change-Id: I7f8c7d98f5e83a45cc0787c245cdcaf8fab176d5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-16soc/amd: Replace enable_smi_generation()Kyösti Mälkki
Change-Id: I9846df34fd2b6b15549fa33d3eda137544fa4219 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-16sb,soc/intel: Replace smm_southbridge_enable_smi()Kyösti Mälkki
Change-Id: I8a2e8b0c104d9e08f07aeb6a2c32106480ace3e5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-16soc/intel/common: Replace smm_soutbridge_enable(SMI_FLAGS)Kyösti Mälkki
Change-Id: I8c4dc5ab91891de9737189bd7ae86df18d86f758 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-16sb/intel: Remove spurious HAVE_SMI_HANDLER testKyösti Mälkki
There are no side-effects in calling acpi_is_wakeup_s3() and apm_control() is a no-op with HAVE_SMI_HANDLER=n. Change-Id: Ia9195781955cc5fa96d0690aa7735fc590e527e4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41986 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-16arch/x86: Create helper for APM_CNT SMI triggersKyösti Mälkki
Attempts to write to APM_CNT IO port should always be guarded with a test to verify SMI handler has been installed. Immediate followup removes redundant HAVE_SMI_HANDLER tests. Change-Id: If3fb0f1a8b32076f1d9f3fea9f817dd4b093ad98 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41971 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-15soc/amd/common/block/acpimmio: Update acpimmio for psp_verstageMartin Roth
Because the PSP maps the MMIO addresses that are used to non- deterministic addresses, the accesses need to be able to find the address at runtime. BUG=b:158124527 TEST=Build & boot with Trembyle Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I68305e0f31956c57bfdee42025bdfe938703e82d Reviewed-on: https://review.coreboot.org/c/coreboot/+/42061 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-15arch/x86: Remove NO_FIXED_XIP_ROM_SIZEKyösti Mälkki
The variable SETUP_XIP_CACHE provides us a working alternative. Change-Id: I6e3befedbbc7967b71409640dc81a0c2a9b3e511 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41821 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-14soc/amd/picasso/graphics: implement map_oprom_vendev_revMartin Roth
Picasso, Dali, and Pollock iGPU share the same PCI device ID, but need different video BIOSes. This checks the vendor & device IDs along with the revision and selects the correct video BIOS to use. Also add the second VGA BIOS for Raven2-based SoCs and change all VGA BIOS IDs to the format including the revision number. Since SeaBIOS still expects the CBFS file name without the revision ID, it won't find the VBIOS any more. As a temporary workaround add the VBIOS for the silicon it will run on as VGA_BIOS_DGPU_*. Change-Id: I8f48ecc3fbffddd21d1f830fbee26a09ac351e1c Signed-off-by: Martin Roth <martinroth@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://chromium-review.googlesource.com/2040455 Reviewed-by: Raul E Rangel <rrangel@chromium.org> Reviewed-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com> Reviewed-by: Justin Frodsham <justin.frodsham@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-14soc/amd/picasso/aoac: Add wait_for_aoac_enabledRaul E Rangel
This way drivers can wait for their devices to be enabled. I also rewrote enable_aoac_devices to take advantage of wait_for_aoac_enabled. BUG=b:153001807 TEST=Trembyle builds Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I8e653c857e164f90439e0028e08aa9608d4eca94 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-14soc/amd/picasso/aoac: Set the Target Device State when powering onRaul E Rangel
If the OS sets the target device state to D3, we need to clear it so we can reestablish register access. BUG=b:153001807 TEST=Boot trembyle with I2C powered off and see it power back on. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: If9bd1b7cfa7b8d074226c4dcdefc1a44cad8b940 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42325 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-14soc/amd/picasso: Move aoac functions to new fileRaul E Rangel
This functionality is needed in the PSP and I can't include all of southbridge.c. BUG=b:153001807 TEST=Made sure trembyle still compiles Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I3a38c655588d7836e1bd033e958a505774de871e Reviewed-on: https://review.coreboot.org/c/coreboot/+/42324 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-14soc/amd/picasso: Explicitly disable legacy UARTRaul E Rangel
The legacy UARTs are supposed to default to off according to the documentation (PPR for AMD Family 17h Model 18h). But legacy UART Range_0 is enabled after reset. The PSP might be enabling it or the documentation might be wrong. Having it enabled causes problems though. We have ACPI nodes defining MMIO UARTs, and the kernel also probes for legacy UARTs. This results in two drivers accessing the same device, one via MMIO and one via IO. I suspect this was the cause of the garbage serial output. Before the change you would see the following in the console: [ 0.741108] serial8250: ttyS3 at I/O 0x2e8 (irq = 3, base_baud = 115200) is a 16550A After this change, we no longer see it. BUG=b:152079780, b:157858890 TEST=Boot trembyle and make sure serial is still working. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I9d837e449b961dbb55d1301d2107838e26b3f892 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-06-14soc/intel/xeon_sp/cpx: select CACHE_MRC_SETTINGSJonathan Zhang
FSP_NV_STORAGE HOB is supported in CPX-SP FSP ww22 release. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Ida06fa7f7c7937f4e66a83fdecbca8bc208d626f Reviewed-on: https://review.coreboot.org/c/coreboot/+/42024 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-14soc/amd/picasso: correct MCFG ACPI tableAaron Durbin
The start and end bus number in the MCFG ACPI table is inclusive. Therefore, the number of buses decoded needs to be subtracted by 1. BUG=b:158874061 Change-Id: Ic773bc1e0ccaa99af45d1a53919f6480887fa37e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42329 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-14soc/intel/tigerlake: enable CPU_INTEL_COMMONAlex Levin
Since we plan to use VMX, enable CPU_INTEL_COMMON. BUG=b:157388365 TEST=tested on Volteer Signed-off-by: Alex Levin <levinale@chromium.org> Change-Id: I5e7bdb4310947dd8a94ee554834a67ce94377ea5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-14soc/amd/picasso: Increase SMM_RESERVED_SIZEMarshall Dawson
Correct a message of "Error: Can't add stage_cache 57a9e101 to imd". ramstage is 0xffc90 and adding FSP-S (0x50000) failed. Increase the reserved region of SMRAM to accommodate both images. BUG=b:158704095 TEST=Boot Mandolin and check console log Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I51595d80d4779e995ec2a26e395cf95d666a309e Reviewed-on: https://review.coreboot.org/c/coreboot/+/42314 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-14soc/intel/cannonlake/acpi: Capitalize hex number to unify with SkylakePaul Menzel
diff -ur src/soc/intel/skylake/acpi/pch_hda.asl src/soc/intel/cannonlake/acpi/pch_hda.asl --- src/soc/intel/skylake/acpi/pch_hda.asl 2020-05-12 11:17:42.780293920 +0200 +++ src/soc/intel/cannonlake/acpi/pch_hda.asl 2020-05-12 11:17:42.756294169 +0200 @@ -4,7 +4,7 @@ Device (HDAS) { - Name (_ADR, 0x001F0003) + Name (_ADR, 0x001f0003) Name (_DDN, "Audio Controller") Name (UUID, ToUUID ("A69F886E-6CEB-4594-A41F-7B5DCE24C553")) Change-Id: Ic8b874163ddede72a75e0dc94021683bca3e7859 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-06-14soc/intel/xeon_sp/cpx: configure FSP-M UPD parametersJonathan Zhang
Configure FSP-M UPD parameters. TESTED=Boot CPX-SP based server. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com> Change-Id: I2d0762a742d8803c7396034e3244120c1e8ece67 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-06-14soc/intel/xeon_sp/cpx: add cpu entries in ssdtJonathan Zhang
Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com> Change-Id: I4d057a7c385ca563bfcc7ad44f651ad1f8ca003c Reviewed-on: https://review.coreboot.org/c/coreboot/+/42059 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-06-14soc/intel/xeon_sp/cpx: fix MADT ACPI tableJonathan Zhang
Fix MADT table generation to keep IIO stack design in consideration. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com> Change-Id: If1bf6e39db545e227e9867aa8d24f7db1d820216 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40383 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-06-14soc/intel/xeon_sp/cpx: add IIO stack resources to DSDTJonathan Zhang
Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com> Change-Id: Iec89551a8b88a683db5857e3a6ab4af5e446cb5b Reviewed-on: https://review.coreboot.org/c/coreboot/+/42058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-06-14soc/intel/xeon_sp/cpx: add NUMA ACPI tablesJonathan Zhang
Add NUMA ACPI tables: SRAT, SLIT. TESTED=Boot CPX-SP based server, check /sys/firmware/acpi/tables for SRAT/SLIT tables. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com> Change-Id: I3374b802afd2d001e841afd85e7ae07bc27c01ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/41902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-06-14soc/amd/picasso/acpi: Add a wrapper method WAL1 for calling ALIB function 1Furquan Shaikh
ALIB function 1 needs to be called every time there is a change in AC/DC state of the system. This change adds a wrapper method that can be called by PNOT (method to notify system power state change) to report to ALIB that system power state has changed i.e. AC <-> DC. Additionally, this change drops the call to ALIB from _INI method since the PWRS object might not be initialized correctly at that point. Instead EC makes a call to PNOT when PWRS is initialized. This wrapper also fixes the value of power state being passed into ALIB. ALIB expects 0 = AC and 1 = DC. On the other hand, PWRS reports 1 as AC and 0 as DC. WAL1() takes care of inverting the PWRS state before passing into ALIB. BUG=b:157752693 TEST=Verified that WAL1() gets called on AC connect/disconnect. Steps followed: $ echo 1 > /sys/module/acpi/parameters/aml_debug_output $ dmesg -w | grep ACPI [ 76.306947] ACPI Debug: "EC: AC DISCONNECTED" [ 76.307064] ACPI Debug: "ALIB call: func 1 params 0x03 0x00 0x01" [ 82.264946] ACPI Debug: "EC: GOT PD EVENT" [ 82.539833] ACPI Debug: "EC: GOT PD EVENT" [ 82.753721] ACPI Debug: "EC: GOT PD EVENT" [ 82.843676] ACPI Debug: "EC: GOT PD EVENT" [ 82.970596] ACPI Debug: "EC: AC CONNECTED" [ 82.970659] ACPI Debug: "ALIB call: func 1 params 0x03 0x00 0x00" [ 83.047598] ACPI Debug: "EC: GOT PD EVENT" [ 84.804733] ACPI Debug: "EC: GOT PD EVENT" [ 86.317934] ACPI Debug: "EC: GOT PD EVENT" [ 86.385920] ACPI Debug: "EC: GOT PD EVENT" [ 86.515830] ACPI Debug: "EC: AC DISCONNECTED" [ 86.515922] ACPI Debug: "ALIB call: func 1 params 0x03 0x00 0x01" [ 90.089062] ACPI Debug: "EC: GOT PD EVENT" [ 90.357914] ACPI Debug: "EC: GOT PD EVENT" [ 90.573812] ACPI Debug: "EC: GOT PD EVENT" [ 90.662744] ACPI Debug: "EC: GOT PD EVENT" [ 90.788706] ACPI Debug: "EC: AC CONNECTED" [ 90.788835] ACPI Debug: "ALIB call: func 1 params 0x03 0x00 0x00" [ 90.865675] ACPI Debug: "EC: GOT PD EVENT" [ 92.621793] ACPI Debug: "EC: GOT PD EVENT" Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I1f2ade28ca35378ebf4647d8df3d2ea4d0b08096 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-13soc/intel/common: Introduce ASL2.0 syntaxAlexey Buyanov
Modify soc/intel/common .asl files to comply with ASL2.0 syntax for better code readability and clarity BUG=none BRANCH=none TEST= Deltan coreboot binary remains the same after the changes are applied Signed-off-by: Alexey Buyanov <alexey.buyanov@intel.com> Change-Id: I8f95cf88f499d9f9bdd8c80c95af52f8fd886cdf Reviewed-on: https://review.coreboot.org/c/coreboot/+/42083 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-13soc/amd/picasso: Place early stages and data buffers at the bottom of DRAMFurquan Shaikh
This change updates memlayout.ld for Picasso to place all early stages (bootblock, romstage, FSP-M, verstage) and data buffers (vboot workbuf, APOB, preram-cbmem console, timestamp, early BSP stack) at the bottom of DRAM starting at 32MiB. This uses static allocation for most components by defining Kconfig variables for base and size. It relies on the linker to complain if any of the assumptions are broken. This also allows romstage to use linker symbols for _early_reserved_dram and _eearly_reserved_dram to store information in CBMEM about the early DRAM usage by coreboot before ramstage starts execution. This allows ramstage to reserve this memory region in BIOS tables so that S3 resume can reuse the same space without corrupting OS memory. BUG=b:155322763 TEST=Verified memory reported by coreboot: Writing coreboot table at 0xcc656000 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000a0000-00000000000fffff: RESERVED 3. 0000000000100000-0000000001ffffff: RAM 4. 0000000002000000-000000000223ffff: RESERVED 5. 0000000002240000-00000000cc512fff: RAM 6. 00000000cc513000-00000000cc6bffff: CONFIGURATION TABLES 7. 00000000cc6c0000-00000000cc7c7fff: RAMSTAGE 8. 00000000cc7c8000-00000000cd7fffff: CONFIGURATION TABLES 9. 00000000cd800000-00000000cfffffff: RESERVED 10. 00000000f8000000-00000000fbffffff: RESERVED 11. 0000000100000000-000000042f33ffff: RAM 12. 000000042f340000-000000042fffffff: RESERVED Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I009e1ea71b5b5a8e65eba16911897b2586ccfdb6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42264 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-13soc/amd/picasso: Add custom memlayout.ld fileFurquan Shaikh
This change copies src/arch/x86/memlayout.ld file to src/soc/amd/picasso/ and sets MEMLAYOUT_LD_FILE config variable to point to this newly added file. Unused elements from the memlayout.ld file are dropped and path to early_dram.ld is updated to include the one from src/arch/x86. BUG=b:155322763 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I59bf5f93b712407ddcc9fb8a46167936c6c28a76 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-13treewide: Add Kconfig variable MEMLAYOUT_LD_FILEFurquan Shaikh
This change defines a Kconfig variable MEMLAYOUT_LD_FILE which allows SoC/mainboard to provide a linker file for the platform. x86 already provides a default memlayout.ld under src/arch/x86. With this new Kconfig variable, it is possible for the SoC/mainboard code for x86 to provide a custom linker file as well. Makefile.inc is updated for all architectures to use this new Kconfig variable instead of assuming memlayout.ld files under a certain path. All non-x86 boards used memlayout.ld under mainboard directory. However, a lot of these boards were simply including the memlayout from SoC. So, this change also updates these mainboards and SoCs to define the Kconfig as required. BUG=b:155322763 TEST=Verified that abuild with --timeless option results in the same coreboot.rom image for all boards. Change-Id: I6a7f96643ed0519c93967ea2c3bcd881a5d6a4d6 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42292 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-12soc/intel/tigerlake: Add devicetree support to change PCH VR settingsVenkata Krishna Nimmagadda
For Tiger Lake platforms, this patch set provides a way to override PCH external VR settings and ext rail voltage/current through devicetree. This enables setting of optimal settings for FIVRs for a particular PCH type. BUG=None BRANCH=None TEST=Build and boot volteer. Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com> Change-Id: Ic55472d392f27d153656afbe8692be7e243bb374 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41424 Reviewed-by: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-12soc/amd/picasso: Reconfigure SPI speeds after FSP-S has runFurquan Shaikh
This change reconfigures SPI speeds after FSP-S has run since FSP-S is currently configuring the SPI frequency when it should not. Until FSP-S behavior is fixed, this workaround needs to be applied. BUG=b:153506142 TEST=Verified that em100 works fine. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Id9b8330c6f82c7162ff91e8cc10160fdd8cfedab Reviewed-on: https://review.coreboot.org/c/coreboot/+/42267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-11soc/amd/picasso/uart: fix possible out of bounds accessFelix Held
Found-by: Coverity CID 1429769, 1429777 Change-Id: Ide188379a34c769c929bf7832fd94a7004c09a64 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42253 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-02 00:56:59 +0000